Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 4 | #include <bootsplash.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 5 | #include <bootstate.h> |
| 6 | #include <console/console.h> |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 7 | #include <cpu/x86/mp.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 12 | #include <intelblocks/acpi.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 13 | #include <intelblocks/cfg.h> |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 14 | #include <intelblocks/fast_spi.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 15 | #include <intelblocks/msr.h> |
Subrata Banik | f699c14 | 2018-06-08 17:57:37 +0530 | [diff] [blame] | 16 | #include <intelblocks/p2sb.h> |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 17 | #include <intelblocks/power_limit.h> |
Duncan Laurie | 4c8fbc0 | 2018-03-26 02:19:58 -0700 | [diff] [blame] | 18 | #include <intelblocks/xdci.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 19 | #include <fsp/api.h> |
| 20 | #include <fsp/util.h> |
Dinesh Gehlot | 58cc96f | 2023-01-17 04:01:13 +0000 | [diff] [blame] | 21 | #include <gpio.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 22 | #include <intelblocks/cpulib.h> |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 23 | #include <intelblocks/itss.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 24 | #include <intelblocks/pmclib.h> |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 25 | #include <intelblocks/systemagent.h> |
Sean Rhodes | c397f00 | 2022-02-07 15:05:12 +0000 | [diff] [blame] | 26 | #include <option.h> |
Furquan Shaikh | d2c2f83 | 2018-11-07 10:24:31 -0800 | [diff] [blame] | 27 | #include <soc/cpu.h> |
| 28 | #include <soc/heci.h> |
| 29 | #include <soc/intel/common/vbt.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 30 | #include <soc/iomap.h> |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 31 | #include <soc/itss.h> |
Subrata Banik | 05865b8 | 2022-01-07 13:01:18 +0000 | [diff] [blame] | 32 | #include <soc/msr.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 34 | #include <soc/pm.h> |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 35 | #include <soc/systemagent.h> |
Furquan Shaikh | d2c2f83 | 2018-11-07 10:24:31 -0800 | [diff] [blame] | 36 | #include <spi-generic.h> |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 37 | #include <timer.h> |
Felix Singer | e59ae10 | 2019-05-02 13:57:57 +0200 | [diff] [blame] | 38 | #include <soc/ramstage.h> |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 39 | #include <soc/soc_chip.h> |
Felix Held | 82faefb | 2021-10-20 20:50:58 +0200 | [diff] [blame] | 40 | #include <types.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 41 | |
| 42 | #include "chip.h" |
| 43 | |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 44 | #define DUAL_ROLE_CFG0 0x80d8 |
| 45 | #define SW_VBUS_VALID_MASK (1 << 24) |
| 46 | #define SW_IDPIN_EN_MASK (1 << 21) |
| 47 | #define SW_IDPIN_MASK (1 << 20) |
| 48 | #define SW_IDPIN_HOST (0 << 20) |
| 49 | #define DUAL_ROLE_CFG1 0x80dc |
| 50 | #define DRD_MODE_MASK (1 << 29) |
| 51 | #define DRD_MODE_HOST (1 << 29) |
| 52 | |
John Zhao | 57aa8b6 | 2019-01-14 09:15:50 -0800 | [diff] [blame] | 53 | #define CFG_XHCLKGTEN 0x8650 |
| 54 | /* Naking USB2.0 EPs for Backbone Clock Gating and PLL Shutdown */ |
| 55 | #define NUEFBCGPS (1 << 28) |
| 56 | /* SRAM Power Gate Enable */ |
| 57 | #define SRAMPGTEN (1 << 27) |
| 58 | /* SS Link PLL Shutdown Enable */ |
| 59 | #define SSLSE (1 << 26) |
| 60 | /* USB2 PLL Shutdown Enable */ |
| 61 | #define USB2PLLSE (1 << 25) |
| 62 | /* IOSF Sideband Trunk Clock Gating Enable */ |
| 63 | #define IOSFSTCGE (1 << 24) |
| 64 | /* BIT[23:20] HS Backbone PXP Trunk Clock Gate Enable */ |
| 65 | #define HSTCGE (1 << 23 | 1 << 22) |
| 66 | /* BIT[19:16] SS Backbone PXP Trunk Clock Gate Enable */ |
| 67 | #define SSTCGE (1 << 19 | 1 << 18 | 1 << 17) |
| 68 | /* XHC Ignore_EU3S */ |
| 69 | #define XHCIGEU3S (1 << 15) |
| 70 | /* XHC Frame Timer Clock Shutdown Enable */ |
| 71 | #define XHCFTCLKSE (1 << 14) |
| 72 | /* XHC Backbone PXP Trunk Clock Gate In Presence of ISOCH EP */ |
| 73 | #define XHCBBTCGIPISO (1 << 13) |
| 74 | /* XHC HS Backbone PXP Trunk Clock Gate U2 non RWE */ |
| 75 | #define XHCHSTCGU2NRWE (1 << 12) |
| 76 | /* BIT[11:10] XHC USB2 PLL Shutdown Lx Enable */ |
| 77 | #define XHCUSB2PLLSDLE (1 << 11 | 1 << 10) |
| 78 | /* BIT[9:8] HS Backbone PXP PLL Shutdown Ux Enable */ |
| 79 | #define HSUXDMIPLLSE (1 << 9) |
| 80 | /* BIT[7:5] SS Backbone PXP PLL shutdown Ux Enable */ |
| 81 | #define SSPLLSUE (1 << 6) |
| 82 | /* XHC Backbone Local Clock Gating Enable */ |
| 83 | #define XHCBLCGE (1 << 4) |
| 84 | /* HS Link Trunk Clock Gating Enable */ |
| 85 | #define HSLTCGE (1 << 3) |
| 86 | /* SS Link Trunk Clock Gating Enable */ |
| 87 | #define SSLTCGE (1 << 2) |
| 88 | /* IOSF Backbone Trunk Clock Gating Enable */ |
| 89 | #define IOSFBTCGE (1 << 1) |
| 90 | /* IOSF Gasket Backbone Local Clock Gating Enable */ |
| 91 | #define IOSFGBLCGE (1 << 0) |
| 92 | |
Marx Wang | abc17d1 | 2020-04-07 16:58:38 +0800 | [diff] [blame] | 93 | #define CFG_XHCPMCTRL 0x80a4 |
| 94 | /* BIT[7:4] LFPS periodic sampling for USB3 Ports */ |
| 95 | #define LFPS_PM_DISABLE_MASK 0xFFFFFF0F |
| 96 | |
Duncan Laurie | bf713b0 | 2018-05-07 15:33:18 -0700 | [diff] [blame] | 97 | const char *soc_acpi_name(const struct device *dev) |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 98 | { |
| 99 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 100 | return "PCI0"; |
| 101 | |
Duncan Laurie | bf713b0 | 2018-05-07 15:33:18 -0700 | [diff] [blame] | 102 | if (dev->path.type == DEVICE_PATH_USB) { |
| 103 | switch (dev->path.usb.port_type) { |
| 104 | case 0: |
| 105 | /* Root Hub */ |
| 106 | return "RHUB"; |
| 107 | case 2: |
| 108 | /* USB2 ports */ |
| 109 | switch (dev->path.usb.port_id) { |
| 110 | case 0: return "HS01"; |
| 111 | case 1: return "HS02"; |
| 112 | case 2: return "HS03"; |
| 113 | case 3: return "HS04"; |
| 114 | case 4: return "HS05"; |
| 115 | case 5: return "HS06"; |
| 116 | case 6: return "HS07"; |
| 117 | case 7: return "HS08"; |
Furquan Shaikh | ad62b9a | 2019-01-30 22:47:17 -0800 | [diff] [blame] | 118 | case 8: |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 119 | if (CONFIG(SOC_INTEL_GEMINILAKE)) |
Furquan Shaikh | ad62b9a | 2019-01-30 22:47:17 -0800 | [diff] [blame] | 120 | return "HS09"; |
Duncan Laurie | bf713b0 | 2018-05-07 15:33:18 -0700 | [diff] [blame] | 121 | } |
| 122 | break; |
| 123 | case 3: |
| 124 | /* USB3 ports */ |
| 125 | switch (dev->path.usb.port_id) { |
| 126 | case 0: return "SS01"; |
| 127 | case 1: return "SS02"; |
| 128 | case 2: return "SS03"; |
| 129 | case 3: return "SS04"; |
| 130 | case 4: return "SS05"; |
| 131 | case 5: return "SS06"; |
| 132 | } |
| 133 | break; |
| 134 | } |
| 135 | return NULL; |
| 136 | } |
| 137 | |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 138 | if (dev->path.type != DEVICE_PATH_PCI) |
| 139 | return NULL; |
| 140 | |
| 141 | switch (dev->path.pci.devfn) { |
| 142 | /* DSDT: acpi/northbridge.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 143 | case SA_DEVFN_ROOT: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 144 | return "MCHC"; |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 145 | /* DSDT: acpi/xhci.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 146 | case PCH_DEVFN_XHCI: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 147 | return "XHCI"; |
| 148 | /* DSDT: acpi/pch_hda.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 149 | case PCH_DEVFN_HDA: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 150 | return "HDAS"; |
| 151 | /* DSDT: acpi/lpss.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 152 | case PCH_DEVFN_UART0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 153 | return "URT1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 154 | case PCH_DEVFN_UART1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 155 | return "URT2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 156 | case PCH_DEVFN_UART2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 157 | return "URT3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 158 | case PCH_DEVFN_UART3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 159 | return "URT4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 160 | case PCH_DEVFN_SPI0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 161 | return "SPI1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 162 | case PCH_DEVFN_SPI1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 163 | return "SPI2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 164 | case PCH_DEVFN_SPI2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 165 | return "SPI3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 166 | case PCH_DEVFN_PWM: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 167 | return "PWM"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 168 | case PCH_DEVFN_I2C0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 169 | return "I2C0"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 170 | case PCH_DEVFN_I2C1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 171 | return "I2C1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 172 | case PCH_DEVFN_I2C2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 173 | return "I2C2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 174 | case PCH_DEVFN_I2C3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 175 | return "I2C3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 176 | case PCH_DEVFN_I2C4: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 177 | return "I2C4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 178 | case PCH_DEVFN_I2C5: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 179 | return "I2C5"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 180 | case PCH_DEVFN_I2C6: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 181 | return "I2C6"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 182 | case PCH_DEVFN_I2C7: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 183 | return "I2C7"; |
| 184 | /* Storage */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 185 | case PCH_DEVFN_SDCARD: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 186 | return "SDCD"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 187 | case PCH_DEVFN_EMMC: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 188 | return "EMMC"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 189 | case PCH_DEVFN_SDIO: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 190 | return "SDIO"; |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 191 | /* PCIe */ |
Venkateswarlu Vinjamuri | f03c63e | 2018-04-12 10:13:43 -0700 | [diff] [blame] | 192 | case PCH_DEVFN_PCIE1: |
| 193 | return "RP03"; |
Venkateswarlu Vinjamuri | efeb690 | 2018-04-09 11:14:42 -0700 | [diff] [blame] | 194 | case PCH_DEVFN_PCIE5: |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 195 | return "RP01"; |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | return NULL; |
| 199 | } |
| 200 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 201 | static struct device_operations pci_domain_ops = { |
| 202 | .read_resources = pci_domain_read_resources, |
| 203 | .set_resources = pci_domain_set_resources, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 204 | .scan_bus = pci_domain_scan_bus, |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 205 | .acpi_name = &soc_acpi_name, |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 206 | .acpi_fill_ssdt = ssdt_set_above_4g_pci, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 207 | }; |
| 208 | |
Arthur Heymans | 584d5e1 | 2023-02-01 08:06:04 +0100 | [diff] [blame] | 209 | struct device_operations apl_cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 210 | .read_resources = noop_read_resources, |
| 211 | .set_resources = noop_set_resources, |
Arthur Heymans | 829e8e6 | 2023-01-30 19:09:34 +0100 | [diff] [blame] | 212 | .init = mp_cpu_bus_init, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 213 | .acpi_fill_ssdt = generate_cpu_entries, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 214 | }; |
| 215 | |
Arthur Heymans | 584d5e1 | 2023-02-01 08:06:04 +0100 | [diff] [blame] | 216 | struct device_operations glk_cpu_bus_ops = { |
| 217 | .read_resources = noop_read_resources, |
| 218 | .set_resources = noop_set_resources, |
| 219 | .acpi_fill_ssdt = generate_cpu_entries, |
| 220 | }; |
| 221 | |
Elyes HAOUAS | 06e8315 | 2018-05-24 22:48:14 +0200 | [diff] [blame] | 222 | static void enable_dev(struct device *dev) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 223 | { |
| 224 | /* Set the operations if it is a special bus type */ |
Lee Leahy | 4430f9f | 2017-03-09 10:00:30 -0800 | [diff] [blame] | 225 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 226 | dev->ops = &pci_domain_ops; |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 227 | else if (dev->path.type == DEVICE_PATH_GPIO) |
| 228 | block_gpio_enable(dev); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 229 | } |
| 230 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 231 | /* |
| 232 | * If the PCIe root port at function 0 is disabled, |
| 233 | * the PCIe root ports might be coalesced after FSP silicon init. |
| 234 | * The below function will swap the devfn of the first enabled device |
| 235 | * in devicetree and function 0 resides a pci device |
| 236 | * so that it won't confuse coreboot. |
| 237 | */ |
| 238 | static void pcie_update_device_tree(unsigned int devfn0, int num_funcs) |
| 239 | { |
Elyes HAOUAS | 06e8315 | 2018-05-24 22:48:14 +0200 | [diff] [blame] | 240 | struct device *func0; |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 241 | unsigned int devfn; |
| 242 | int i; |
| 243 | unsigned int inc = PCI_DEVFN(0, 1); |
| 244 | |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 245 | func0 = pcidev_path_on_root(devfn0); |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 246 | if (func0 == NULL) |
| 247 | return; |
| 248 | |
| 249 | /* No more functions if function 0 is disabled. */ |
| 250 | if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) |
| 251 | return; |
| 252 | |
| 253 | devfn = devfn0 + inc; |
| 254 | |
| 255 | /* |
Elyes HAOUAS | 0f82c12 | 2019-12-04 19:23:50 +0100 | [diff] [blame] | 256 | * Increase function by 1. |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 257 | * Then find first enabled device to replace func0 |
| 258 | * as that port was move to func0. |
| 259 | */ |
| 260 | for (i = 1; i < num_funcs; i++, devfn += inc) { |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 261 | struct device *dev = pcidev_path_on_root(devfn); |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 262 | if (dev == NULL) |
| 263 | continue; |
| 264 | |
| 265 | if (!dev->enabled) |
| 266 | continue; |
| 267 | /* Found the first enabled device in given dev number */ |
| 268 | func0->path.pci.devfn = dev->path.pci.devfn; |
| 269 | dev->path.pci.devfn = devfn0; |
| 270 | break; |
| 271 | } |
| 272 | } |
| 273 | |
| 274 | static void pcie_override_devicetree_after_silicon_init(void) |
| 275 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 276 | pcie_update_device_tree(PCH_DEVFN_PCIE1, 4); |
| 277 | pcie_update_device_tree(PCH_DEVFN_PCIE5, 2); |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 278 | } |
| 279 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 280 | /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */ |
| 281 | static void set_sci_irq(void) |
| 282 | { |
Kyösti Mälkki | 4af4e7f | 2019-07-14 05:50:20 +0300 | [diff] [blame] | 283 | struct soc_intel_apollolake_config *cfg; |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 284 | uint32_t scis; |
| 285 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 286 | cfg = config_of_soc(); |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 287 | |
| 288 | /* Change only if a device tree entry exists. */ |
| 289 | if (cfg->sci_irq) { |
| 290 | scis = soc_read_sci_irq_select(); |
| 291 | scis &= ~SCI_IRQ_SEL; |
| 292 | scis |= (cfg->sci_irq << SCI_IRQ_ADJUST) & SCI_IRQ_SEL; |
| 293 | soc_write_sci_irq_select(scis); |
| 294 | } |
| 295 | } |
| 296 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 297 | static void soc_init(void *data) |
| 298 | { |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 299 | struct soc_power_limits_config *soc_config; |
| 300 | config_t *config; |
| 301 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 302 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 303 | * default policy that doesn't honor boards' requirements. */ |
| 304 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 305 | |
Karthikeyan Ramasubramanian | 6629b4b | 2019-05-01 10:22:22 -0600 | [diff] [blame] | 306 | /* |
| 307 | * Clear the GPI interrupt status and enable registers. These |
| 308 | * registers do not get reset to default state when booting from S5. |
| 309 | */ |
| 310 | gpi_clear_int_cfg(); |
| 311 | |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 312 | fsp_silicon_init(); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 313 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 314 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 315 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 316 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 317 | /* override 'enabled' setting in device tree if needed */ |
| 318 | pcie_override_devicetree_after_silicon_init(); |
| 319 | |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 320 | /* |
| 321 | * Keep the P2SB device visible so it and the other devices are |
| 322 | * visible in coreboot for driver support and PCI resource allocation. |
| 323 | * There is a UPD setting for this, but it's more consistent to use |
| 324 | * hide and unhide symmetrically. |
| 325 | */ |
| 326 | p2sb_unhide(); |
| 327 | |
Uwe Poeche | d2d9021 | 2022-05-23 12:06:28 +0200 | [diff] [blame] | 328 | config = config_of_soc(); |
| 329 | /* Set RAPL MSR for Package power limits */ |
| 330 | soc_config = &config->power_limits_config; |
| 331 | set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 332 | |
| 333 | /* |
| 334 | * FSP-S routes SCI to IRQ 9. With the help of this function you can |
| 335 | * select another IRQ for SCI. |
| 336 | */ |
| 337 | set_sci_irq(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 338 | } |
| 339 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 340 | static void soc_final(void *data) |
| 341 | { |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 342 | /* Make sure payload/OS can't trigger global reset */ |
Michael Niewöhner | 1c6ea92 | 2019-11-02 12:20:53 +0100 | [diff] [blame] | 343 | pmc_global_reset_disable_and_lock(); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 344 | } |
| 345 | |
Lee Leahy | bab8be2 | 2017-03-09 09:53:58 -0800 | [diff] [blame] | 346 | static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) |
| 347 | { |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 348 | switch (dev->path.pci.devfn) { |
Maxim Polyakov | 7b98e3e | 2020-02-16 11:51:57 +0300 | [diff] [blame] | 349 | case PCH_DEVFN_NPK: |
| 350 | /* |
| 351 | * Disable this device in the parse_devicetree_setting() function |
| 352 | * in romstage.c |
| 353 | */ |
| 354 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 355 | case PCH_DEVFN_ISH: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 356 | silconfig->IshEnable = 0; |
| 357 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 358 | case PCH_DEVFN_SATA: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 359 | silconfig->EnableSata = 0; |
| 360 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 361 | case PCH_DEVFN_PCIE5: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 362 | silconfig->PcieRootPortEn[0] = 0; |
| 363 | silconfig->PcieRpHotPlug[0] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 364 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 365 | case PCH_DEVFN_PCIE6: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 366 | silconfig->PcieRootPortEn[1] = 0; |
| 367 | silconfig->PcieRpHotPlug[1] = 0; |
| 368 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 369 | case PCH_DEVFN_PCIE1: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 370 | silconfig->PcieRootPortEn[2] = 0; |
| 371 | silconfig->PcieRpHotPlug[2] = 0; |
| 372 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 373 | case PCH_DEVFN_PCIE2: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 374 | silconfig->PcieRootPortEn[3] = 0; |
| 375 | silconfig->PcieRpHotPlug[3] = 0; |
| 376 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 377 | case PCH_DEVFN_PCIE3: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 378 | silconfig->PcieRootPortEn[4] = 0; |
| 379 | silconfig->PcieRpHotPlug[4] = 0; |
| 380 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 381 | case PCH_DEVFN_PCIE4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 382 | silconfig->PcieRootPortEn[5] = 0; |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 383 | silconfig->PcieRpHotPlug[5] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 384 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 385 | case PCH_DEVFN_XHCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 386 | silconfig->Usb30Mode = 0; |
| 387 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 388 | case PCH_DEVFN_XDCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 389 | silconfig->UsbOtg = 0; |
| 390 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 391 | case PCH_DEVFN_I2C0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 392 | silconfig->I2c0Enable = 0; |
| 393 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 394 | case PCH_DEVFN_I2C1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 395 | silconfig->I2c1Enable = 0; |
| 396 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 397 | case PCH_DEVFN_I2C2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 398 | silconfig->I2c2Enable = 0; |
| 399 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 400 | case PCH_DEVFN_I2C3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 401 | silconfig->I2c3Enable = 0; |
| 402 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 403 | case PCH_DEVFN_I2C4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 404 | silconfig->I2c4Enable = 0; |
| 405 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 406 | case PCH_DEVFN_I2C5: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 407 | silconfig->I2c5Enable = 0; |
| 408 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 409 | case PCH_DEVFN_I2C6: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 410 | silconfig->I2c6Enable = 0; |
| 411 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 412 | case PCH_DEVFN_I2C7: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 413 | silconfig->I2c7Enable = 0; |
| 414 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 415 | case PCH_DEVFN_UART0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 416 | silconfig->Hsuart0Enable = 0; |
| 417 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 418 | case PCH_DEVFN_UART1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 419 | silconfig->Hsuart1Enable = 0; |
| 420 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 421 | case PCH_DEVFN_UART2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 422 | silconfig->Hsuart2Enable = 0; |
| 423 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 424 | case PCH_DEVFN_UART3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 425 | silconfig->Hsuart3Enable = 0; |
| 426 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 427 | case PCH_DEVFN_SPI0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 428 | silconfig->Spi0Enable = 0; |
| 429 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 430 | case PCH_DEVFN_SPI1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 431 | silconfig->Spi1Enable = 0; |
| 432 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 433 | case PCH_DEVFN_SPI2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 434 | silconfig->Spi2Enable = 0; |
| 435 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 436 | case PCH_DEVFN_SDCARD: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 437 | silconfig->SdcardEnabled = 0; |
| 438 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 439 | case PCH_DEVFN_EMMC: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 440 | silconfig->eMMCEnabled = 0; |
| 441 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 442 | case PCH_DEVFN_SDIO: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 443 | silconfig->SdioEnabled = 0; |
| 444 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 445 | case PCH_DEVFN_SMBUS: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 446 | silconfig->SmbusEnable = 0; |
| 447 | break; |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 448 | #if !CONFIG(SOC_INTEL_GEMINILAKE) |
Werner Zeh | de3ace0 | 2019-01-15 08:03:43 +0100 | [diff] [blame] | 449 | case SA_DEVFN_IPU: |
| 450 | silconfig->IpuEn = 0; |
| 451 | break; |
Sean Rhodes | e06ded8 | 2022-02-17 14:44:32 +0000 | [diff] [blame] | 452 | #else |
| 453 | case PCH_DEVFN_CNVI: |
| 454 | silconfig->CnviMode = 0; |
| 455 | break; |
Sean Rhodes | 9088b68 | 2022-06-08 21:41:53 +0100 | [diff] [blame] | 456 | case PCH_DEVFN_UFS: |
| 457 | silconfig->UfsEnabled = 0; |
| 458 | break; |
Werner Zeh | de3ace0 | 2019-01-15 08:03:43 +0100 | [diff] [blame] | 459 | #endif |
Nico Huber | 4074ce0 | 2019-01-31 16:45:04 +0100 | [diff] [blame] | 460 | case PCH_DEVFN_HDA: |
| 461 | silconfig->HdaEnable = 0; |
| 462 | break; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 463 | default: |
| 464 | printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", |
| 465 | PCI_SLOT(dev->path.pci.devfn), |
| 466 | PCI_FUNC(dev->path.pci.devfn)); |
| 467 | break; |
| 468 | } |
| 469 | } |
| 470 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 471 | static void parse_devicetree(FSP_S_CONFIG *silconfig) |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 472 | { |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 473 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 474 | |
| 475 | if (!dev) { |
| 476 | printk(BIOS_ERR, "Could not find root device\n"); |
| 477 | return; |
| 478 | } |
| 479 | /* Only disable bus 0 devices. */ |
| 480 | for (dev = dev->bus->children; dev; dev = dev->sibling) { |
| 481 | if (!dev->enabled) |
| 482 | disable_dev(dev, silconfig); |
| 483 | } |
| 484 | } |
| 485 | |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 486 | static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config |
| 487 | *cfg, FSP_S_CONFIG *silconfig) |
| 488 | { |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 489 | #if !CONFIG(SOC_INTEL_GEMINILAKE) /* GLK FSP does not have these fields in FspsUpd.h yet */ |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 490 | uint8_t port; |
| 491 | |
| 492 | for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { |
Maxim Polyakov | 6704049 | 2020-02-16 11:51:57 +0300 | [diff] [blame] | 493 | if (cfg->usb_config_override) { |
| 494 | if (!cfg->usb2_port[port].enable) |
| 495 | continue; |
| 496 | |
| 497 | silconfig->PortUsb20Enable[port] = 1; |
| 498 | silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin; |
| 499 | } |
| 500 | |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 501 | if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0) |
| 502 | silconfig->PortUsb20PerPortTxPeHalf[port] = |
| 503 | cfg->usb2eye[port].Usb20PerPortTxPeHalf; |
| 504 | |
| 505 | if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0) |
| 506 | silconfig->PortUsb20PerPortPeTxiSet[port] = |
| 507 | cfg->usb2eye[port].Usb20PerPortPeTxiSet; |
| 508 | |
| 509 | if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0) |
| 510 | silconfig->PortUsb20PerPortTxiSet[port] = |
| 511 | cfg->usb2eye[port].Usb20PerPortTxiSet; |
| 512 | |
| 513 | if (cfg->usb2eye[port].Usb20HsSkewSel != 0) |
| 514 | silconfig->PortUsb20HsSkewSel[port] = |
| 515 | cfg->usb2eye[port].Usb20HsSkewSel; |
| 516 | |
| 517 | if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0) |
| 518 | silconfig->PortUsb20IUsbTxEmphasisEn[port] = |
| 519 | cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; |
| 520 | |
| 521 | if (cfg->usb2eye[port].Usb20PerPortRXISet != 0) |
| 522 | silconfig->PortUsb20PerPortRXISet[port] = |
| 523 | cfg->usb2eye[port].Usb20PerPortRXISet; |
| 524 | |
| 525 | if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0) |
| 526 | silconfig->PortUsb20HsNpreDrvSel[port] = |
| 527 | cfg->usb2eye[port].Usb20HsNpreDrvSel; |
| 528 | } |
Maxim Polyakov | 6704049 | 2020-02-16 11:51:57 +0300 | [diff] [blame] | 529 | |
| 530 | if (cfg->usb_config_override) { |
| 531 | for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) { |
| 532 | if (!cfg->usb3_port[port].enable) |
| 533 | continue; |
| 534 | |
| 535 | silconfig->PortUsb30Enable[port] = 1; |
| 536 | silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin; |
| 537 | } |
| 538 | } |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 539 | #endif |
| 540 | } |
| 541 | |
| 542 | static void glk_fsp_silicon_init_params_cb( |
| 543 | struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) |
| 544 | { |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 545 | #if CONFIG(SOC_INTEL_GEMINILAKE) |
Seunghwan Kim | f7fd9b1 | 2019-01-24 16:17:44 +0900 | [diff] [blame] | 546 | uint8_t port; |
| 547 | |
Sean Rhodes | 3a260ad | 2022-02-16 16:50:55 +0000 | [diff] [blame] | 548 | /* |
| 549 | * UsbPerPortCtl was retired in Fsp 2.0.0+, so PDO programming must be |
| 550 | * enabled to configure individual ports in what Fsp thinks is PEI. |
| 551 | */ |
| 552 | silconfig->UsbPdoProgramming = cfg->usb_config_override; |
| 553 | |
Seunghwan Kim | f7fd9b1 | 2019-01-24 16:17:44 +0900 | [diff] [blame] | 554 | for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { |
Sean Rhodes | 3a260ad | 2022-02-16 16:50:55 +0000 | [diff] [blame] | 555 | if (cfg->usb_config_override) { |
| 556 | silconfig->PortUsb20Enable[port] = cfg->usb2_port[port].enable; |
| 557 | silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin; |
| 558 | } |
| 559 | |
Seunghwan Kim | f7fd9b1 | 2019-01-24 16:17:44 +0900 | [diff] [blame] | 560 | if (!cfg->usb2eye[port].Usb20OverrideEn) |
| 561 | continue; |
| 562 | |
| 563 | silconfig->Usb2AfePehalfbit[port] = |
| 564 | cfg->usb2eye[port].Usb20PerPortTxPeHalf; |
| 565 | silconfig->Usb2AfePetxiset[port] = |
| 566 | cfg->usb2eye[port].Usb20PerPortPeTxiSet; |
| 567 | silconfig->Usb2AfeTxiset[port] = |
| 568 | cfg->usb2eye[port].Usb20PerPortTxiSet; |
| 569 | silconfig->Usb2AfePredeemp[port] = |
| 570 | cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; |
| 571 | } |
| 572 | |
Sean Rhodes | 3a260ad | 2022-02-16 16:50:55 +0000 | [diff] [blame] | 573 | if (cfg->usb_config_override) { |
| 574 | for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) { |
| 575 | silconfig->PortUsb30Enable[port] = cfg->usb3_port[port].enable; |
| 576 | silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin; |
| 577 | } |
| 578 | } |
| 579 | |
Subrata Banik | 54a3417 | 2021-06-09 03:54:58 +0530 | [diff] [blame] | 580 | silconfig->Gmm = is_devfn_enabled(SA_GLK_DEVFN_GMM); |
Shamile Khan | c4276a3 | 2018-03-14 18:09:19 -0700 | [diff] [blame] | 581 | |
| 582 | /* On Geminilake, we need to override the default FSP PCIe de-emphasis |
| 583 | * settings using the device tree settings. This is because PCIe |
| 584 | * de-emphasis is enabled by default and Thunderpeak PCIe WiFi detection |
| 585 | * requires de-emphasis disabled. If we make this change common to both |
| 586 | * Apollolake and Geminilake, then we need to add mainboard device tree |
| 587 | * de-emphasis settings of 1 to Apollolake systems. |
| 588 | */ |
| 589 | memcpy(silconfig->PcieRpSelectableDeemphasis, |
| 590 | cfg->pcie_rp_deemphasis_enable, |
| 591 | sizeof(silconfig->PcieRpSelectableDeemphasis)); |
Srinidhi N Kaushik | 5af546c | 2018-05-14 23:33:55 -0700 | [diff] [blame] | 592 | /* |
| 593 | * FSP does not know what the clock requirements are for the |
| 594 | * device on SPI bus, hence it should not modify what coreboot |
| 595 | * has set up. Hence skipping in FSP. |
| 596 | */ |
| 597 | silconfig->SkipSpiPCP = 1; |
John Zhao | e673e5c | 2018-10-30 15:12:11 -0700 | [diff] [blame] | 598 | |
| 599 | /* |
| 600 | * FSP provides UPD interface to execute IPC command. In order to |
| 601 | * improve boot performance, configure PmicPmcIpcCtrl for PMC to program |
| 602 | * PMIC PCH_PWROK delay. |
John Zhao | 91600a3 | 2019-01-10 12:13:38 -0800 | [diff] [blame] | 603 | */ |
John Zhao | e673e5c | 2018-10-30 15:12:11 -0700 | [diff] [blame] | 604 | silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl; |
John Zhao | 91600a3 | 2019-01-10 12:13:38 -0800 | [diff] [blame] | 605 | |
| 606 | /* |
| 607 | * Options to disable XHCI Link Compliance Mode. |
| 608 | */ |
| 609 | silconfig->DisableComplianceMode = cfg->DisableComplianceMode; |
John Zhao | 9a4beb4 | 2019-01-28 16:04:35 -0800 | [diff] [blame] | 610 | |
| 611 | /* |
| 612 | * Options to change USB3 ModPhy setting for Integrated Filter value. |
| 613 | */ |
| 614 | silconfig->ModPhyIfValue = cfg->ModPhyIfValue; |
| 615 | |
| 616 | /* |
| 617 | * Options to bump USB3 LDO voltage with 40mv. |
| 618 | */ |
| 619 | silconfig->ModPhyVoltageBump = cfg->ModPhyVoltageBump; |
| 620 | |
| 621 | /* |
| 622 | * Options to adjust PMIC Vdd2 voltage. |
| 623 | */ |
| 624 | silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage; |
Sean Rhodes | 5d2b1e6 | 2022-06-08 12:29:01 +0100 | [diff] [blame] | 625 | |
| 626 | /* FSP should let coreboot set subsystem IDs, which are read/write-once */ |
| 627 | silconfig->SiSVID = 0; |
| 628 | silconfig->SiSSID = 0; |
| 629 | silconfig->HgSubSystemId = 0; |
Srinidhi N Kaushik | 5af546c | 2018-05-14 23:33:55 -0700 | [diff] [blame] | 630 | #endif |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 631 | } |
| 632 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 633 | void __weak mainboard_devtree_update(struct device *dev) |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 634 | { |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 635 | /* Override dev tree settings per board */ |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 636 | } |
| 637 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 638 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 639 | { |
Lee Leahy | 1d20fe7 | 2017-03-09 09:50:28 -0800 | [diff] [blame] | 640 | FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
Kyösti Mälkki | 4af4e7f | 2019-07-14 05:50:20 +0300 | [diff] [blame] | 641 | struct soc_intel_apollolake_config *cfg; |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 642 | struct device *dev; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 643 | |
| 644 | /* Load VBT before devicetree-specific config. */ |
Patrick Georgi | 2257959 | 2017-10-06 17:36:09 +0200 | [diff] [blame] | 645 | silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 646 | |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 647 | dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 648 | cfg = config_of(dev); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 649 | |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 650 | mainboard_devtree_update(dev); |
| 651 | |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 652 | /* Parse device tree and disable unused device*/ |
| 653 | parse_devicetree(silconfig); |
| 654 | |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 655 | memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin, |
| 656 | sizeof(silconfig->PcieRpClkReqNumber)); |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 657 | |
Furquan Shaikh | 2cfc862 | 2018-03-14 21:43:04 -0700 | [diff] [blame] | 658 | memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, |
| 659 | sizeof(silconfig->PcieRpHotPlug)); |
| 660 | |
Nico Huber | 8885529 | 2018-11-27 15:13:22 +0100 | [diff] [blame] | 661 | switch (cfg->serirq_mode) { |
| 662 | case SERIRQ_QUIET: |
| 663 | silconfig->SirqEnable = 1; |
| 664 | silconfig->SirqMode = 0; |
| 665 | break; |
| 666 | case SERIRQ_CONTINUOUS: |
| 667 | silconfig->SirqEnable = 1; |
| 668 | silconfig->SirqMode = 1; |
| 669 | break; |
| 670 | case SERIRQ_OFF: |
| 671 | default: |
| 672 | silconfig->SirqEnable = 0; |
| 673 | break; |
| 674 | } |
| 675 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 676 | if (cfg->emmc_tx_cmd_cntl != 0) |
| 677 | silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; |
| 678 | if (cfg->emmc_tx_data_cntl1 != 0) |
| 679 | silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; |
| 680 | if (cfg->emmc_tx_data_cntl2 != 0) |
| 681 | silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2; |
| 682 | if (cfg->emmc_rx_cmd_data_cntl1 != 0) |
| 683 | silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1; |
| 684 | if (cfg->emmc_rx_strobe_cntl != 0) |
| 685 | silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; |
| 686 | if (cfg->emmc_rx_cmd_data_cntl2 != 0) |
| 687 | silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; |
Mario Scheithauer | 9116eb6 | 2018-08-23 11:39:19 +0200 | [diff] [blame] | 688 | if (cfg->emmc_host_max_speed != 0) |
| 689 | silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed; |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 690 | |
Sean Rhodes | de198bb | 2022-05-19 15:34:35 +0100 | [diff] [blame] | 691 | memcpy(silconfig->SataPortsHotPlug, cfg->SataPortsHotPlug, |
| 692 | sizeof(silconfig->SataPortsHotPlug)); |
| 693 | |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 694 | silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; |
| 695 | |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 696 | /* Disable monitor mwait since it is broken due to a hardware bug |
Cole Nelson | f357c25 | 2017-05-16 11:38:59 -0700 | [diff] [blame] | 697 | * without a fix. Specific to Apollolake. |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 698 | */ |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 699 | if (!CONFIG(SOC_INTEL_GEMINILAKE)) |
Cole Nelson | f357c25 | 2017-05-16 11:38:59 -0700 | [diff] [blame] | 700 | silconfig->MonitorMwaitEnable = 0; |
Bora Guvendik | 60cc75d | 2016-07-25 14:44:51 -0700 | [diff] [blame] | 701 | |
Martin Roth | c25c1eb | 2020-07-24 12:26:21 -0600 | [diff] [blame] | 702 | silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); |
Venkateswarlu Vinjamuri | 1a5e32c | 2016-10-31 17:15:30 -0700 | [diff] [blame] | 703 | |
Sean Rhodes | 4b966b5 | 2022-09-21 08:52:42 +0100 | [diff] [blame] | 704 | /* coreboot handles the lockdown */ |
| 705 | silconfig->LockDownGlobalSmi = 0; |
| 706 | silconfig->BiosLock = 0; |
| 707 | silconfig->BiosInterface = 0; |
| 708 | silconfig->WriteProtectionEnable[0] = 0; |
| 709 | silconfig->SpiEiss = 0; |
| 710 | silconfig->RtcLock = 0; |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 711 | |
| 712 | /* Enable Audio clk gate and power gate */ |
| 713 | silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; |
| 714 | silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; |
Elyes HAOUAS | 6dc9d03 | 2020-02-16 16:22:52 +0100 | [diff] [blame] | 715 | /* BIOS config lockdown Audio clk and power gate */ |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 716 | silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 717 | if (CONFIG(SOC_INTEL_GEMINILAKE)) |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 718 | glk_fsp_silicon_init_params_cb(cfg, silconfig); |
| 719 | else |
| 720 | apl_fsp_silicon_init_params_cb(cfg, silconfig); |
Duncan Laurie | 4c8fbc0 | 2018-03-26 02:19:58 -0700 | [diff] [blame] | 721 | |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 722 | silconfig->UsbOtg = xdci_can_enable(PCH_DEVFN_XDCI); |
Werner Zeh | 279afdc | 2019-02-01 12:32:51 +0100 | [diff] [blame] | 723 | |
Angel Pons | 320f2c1 | 2020-09-02 15:11:37 +0200 | [diff] [blame] | 724 | silconfig->VmxEnable = CONFIG(ENABLE_VMX); |
| 725 | |
Sean Rhodes | 9d894b8 | 2022-05-26 22:20:41 +0100 | [diff] [blame] | 726 | /* Enable enhanced C-states */ |
| 727 | silconfig->C1e = cfg->enhanced_cstates; |
| 728 | |
Werner Zeh | 279afdc | 2019-02-01 12:32:51 +0100 | [diff] [blame] | 729 | /* Set VTD feature according to devicetree */ |
Sean Rhodes | c397f00 | 2022-02-07 15:05:12 +0000 | [diff] [blame] | 730 | silconfig->VtdEnable = get_uint_option("vtd", cfg->enable_vtd); |
Felix Singer | e59ae10 | 2019-05-02 13:57:57 +0200 | [diff] [blame] | 731 | |
Subrata Banik | 54a3417 | 2021-06-09 03:54:58 +0530 | [diff] [blame] | 732 | silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
Michael Niewöhner | 9b8d28f | 2019-10-26 10:44:33 +0200 | [diff] [blame] | 733 | |
Benjamin Doron | bbb8123 | 2020-06-28 02:43:53 +0000 | [diff] [blame] | 734 | silconfig->PavpEnable = CONFIG(PAVP); |
| 735 | |
Mario Scheithauer | b11f381 | 2022-01-26 11:49:10 +0100 | [diff] [blame] | 736 | /* SATA config */ |
Sean Rhodes | 5777995 | 2022-05-19 15:35:31 +0100 | [diff] [blame] | 737 | if (is_devfn_enabled(PCH_DEVFN_SATA)) { |
Mario Scheithauer | b11f381 | 2022-01-26 11:49:10 +0100 | [diff] [blame] | 738 | silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport); |
Mario Scheithauer | f165bbdc | 2023-05-22 14:44:27 +0200 | [diff] [blame] | 739 | silconfig->SpeedLimit = cfg->sata_speed; |
Sean Rhodes | 5777995 | 2022-05-19 15:35:31 +0100 | [diff] [blame] | 740 | memcpy(silconfig->SataPortsEnable, cfg->SataPortsEnable, |
| 741 | sizeof(silconfig->SataPortsEnable)); |
| 742 | } |
Mario Scheithauer | b11f381 | 2022-01-26 11:49:10 +0100 | [diff] [blame] | 743 | |
Sean Rhodes | 48f69da | 2022-06-08 21:30:26 +0100 | [diff] [blame] | 744 | /* Sata Power Optimisation */ |
| 745 | silconfig->SataPwrOptEnable = !(cfg->SataPwrOptimizeDisable); |
| 746 | |
Sean Rhodes | 2683108 | 2022-05-19 15:06:15 +0100 | [diff] [blame] | 747 | /* 8254 Timer */ |
| 748 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 749 | silconfig->Timer8254ClkSetting = use_8254; |
| 750 | |
Sean Rhodes | 5d2b1e6 | 2022-06-08 12:29:01 +0100 | [diff] [blame] | 751 | /* FSP should let coreboot set subsystem IDs, which are read/write-once */ |
| 752 | silconfig->SubSystemVendorId = 0; |
| 753 | silconfig->SubSystemId = 0; |
| 754 | |
Felix Singer | e59ae10 | 2019-05-02 13:57:57 +0200 | [diff] [blame] | 755 | mainboard_silicon_init_params(silconfig); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 756 | } |
| 757 | |
| 758 | struct chip_operations soc_intel_apollolake_ops = { |
| 759 | CHIP_NAME("Intel Apollolake SOC") |
John Zhao | 57aa8b6 | 2019-01-14 09:15:50 -0800 | [diff] [blame] | 760 | .enable_dev = &enable_dev, |
| 761 | .init = &soc_init, |
| 762 | .final = &soc_final |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 763 | }; |
| 764 | |
Subrata Banik | 05865b8 | 2022-01-07 13:01:18 +0000 | [diff] [blame] | 765 | static void soc_enable_untrusted_mode(void *unused) |
| 766 | { |
| 767 | /* |
| 768 | * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120 |
| 769 | * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode. |
| 770 | */ |
| 771 | msr_set(MSR_POWER_MISC, ENABLE_IA_UNTRUSTED); |
| 772 | } |
| 773 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 774 | static void drop_privilege_all(void) |
| 775 | { |
| 776 | /* Drop privilege level on all the CPUs */ |
Subrata Banik | 05865b8 | 2022-01-07 13:01:18 +0000 | [diff] [blame] | 777 | if (mp_run_on_all_cpus(&soc_enable_untrusted_mode, NULL) != CB_SUCCESS) |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 778 | printk(BIOS_ERR, "failed to enable untrusted mode\n"); |
| 779 | } |
| 780 | |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 781 | static void configure_xhci_host_mode_port0(void) |
| 782 | { |
| 783 | uint32_t *cfg0; |
| 784 | uint32_t *cfg1; |
| 785 | const struct resource *res; |
| 786 | uint32_t reg; |
| 787 | struct stopwatch sw; |
| 788 | struct device *xhci_dev = PCH_DEV_XHCI; |
| 789 | |
| 790 | printk(BIOS_INFO, "Putting xHCI port 0 into host mode.\n"); |
| 791 | res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); |
| 792 | cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); |
| 793 | cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); |
| 794 | reg = read32(cfg0); |
John Zhao | db2f91b | 2018-08-21 15:02:54 -0700 | [diff] [blame] | 795 | if (!(reg & SW_IDPIN_EN_MASK)) |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 796 | return; |
| 797 | |
| 798 | reg &= ~(SW_IDPIN_MASK | SW_VBUS_VALID_MASK); |
| 799 | write32(cfg0, reg); |
| 800 | |
| 801 | stopwatch_init_msecs_expire(&sw, 10); |
| 802 | /* Wait for the host mode status bit. */ |
| 803 | while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { |
| 804 | if (stopwatch_expired(&sw)) { |
| 805 | printk(BIOS_ERR, "Timed out waiting for host mode.\n"); |
| 806 | return; |
| 807 | } |
| 808 | } |
| 809 | |
Rob Barnes | d522f38 | 2022-09-12 06:31:47 -0600 | [diff] [blame] | 810 | printk(BIOS_INFO, "xHCI port 0 host switch over took %lld ms\n", |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 811 | stopwatch_duration_msecs(&sw)); |
| 812 | } |
| 813 | |
| 814 | static int check_xdci_enable(void) |
| 815 | { |
Werner Zeh | 69dcc1e | 2021-10-21 15:54:23 +0200 | [diff] [blame] | 816 | return is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_XDCI)); |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 817 | } |
| 818 | |
Marx Wang | abc17d1 | 2020-04-07 16:58:38 +0800 | [diff] [blame] | 819 | static void disable_xhci_lfps_pm(void) |
| 820 | { |
| 821 | struct soc_intel_apollolake_config *cfg; |
| 822 | |
| 823 | cfg = config_of_soc(); |
| 824 | |
| 825 | if (cfg->disable_xhci_lfps_pm) { |
| 826 | void *addr; |
| 827 | const struct resource *res; |
| 828 | uint32_t reg; |
| 829 | struct device *xhci_dev = PCH_DEV_XHCI; |
| 830 | |
| 831 | res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); |
| 832 | addr = (void *)(uintptr_t)(res->base + CFG_XHCPMCTRL); |
| 833 | reg = read32(addr); |
| 834 | printk(BIOS_DEBUG, "XHCI PM: control reg=0x%x.\n", reg); |
| 835 | if (reg) { |
| 836 | reg &= LFPS_PM_DISABLE_MASK; |
| 837 | write32(addr, reg); |
| 838 | printk(BIOS_INFO, "XHCI PM: Disable xHCI LFPS as configured in devicetree.\n"); |
| 839 | } |
| 840 | } |
| 841 | } |
| 842 | |
Lee Leahy | 806fa24 | 2016-08-01 13:55:02 -0700 | [diff] [blame] | 843 | void platform_fsp_notify_status(enum fsp_notify_phase phase) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 844 | { |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 845 | if (phase == END_OF_FIRMWARE) { |
Furquan Shaikh | d2c2f83 | 2018-11-07 10:24:31 -0800 | [diff] [blame] | 846 | |
| 847 | /* |
| 848 | * Before hiding P2SB device and dropping privilege level, |
| 849 | * dump CSE status and disable HECI1 interface. |
| 850 | */ |
| 851 | heci_cse_lockdown(); |
| 852 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 853 | /* Hide the P2SB device to align with previous behavior. */ |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 854 | p2sb_hide(); |
Furquan Shaikh | d2c2f83 | 2018-11-07 10:24:31 -0800 | [diff] [blame] | 855 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 856 | /* |
| 857 | * As per guidelines BIOS is recommended to drop CPU privilege |
| 858 | * level to IA_UNTRUSTED. After that certain device registers |
| 859 | * and MSRs become inaccessible supposedly increasing system |
| 860 | * security. |
| 861 | */ |
| 862 | drop_privilege_all(); |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 863 | |
| 864 | /* |
| 865 | * When USB OTG is set, GLK FSP enables xHCI SW ID pin and |
| 866 | * configures USB-C as device mode. Force USB-C into host mode. |
| 867 | */ |
| 868 | if (check_xdci_enable()) |
| 869 | configure_xhci_host_mode_port0(); |
John Zhao | 57aa8b6 | 2019-01-14 09:15:50 -0800 | [diff] [blame] | 870 | |
| 871 | /* |
| 872 | * Override GLK xhci clock gating register(XHCLKGTEN) to |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 873 | * mitigate USB device suspend and resume failure. |
John Zhao | 57aa8b6 | 2019-01-14 09:15:50 -0800 | [diff] [blame] | 874 | */ |
Angel Pons | b36100f | 2020-09-07 13:18:10 +0200 | [diff] [blame] | 875 | if (CONFIG(SOC_INTEL_GEMINILAKE)) { |
John Zhao | 57aa8b6 | 2019-01-14 09:15:50 -0800 | [diff] [blame] | 876 | uint32_t *cfg; |
| 877 | const struct resource *res; |
| 878 | uint32_t reg; |
| 879 | struct device *xhci_dev = PCH_DEV_XHCI; |
| 880 | |
| 881 | res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); |
| 882 | cfg = (void *)(uintptr_t)(res->base + CFG_XHCLKGTEN); |
| 883 | reg = SRAMPGTEN | SSLSE | USB2PLLSE | IOSFSTCGE | |
| 884 | HSTCGE | HSUXDMIPLLSE | SSTCGE | XHCFTCLKSE | |
| 885 | XHCBBTCGIPISO | XHCUSB2PLLSDLE | SSPLLSUE | |
| 886 | XHCBLCGE | HSLTCGE | SSLTCGE | IOSFBTCGE | |
| 887 | IOSFGBLCGE; |
| 888 | write32(cfg, reg); |
| 889 | } |
Marx Wang | abc17d1 | 2020-04-07 16:58:38 +0800 | [diff] [blame] | 890 | |
| 891 | /* Disable XHCI LFPS power management if the option in dev tree is set. */ |
| 892 | disable_xhci_lfps_pm(); |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 893 | } |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 894 | } |
| 895 | |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 896 | /* |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 897 | * spi_flash init() needs to run unconditionally on every boot (including |
| 898 | * resume) to allow write protect to be disabled for eventlog and nvram |
| 899 | * updates. This needs to be done as early as possible in ramstage. Thus, add a |
| 900 | * callback for entry into BS_PRE_DEVICE. |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 901 | */ |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 902 | static void spi_flash_init_cb(void *unused) |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 903 | { |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 904 | fast_spi_init(); |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 905 | } |
| 906 | |
Felix Singer | e59ae10 | 2019-05-02 13:57:57 +0200 | [diff] [blame] | 907 | __weak |
| 908 | void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) |
| 909 | { |
| 910 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 911 | } |
| 912 | |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 913 | /* Handle FSP logo params */ |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 914 | void soc_load_logo(FSPS_UPD *supd) |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 915 | { |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 916 | bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 917 | } |
| 918 | |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 919 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); |