Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 20 | #include <bootstate.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 21 | #include <cbmem.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <cpu/cpu.h> |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame^] | 24 | #include <cpu/x86/mp.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <fsp/api.h> |
| 28 | #include <fsp/util.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 29 | #include <romstage_handoff.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 30 | #include <soc/iomap.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 31 | #include <soc/cpu.h> |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 32 | #include <soc/flash_ctrlr.h> |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 33 | #include <soc/intel/common/vbt.h> |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 34 | #include <soc/itss.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 35 | #include <soc/nvs.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 36 | #include <soc/pci_devs.h> |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 37 | #include <spi-generic.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 38 | #include <soc/pm.h> |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 39 | #include <soc/p2sb.h> |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 40 | #include <soc/northbridge.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 41 | |
| 42 | #include "chip.h" |
| 43 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 44 | static void *vbt; |
| 45 | static struct region_device vbt_rdev; |
| 46 | |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 47 | static const char *soc_acpi_name(struct device *dev) |
| 48 | { |
| 49 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 50 | return "PCI0"; |
| 51 | |
| 52 | if (dev->path.type != DEVICE_PATH_PCI) |
| 53 | return NULL; |
| 54 | |
| 55 | switch (dev->path.pci.devfn) { |
| 56 | /* DSDT: acpi/northbridge.asl */ |
| 57 | case NB_DEVFN: |
| 58 | return "MCHC"; |
| 59 | /* DSDT: acpi/lpc.asl */ |
| 60 | case LPC_DEVFN: |
| 61 | return "LPCB"; |
| 62 | /* DSDT: acpi/xhci.asl */ |
| 63 | case XHCI_DEVFN: |
| 64 | return "XHCI"; |
| 65 | /* DSDT: acpi/pch_hda.asl */ |
| 66 | case HDA_DEVFN: |
| 67 | return "HDAS"; |
| 68 | /* DSDT: acpi/lpss.asl */ |
| 69 | case LPSS_DEVFN_UART0: |
| 70 | return "URT1"; |
| 71 | case LPSS_DEVFN_UART1: |
| 72 | return "URT2"; |
| 73 | case LPSS_DEVFN_UART2: |
| 74 | return "URT3"; |
| 75 | case LPSS_DEVFN_UART3: |
| 76 | return "URT4"; |
| 77 | case LPSS_DEVFN_SPI0: |
| 78 | return "SPI1"; |
| 79 | case LPSS_DEVFN_SPI1: |
| 80 | return "SPI2"; |
| 81 | case LPSS_DEVFN_SPI2: |
| 82 | return "SPI3"; |
| 83 | case LPSS_DEVFN_PWM: |
| 84 | return "PWM"; |
| 85 | case LPSS_DEVFN_I2C0: |
| 86 | return "I2C0"; |
| 87 | case LPSS_DEVFN_I2C1: |
| 88 | return "I2C1"; |
| 89 | case LPSS_DEVFN_I2C2: |
| 90 | return "I2C2"; |
| 91 | case LPSS_DEVFN_I2C3: |
| 92 | return "I2C3"; |
| 93 | case LPSS_DEVFN_I2C4: |
| 94 | return "I2C4"; |
| 95 | case LPSS_DEVFN_I2C5: |
| 96 | return "I2C5"; |
| 97 | case LPSS_DEVFN_I2C6: |
| 98 | return "I2C6"; |
| 99 | case LPSS_DEVFN_I2C7: |
| 100 | return "I2C7"; |
| 101 | /* Storage */ |
| 102 | case SDCARD_DEVFN: |
| 103 | return "SDCD"; |
| 104 | case EMMC_DEVFN: |
| 105 | return "EMMC"; |
| 106 | case SDIO_DEVFN: |
| 107 | return "SDIO"; |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 108 | /* PCIe */ |
| 109 | case PCIEB0_DEVFN: |
| 110 | return "RP01"; |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | return NULL; |
| 114 | } |
| 115 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 116 | static void pci_domain_set_resources(device_t dev) |
| 117 | { |
| 118 | assign_resources(dev->link_list); |
| 119 | } |
| 120 | |
| 121 | static struct device_operations pci_domain_ops = { |
| 122 | .read_resources = pci_domain_read_resources, |
| 123 | .set_resources = pci_domain_set_resources, |
| 124 | .enable_resources = NULL, |
| 125 | .init = NULL, |
| 126 | .scan_bus = pci_domain_scan_bus, |
| 127 | .ops_pci_bus = pci_bus_default_ops, |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 128 | .acpi_name = &soc_acpi_name, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 129 | }; |
| 130 | |
| 131 | static struct device_operations cpu_bus_ops = { |
| 132 | .read_resources = DEVICE_NOOP, |
| 133 | .set_resources = DEVICE_NOOP, |
| 134 | .enable_resources = DEVICE_NOOP, |
| 135 | .init = apollolake_init_cpus, |
| 136 | .scan_bus = NULL, |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 137 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | static void enable_dev(device_t dev) |
| 141 | { |
| 142 | /* Set the operations if it is a special bus type */ |
| 143 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 144 | dev->ops = &pci_domain_ops; |
| 145 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 146 | dev->ops = &cpu_bus_ops; |
| 147 | } |
| 148 | } |
| 149 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 150 | /* |
| 151 | * If the PCIe root port at function 0 is disabled, |
| 152 | * the PCIe root ports might be coalesced after FSP silicon init. |
| 153 | * The below function will swap the devfn of the first enabled device |
| 154 | * in devicetree and function 0 resides a pci device |
| 155 | * so that it won't confuse coreboot. |
| 156 | */ |
| 157 | static void pcie_update_device_tree(unsigned int devfn0, int num_funcs) |
| 158 | { |
| 159 | device_t func0; |
| 160 | unsigned int devfn; |
| 161 | int i; |
| 162 | unsigned int inc = PCI_DEVFN(0, 1); |
| 163 | |
| 164 | func0 = dev_find_slot(0, devfn0); |
| 165 | if (func0 == NULL) |
| 166 | return; |
| 167 | |
| 168 | /* No more functions if function 0 is disabled. */ |
| 169 | if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) |
| 170 | return; |
| 171 | |
| 172 | devfn = devfn0 + inc; |
| 173 | |
| 174 | /* |
| 175 | * Increase funtion by 1. |
| 176 | * Then find first enabled device to replace func0 |
| 177 | * as that port was move to func0. |
| 178 | */ |
| 179 | for (i = 1; i < num_funcs; i++, devfn += inc) { |
| 180 | device_t dev = dev_find_slot(0, devfn); |
| 181 | if (dev == NULL) |
| 182 | continue; |
| 183 | |
| 184 | if (!dev->enabled) |
| 185 | continue; |
| 186 | /* Found the first enabled device in given dev number */ |
| 187 | func0->path.pci.devfn = dev->path.pci.devfn; |
| 188 | dev->path.pci.devfn = devfn0; |
| 189 | break; |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | static void pcie_override_devicetree_after_silicon_init(void) |
| 194 | { |
| 195 | pcie_update_device_tree(PCIEA0_DEVFN, 4); |
| 196 | pcie_update_device_tree(PCIEB0_DEVFN, 2); |
| 197 | } |
| 198 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 199 | /* Configure package power limits */ |
| 200 | static void set_power_limits(void) |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 201 | { |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 202 | static struct soc_intel_apollolake_config *cfg; |
| 203 | struct device *dev = NB_DEV_ROOT; |
| 204 | msr_t rapl_msr_reg, limit; |
| 205 | uint32_t power_unit; |
| 206 | uint32_t tdp, min_power, max_power; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 207 | uint32_t pl2_val; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 208 | uint32_t *rapl_mmio_reg; |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 209 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 210 | if (!dev || !dev->chip_info) { |
| 211 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 212 | return; |
| 213 | } |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 214 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 215 | cfg = dev->chip_info; |
| 216 | |
| 217 | /* Get units */ |
| 218 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 219 | power_unit = 1 << (rapl_msr_reg.lo & 0xf); |
| 220 | |
| 221 | /* Get power defaults for this SKU */ |
| 222 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); |
| 223 | tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 224 | pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 225 | min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; |
| 226 | max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
| 227 | |
| 228 | if (min_power > 0 && tdp < min_power) |
| 229 | tdp = min_power; |
| 230 | |
| 231 | if (max_power > 0 && tdp > max_power) |
| 232 | tdp = max_power; |
| 233 | |
| 234 | /* Set PL1 override value */ |
| 235 | tdp = (cfg->tdp_pl1_override_mw == 0) ? |
| 236 | tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 237 | /* Set PL2 override value */ |
| 238 | pl2_val = (cfg->tdp_pl2_override_mw == 0) ? |
| 239 | pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 240 | |
| 241 | /* Set long term power limit to TDP */ |
| 242 | limit.lo = tdp & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 243 | /* Set PL1 Pkg Power clamp bit */ |
| 244 | limit.lo |= PKG_POWER_LIMIT_CLAMP; |
| 245 | |
| 246 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 247 | limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & |
| 248 | PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; |
| 249 | |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 250 | /* Set short term power limit PL2 */ |
| 251 | limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; |
| 252 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 253 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 254 | /* Program package power limits in RAPL MSR */ |
| 255 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 256 | printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, |
| 257 | 100 * (tdp % power_unit) / power_unit); |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 258 | printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, |
| 259 | 100 * (pl2_val % power_unit) / power_unit); |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 260 | |
| 261 | /* Get the MMIO address */ |
| 262 | rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 263 | |
| 264 | /* Setting RAPL MMIO register for Power limits. |
| 265 | * RAPL driver is using MSR instead of MMIO. |
| 266 | * So, disabled LIMIT_EN bit for MMIO. */ |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 267 | write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 268 | write32(rapl_mmio_reg + 1, limit.hi & ~(PKG_POWER_LIMIT_EN)); |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 269 | } |
| 270 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 271 | static void soc_init(void *data) |
| 272 | { |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 273 | struct global_nvs_t *gnvs; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 274 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 275 | /* Save VBT info and mapping */ |
Abhay Kumar | ec2947f | 2016-07-14 18:43:54 -0700 | [diff] [blame] | 276 | vbt = vbt_get(&vbt_rdev); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 277 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 278 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 279 | * default policy that doesn't honor boards' requirements. */ |
| 280 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 281 | |
Aaron Durbin | 6c191d8 | 2016-11-29 21:22:42 -0600 | [diff] [blame] | 282 | fsp_silicon_init(romstage_handoff_is_resume()); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 283 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 284 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 285 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 286 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 287 | /* override 'enabled' setting in device tree if needed */ |
| 288 | pcie_override_devicetree_after_silicon_init(); |
| 289 | |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 290 | /* |
| 291 | * Keep the P2SB device visible so it and the other devices are |
| 292 | * visible in coreboot for driver support and PCI resource allocation. |
| 293 | * There is a UPD setting for this, but it's more consistent to use |
| 294 | * hide and unhide symmetrically. |
| 295 | */ |
| 296 | p2sb_unhide(); |
| 297 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 298 | /* Allocate ACPI NVS in CBMEM */ |
| 299 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 300 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 301 | /* Set RAPL MSR for Package power limits*/ |
| 302 | set_power_limits(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 303 | } |
| 304 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 305 | static void soc_final(void *data) |
| 306 | { |
| 307 | if (vbt) |
| 308 | rdev_munmap(&vbt_rdev, vbt); |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 309 | |
| 310 | /* Disable global reset, just in case */ |
| 311 | global_reset_enable(0); |
| 312 | /* Make sure payload/OS can't trigger global reset */ |
| 313 | global_reset_lock(); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 314 | } |
| 315 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 316 | static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) { |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 317 | |
| 318 | switch (dev->path.pci.devfn) { |
| 319 | case ISH_DEVFN: |
| 320 | silconfig->IshEnable = 0; |
| 321 | break; |
| 322 | case SATA_DEVFN: |
| 323 | silconfig->EnableSata = 0; |
| 324 | break; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 325 | case PCIEB0_DEVFN: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 326 | silconfig->PcieRootPortEn[0] = 0; |
| 327 | silconfig->PcieRpHotPlug[0] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 328 | break; |
| 329 | case PCIEB1_DEVFN: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 330 | silconfig->PcieRootPortEn[1] = 0; |
| 331 | silconfig->PcieRpHotPlug[1] = 0; |
| 332 | break; |
| 333 | case PCIEA0_DEVFN: |
| 334 | silconfig->PcieRootPortEn[2] = 0; |
| 335 | silconfig->PcieRpHotPlug[2] = 0; |
| 336 | break; |
| 337 | case PCIEA1_DEVFN: |
| 338 | silconfig->PcieRootPortEn[3] = 0; |
| 339 | silconfig->PcieRpHotPlug[3] = 0; |
| 340 | break; |
| 341 | case PCIEA2_DEVFN: |
| 342 | silconfig->PcieRootPortEn[4] = 0; |
| 343 | silconfig->PcieRpHotPlug[4] = 0; |
| 344 | break; |
| 345 | case PCIEA3_DEVFN: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 346 | silconfig->PcieRootPortEn[5] = 0; |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 347 | silconfig->PcieRpHotPlug[5] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 348 | break; |
| 349 | case XHCI_DEVFN: |
| 350 | silconfig->Usb30Mode = 0; |
| 351 | break; |
| 352 | case XDCI_DEVFN: |
| 353 | silconfig->UsbOtg = 0; |
| 354 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 355 | case LPSS_DEVFN_I2C0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 356 | silconfig->I2c0Enable = 0; |
| 357 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 358 | case LPSS_DEVFN_I2C1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 359 | silconfig->I2c1Enable = 0; |
| 360 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 361 | case LPSS_DEVFN_I2C2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 362 | silconfig->I2c2Enable = 0; |
| 363 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 364 | case LPSS_DEVFN_I2C3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 365 | silconfig->I2c3Enable = 0; |
| 366 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 367 | case LPSS_DEVFN_I2C4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 368 | silconfig->I2c4Enable = 0; |
| 369 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 370 | case LPSS_DEVFN_I2C5: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 371 | silconfig->I2c5Enable = 0; |
| 372 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 373 | case LPSS_DEVFN_I2C6: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 374 | silconfig->I2c6Enable = 0; |
| 375 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 376 | case LPSS_DEVFN_I2C7: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 377 | silconfig->I2c7Enable = 0; |
| 378 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 379 | case LPSS_DEVFN_UART0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 380 | silconfig->Hsuart0Enable = 0; |
| 381 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 382 | case LPSS_DEVFN_UART1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 383 | silconfig->Hsuart1Enable = 0; |
| 384 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 385 | case LPSS_DEVFN_UART2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 386 | silconfig->Hsuart2Enable = 0; |
| 387 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 388 | case LPSS_DEVFN_UART3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 389 | silconfig->Hsuart3Enable = 0; |
| 390 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 391 | case LPSS_DEVFN_SPI0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 392 | silconfig->Spi0Enable = 0; |
| 393 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 394 | case LPSS_DEVFN_SPI1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 395 | silconfig->Spi1Enable = 0; |
| 396 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 397 | case LPSS_DEVFN_SPI2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 398 | silconfig->Spi2Enable = 0; |
| 399 | break; |
| 400 | case SDCARD_DEVFN: |
| 401 | silconfig->SdcardEnabled = 0; |
| 402 | break; |
| 403 | case EMMC_DEVFN: |
| 404 | silconfig->eMMCEnabled = 0; |
| 405 | break; |
| 406 | case SDIO_DEVFN: |
| 407 | silconfig->SdioEnabled = 0; |
| 408 | break; |
| 409 | case SMBUS_DEVFN: |
| 410 | silconfig->SmbusEnable = 0; |
| 411 | break; |
| 412 | default: |
| 413 | printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", |
| 414 | PCI_SLOT(dev->path.pci.devfn), |
| 415 | PCI_FUNC(dev->path.pci.devfn)); |
| 416 | break; |
| 417 | } |
| 418 | } |
| 419 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 420 | static void parse_devicetree(FSP_S_CONFIG *silconfig) |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 421 | { |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 422 | struct device *dev = NB_DEV_ROOT; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 423 | |
| 424 | if (!dev) { |
| 425 | printk(BIOS_ERR, "Could not find root device\n"); |
| 426 | return; |
| 427 | } |
| 428 | /* Only disable bus 0 devices. */ |
| 429 | for (dev = dev->bus->children; dev; dev = dev->sibling) { |
| 430 | if (!dev->enabled) |
| 431 | disable_dev(dev, silconfig); |
| 432 | } |
| 433 | } |
| 434 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 435 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 436 | { |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 437 | FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 438 | static struct soc_intel_apollolake_config *cfg; |
| 439 | |
| 440 | /* Load VBT before devicetree-specific config. */ |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 441 | silconfig->GraphicsConfigPtr = (uintptr_t)vbt; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 442 | |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 443 | struct device *dev = NB_DEV_ROOT; |
| 444 | |
Patrick Georgi | 831d65d | 2016-04-14 11:53:48 +0200 | [diff] [blame] | 445 | if (!dev || !dev->chip_info) { |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 446 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 447 | return; |
| 448 | } |
| 449 | |
| 450 | cfg = dev->chip_info; |
| 451 | |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 452 | /* Parse device tree and disable unused device*/ |
| 453 | parse_devicetree(silconfig); |
| 454 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 455 | silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; |
| 456 | silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; |
| 457 | silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; |
| 458 | silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; |
| 459 | silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; |
| 460 | silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 461 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 462 | if (cfg->emmc_tx_cmd_cntl != 0) |
| 463 | silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; |
| 464 | if (cfg->emmc_tx_data_cntl1 != 0) |
| 465 | silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; |
| 466 | if (cfg->emmc_tx_data_cntl2 != 0) |
| 467 | silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2; |
| 468 | if (cfg->emmc_rx_cmd_data_cntl1 != 0) |
| 469 | silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1; |
| 470 | if (cfg->emmc_rx_strobe_cntl != 0) |
| 471 | silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; |
| 472 | if (cfg->emmc_rx_cmd_data_cntl2 != 0) |
| 473 | silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; |
| 474 | |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 475 | silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; |
| 476 | |
Bora Guvendik | 60cc75d | 2016-07-25 14:44:51 -0700 | [diff] [blame] | 477 | /* Disable monitor mwait since it is broken due to a hardware bug without a fix */ |
| 478 | silconfig->MonitorMwaitEnable = 0; |
| 479 | |
Venkateswarlu Vinjamuri | 1a5e32c | 2016-10-31 17:15:30 -0700 | [diff] [blame] | 480 | silconfig->SkipMpInit = 1; |
| 481 | |
Furquan Shaikh | cad9b63 | 2016-06-20 16:08:42 -0700 | [diff] [blame] | 482 | /* Disable setting of EISS bit in FSP. */ |
| 483 | silconfig->SpiEiss = 0; |
Ravi Sarawadi | 3a21d0f | 2016-08-10 11:33:56 -0700 | [diff] [blame] | 484 | |
| 485 | /* Disable FSP from locking access to the RTC NVRAM */ |
| 486 | silconfig->RtcLock = 0; |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 487 | |
| 488 | /* Enable Audio clk gate and power gate */ |
| 489 | silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; |
| 490 | silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; |
| 491 | /* Bios config lockdown Audio clk and power gate */ |
| 492 | silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; |
| 493 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 494 | } |
| 495 | |
| 496 | struct chip_operations soc_intel_apollolake_ops = { |
| 497 | CHIP_NAME("Intel Apollolake SOC") |
| 498 | .enable_dev = &enable_dev, |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 499 | .init = &soc_init, |
| 500 | .final = &soc_final |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 501 | }; |
| 502 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame^] | 503 | static void drop_privilege_all(void) |
| 504 | { |
| 505 | /* Drop privilege level on all the CPUs */ |
| 506 | if (mp_run_on_all_cpus(&enable_untrusted_mode, 1000) < 0) |
| 507 | printk(BIOS_ERR, "failed to enable untrusted mode\n"); |
| 508 | } |
| 509 | |
Lee Leahy | 806fa24 | 2016-08-01 13:55:02 -0700 | [diff] [blame] | 510 | void platform_fsp_notify_status(enum fsp_notify_phase phase) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 511 | { |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame^] | 512 | if (phase == END_OF_FIRMWARE) { |
| 513 | /* Hide the P2SB device to align with previous behavior. */ |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 514 | p2sb_hide(); |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame^] | 515 | /* |
| 516 | * As per guidelines BIOS is recommended to drop CPU privilege |
| 517 | * level to IA_UNTRUSTED. After that certain device registers |
| 518 | * and MSRs become inaccessible supposedly increasing system |
| 519 | * security. |
| 520 | */ |
| 521 | drop_privilege_all(); |
| 522 | } |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 523 | } |
| 524 | |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 525 | /* |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 526 | * spi_flash init() needs to run unconditionally on every boot (including |
| 527 | * resume) to allow write protect to be disabled for eventlog and nvram |
| 528 | * updates. This needs to be done as early as possible in ramstage. Thus, add a |
| 529 | * callback for entry into BS_PRE_DEVICE. |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 530 | */ |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 531 | static void spi_flash_init_cb(void *unused) |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 532 | { |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 533 | spi_flash_init(); |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 534 | } |
| 535 | |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 536 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); |