soc/intel/apollolake: Bypass FSP's CpuMemorytest, PCIe pwr seq & SPI Init
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table
entry for this range which caused a page fault. Since this test
is anyway not exhaustive, we will skip the memory test in FSP.
There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.
FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence
skipping SPI clock programming in FSP.
BUG=b:78599939, b:78599576, b:76058338
TEST=Build coreboot for Octopus board.
Signed-off-by: Srinidhi N Kaushik <email@example.com>
Reviewed-by: Aaron Durbin <firstname.lastname@example.org>
Reviewed-by: Furquan Shaikh <email@example.com>
Tested-by: build bot (Jenkins) <firstname.lastname@example.org>
2 files changed