Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 20 | #include <bootstate.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 21 | #include <cbmem.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <cpu/cpu.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <fsp/api.h> |
| 27 | #include <fsp/util.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 28 | #include <soc/iomap.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 29 | #include <soc/cpu.h> |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 30 | #include <soc/intel/common/vbt.h> |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 31 | #include <soc/itss.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 32 | #include <soc/nvs.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 34 | #include <spi-generic.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 35 | #include <soc/pm.h> |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 36 | #include <soc/p2sb.h> |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 37 | #include <soc/northbridge.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 38 | |
| 39 | #include "chip.h" |
| 40 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 41 | static void *vbt; |
| 42 | static struct region_device vbt_rdev; |
| 43 | |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 44 | static const char *soc_acpi_name(struct device *dev) |
| 45 | { |
| 46 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 47 | return "PCI0"; |
| 48 | |
| 49 | if (dev->path.type != DEVICE_PATH_PCI) |
| 50 | return NULL; |
| 51 | |
| 52 | switch (dev->path.pci.devfn) { |
| 53 | /* DSDT: acpi/northbridge.asl */ |
| 54 | case NB_DEVFN: |
| 55 | return "MCHC"; |
| 56 | /* DSDT: acpi/lpc.asl */ |
| 57 | case LPC_DEVFN: |
| 58 | return "LPCB"; |
| 59 | /* DSDT: acpi/xhci.asl */ |
| 60 | case XHCI_DEVFN: |
| 61 | return "XHCI"; |
| 62 | /* DSDT: acpi/pch_hda.asl */ |
| 63 | case HDA_DEVFN: |
| 64 | return "HDAS"; |
| 65 | /* DSDT: acpi/lpss.asl */ |
| 66 | case LPSS_DEVFN_UART0: |
| 67 | return "URT1"; |
| 68 | case LPSS_DEVFN_UART1: |
| 69 | return "URT2"; |
| 70 | case LPSS_DEVFN_UART2: |
| 71 | return "URT3"; |
| 72 | case LPSS_DEVFN_UART3: |
| 73 | return "URT4"; |
| 74 | case LPSS_DEVFN_SPI0: |
| 75 | return "SPI1"; |
| 76 | case LPSS_DEVFN_SPI1: |
| 77 | return "SPI2"; |
| 78 | case LPSS_DEVFN_SPI2: |
| 79 | return "SPI3"; |
| 80 | case LPSS_DEVFN_PWM: |
| 81 | return "PWM"; |
| 82 | case LPSS_DEVFN_I2C0: |
| 83 | return "I2C0"; |
| 84 | case LPSS_DEVFN_I2C1: |
| 85 | return "I2C1"; |
| 86 | case LPSS_DEVFN_I2C2: |
| 87 | return "I2C2"; |
| 88 | case LPSS_DEVFN_I2C3: |
| 89 | return "I2C3"; |
| 90 | case LPSS_DEVFN_I2C4: |
| 91 | return "I2C4"; |
| 92 | case LPSS_DEVFN_I2C5: |
| 93 | return "I2C5"; |
| 94 | case LPSS_DEVFN_I2C6: |
| 95 | return "I2C6"; |
| 96 | case LPSS_DEVFN_I2C7: |
| 97 | return "I2C7"; |
| 98 | /* Storage */ |
| 99 | case SDCARD_DEVFN: |
| 100 | return "SDCD"; |
| 101 | case EMMC_DEVFN: |
| 102 | return "EMMC"; |
| 103 | case SDIO_DEVFN: |
| 104 | return "SDIO"; |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 105 | /* PCIe */ |
| 106 | case PCIEB0_DEVFN: |
| 107 | return "RP01"; |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | return NULL; |
| 111 | } |
| 112 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 113 | static void pci_domain_set_resources(device_t dev) |
| 114 | { |
| 115 | assign_resources(dev->link_list); |
| 116 | } |
| 117 | |
| 118 | static struct device_operations pci_domain_ops = { |
| 119 | .read_resources = pci_domain_read_resources, |
| 120 | .set_resources = pci_domain_set_resources, |
| 121 | .enable_resources = NULL, |
| 122 | .init = NULL, |
| 123 | .scan_bus = pci_domain_scan_bus, |
| 124 | .ops_pci_bus = pci_bus_default_ops, |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 125 | .acpi_name = &soc_acpi_name, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | static struct device_operations cpu_bus_ops = { |
| 129 | .read_resources = DEVICE_NOOP, |
| 130 | .set_resources = DEVICE_NOOP, |
| 131 | .enable_resources = DEVICE_NOOP, |
| 132 | .init = apollolake_init_cpus, |
| 133 | .scan_bus = NULL, |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 134 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 135 | }; |
| 136 | |
| 137 | static void enable_dev(device_t dev) |
| 138 | { |
| 139 | /* Set the operations if it is a special bus type */ |
| 140 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 141 | dev->ops = &pci_domain_ops; |
| 142 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 143 | dev->ops = &cpu_bus_ops; |
| 144 | } |
| 145 | } |
| 146 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 147 | /* |
| 148 | * If the PCIe root port at function 0 is disabled, |
| 149 | * the PCIe root ports might be coalesced after FSP silicon init. |
| 150 | * The below function will swap the devfn of the first enabled device |
| 151 | * in devicetree and function 0 resides a pci device |
| 152 | * so that it won't confuse coreboot. |
| 153 | */ |
| 154 | static void pcie_update_device_tree(unsigned int devfn0, int num_funcs) |
| 155 | { |
| 156 | device_t func0; |
| 157 | unsigned int devfn; |
| 158 | int i; |
| 159 | unsigned int inc = PCI_DEVFN(0, 1); |
| 160 | |
| 161 | func0 = dev_find_slot(0, devfn0); |
| 162 | if (func0 == NULL) |
| 163 | return; |
| 164 | |
| 165 | /* No more functions if function 0 is disabled. */ |
| 166 | if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) |
| 167 | return; |
| 168 | |
| 169 | devfn = devfn0 + inc; |
| 170 | |
| 171 | /* |
| 172 | * Increase funtion by 1. |
| 173 | * Then find first enabled device to replace func0 |
| 174 | * as that port was move to func0. |
| 175 | */ |
| 176 | for (i = 1; i < num_funcs; i++, devfn += inc) { |
| 177 | device_t dev = dev_find_slot(0, devfn); |
| 178 | if (dev == NULL) |
| 179 | continue; |
| 180 | |
| 181 | if (!dev->enabled) |
| 182 | continue; |
| 183 | /* Found the first enabled device in given dev number */ |
| 184 | func0->path.pci.devfn = dev->path.pci.devfn; |
| 185 | dev->path.pci.devfn = devfn0; |
| 186 | break; |
| 187 | } |
| 188 | } |
| 189 | |
| 190 | static void pcie_override_devicetree_after_silicon_init(void) |
| 191 | { |
| 192 | pcie_update_device_tree(PCIEA0_DEVFN, 4); |
| 193 | pcie_update_device_tree(PCIEB0_DEVFN, 2); |
| 194 | } |
| 195 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 196 | /* Configure package power limits */ |
| 197 | static void set_power_limits(void) |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 198 | { |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 199 | static struct soc_intel_apollolake_config *cfg; |
| 200 | struct device *dev = NB_DEV_ROOT; |
| 201 | msr_t rapl_msr_reg, limit; |
| 202 | uint32_t power_unit; |
| 203 | uint32_t tdp, min_power, max_power; |
| 204 | uint32_t *rapl_mmio_reg; |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 205 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 206 | if (!dev || !dev->chip_info) { |
| 207 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 208 | return; |
| 209 | } |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 210 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 211 | cfg = dev->chip_info; |
| 212 | |
| 213 | /* Get units */ |
| 214 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 215 | power_unit = 1 << (rapl_msr_reg.lo & 0xf); |
| 216 | |
| 217 | /* Get power defaults for this SKU */ |
| 218 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); |
| 219 | tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; |
| 220 | min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; |
| 221 | max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
| 222 | |
| 223 | if (min_power > 0 && tdp < min_power) |
| 224 | tdp = min_power; |
| 225 | |
| 226 | if (max_power > 0 && tdp > max_power) |
| 227 | tdp = max_power; |
| 228 | |
| 229 | /* Set PL1 override value */ |
| 230 | tdp = (cfg->tdp_pl1_override_mw == 0) ? |
| 231 | tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000; |
| 232 | |
| 233 | /* Set long term power limit to TDP */ |
| 234 | limit.lo = tdp & PKG_POWER_LIMIT_MASK; |
| 235 | /* PL2 is invalid for small core */ |
| 236 | limit.hi = 0x0; |
| 237 | |
| 238 | /* Set PL1 Pkg Power clamp bit */ |
| 239 | limit.lo |= PKG_POWER_LIMIT_CLAMP; |
| 240 | |
| 241 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 242 | limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & |
| 243 | PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; |
| 244 | |
| 245 | /* Program package power limits in RAPL MSR */ |
| 246 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 247 | printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, |
| 248 | 100 * (tdp % power_unit) / power_unit); |
| 249 | |
| 250 | /* Get the MMIO address */ |
| 251 | rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); |
| 252 | /* |
| 253 | * Disable RAPL MMIO PL1 Power limits because RAPL uses MSR value. |
| 254 | * PL2 (limit.hi) is invalid for small cores |
| 255 | */ |
| 256 | write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 257 | } |
| 258 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 259 | static void soc_init(void *data) |
| 260 | { |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 261 | struct global_nvs_t *gnvs; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 262 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 263 | /* Save VBT info and mapping */ |
Abhay Kumar | ec2947f | 2016-07-14 18:43:54 -0700 | [diff] [blame] | 264 | vbt = vbt_get(&vbt_rdev); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 265 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 266 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 267 | * default policy that doesn't honor boards' requirements. */ |
| 268 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 269 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 270 | fsp_silicon_init(); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 271 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 272 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 273 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 274 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 275 | /* override 'enabled' setting in device tree if needed */ |
| 276 | pcie_override_devicetree_after_silicon_init(); |
| 277 | |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 278 | /* |
| 279 | * Keep the P2SB device visible so it and the other devices are |
| 280 | * visible in coreboot for driver support and PCI resource allocation. |
| 281 | * There is a UPD setting for this, but it's more consistent to use |
| 282 | * hide and unhide symmetrically. |
| 283 | */ |
| 284 | p2sb_unhide(); |
| 285 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 286 | /* Allocate ACPI NVS in CBMEM */ |
| 287 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 288 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 289 | /* Set RAPL MSR for Package power limits*/ |
| 290 | set_power_limits(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 291 | } |
| 292 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 293 | static void soc_final(void *data) |
| 294 | { |
| 295 | if (vbt) |
| 296 | rdev_munmap(&vbt_rdev, vbt); |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 297 | |
| 298 | /* Disable global reset, just in case */ |
| 299 | global_reset_enable(0); |
| 300 | /* Make sure payload/OS can't trigger global reset */ |
| 301 | global_reset_lock(); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 302 | } |
| 303 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 304 | static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) { |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 305 | |
| 306 | switch (dev->path.pci.devfn) { |
| 307 | case ISH_DEVFN: |
| 308 | silconfig->IshEnable = 0; |
| 309 | break; |
| 310 | case SATA_DEVFN: |
| 311 | silconfig->EnableSata = 0; |
| 312 | break; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 313 | case PCIEB0_DEVFN: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 314 | silconfig->PcieRootPortEn[0] = 0; |
| 315 | silconfig->PcieRpHotPlug[0] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 316 | break; |
| 317 | case PCIEB1_DEVFN: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 318 | silconfig->PcieRootPortEn[1] = 0; |
| 319 | silconfig->PcieRpHotPlug[1] = 0; |
| 320 | break; |
| 321 | case PCIEA0_DEVFN: |
| 322 | silconfig->PcieRootPortEn[2] = 0; |
| 323 | silconfig->PcieRpHotPlug[2] = 0; |
| 324 | break; |
| 325 | case PCIEA1_DEVFN: |
| 326 | silconfig->PcieRootPortEn[3] = 0; |
| 327 | silconfig->PcieRpHotPlug[3] = 0; |
| 328 | break; |
| 329 | case PCIEA2_DEVFN: |
| 330 | silconfig->PcieRootPortEn[4] = 0; |
| 331 | silconfig->PcieRpHotPlug[4] = 0; |
| 332 | break; |
| 333 | case PCIEA3_DEVFN: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 334 | silconfig->PcieRootPortEn[5] = 0; |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 335 | silconfig->PcieRpHotPlug[5] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 336 | break; |
| 337 | case XHCI_DEVFN: |
| 338 | silconfig->Usb30Mode = 0; |
| 339 | break; |
| 340 | case XDCI_DEVFN: |
| 341 | silconfig->UsbOtg = 0; |
| 342 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 343 | case LPSS_DEVFN_I2C0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 344 | silconfig->I2c0Enable = 0; |
| 345 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 346 | case LPSS_DEVFN_I2C1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 347 | silconfig->I2c1Enable = 0; |
| 348 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 349 | case LPSS_DEVFN_I2C2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 350 | silconfig->I2c2Enable = 0; |
| 351 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 352 | case LPSS_DEVFN_I2C3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 353 | silconfig->I2c3Enable = 0; |
| 354 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 355 | case LPSS_DEVFN_I2C4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 356 | silconfig->I2c4Enable = 0; |
| 357 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 358 | case LPSS_DEVFN_I2C5: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 359 | silconfig->I2c5Enable = 0; |
| 360 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 361 | case LPSS_DEVFN_I2C6: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 362 | silconfig->I2c6Enable = 0; |
| 363 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 364 | case LPSS_DEVFN_I2C7: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 365 | silconfig->I2c7Enable = 0; |
| 366 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 367 | case LPSS_DEVFN_UART0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 368 | silconfig->Hsuart0Enable = 0; |
| 369 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 370 | case LPSS_DEVFN_UART1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 371 | silconfig->Hsuart1Enable = 0; |
| 372 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 373 | case LPSS_DEVFN_UART2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 374 | silconfig->Hsuart2Enable = 0; |
| 375 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 376 | case LPSS_DEVFN_UART3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 377 | silconfig->Hsuart3Enable = 0; |
| 378 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 379 | case LPSS_DEVFN_SPI0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 380 | silconfig->Spi0Enable = 0; |
| 381 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 382 | case LPSS_DEVFN_SPI1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 383 | silconfig->Spi1Enable = 0; |
| 384 | break; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 385 | case LPSS_DEVFN_SPI2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 386 | silconfig->Spi2Enable = 0; |
| 387 | break; |
| 388 | case SDCARD_DEVFN: |
| 389 | silconfig->SdcardEnabled = 0; |
| 390 | break; |
| 391 | case EMMC_DEVFN: |
| 392 | silconfig->eMMCEnabled = 0; |
| 393 | break; |
| 394 | case SDIO_DEVFN: |
| 395 | silconfig->SdioEnabled = 0; |
| 396 | break; |
| 397 | case SMBUS_DEVFN: |
| 398 | silconfig->SmbusEnable = 0; |
| 399 | break; |
| 400 | default: |
| 401 | printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", |
| 402 | PCI_SLOT(dev->path.pci.devfn), |
| 403 | PCI_FUNC(dev->path.pci.devfn)); |
| 404 | break; |
| 405 | } |
| 406 | } |
| 407 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 408 | static void parse_devicetree(FSP_S_CONFIG *silconfig) |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 409 | { |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 410 | struct device *dev = NB_DEV_ROOT; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 411 | |
| 412 | if (!dev) { |
| 413 | printk(BIOS_ERR, "Could not find root device\n"); |
| 414 | return; |
| 415 | } |
| 416 | /* Only disable bus 0 devices. */ |
| 417 | for (dev = dev->bus->children; dev; dev = dev->sibling) { |
| 418 | if (!dev->enabled) |
| 419 | disable_dev(dev, silconfig); |
| 420 | } |
| 421 | } |
| 422 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 423 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 424 | { |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 425 | FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 426 | static struct soc_intel_apollolake_config *cfg; |
| 427 | |
| 428 | /* Load VBT before devicetree-specific config. */ |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 429 | silconfig->GraphicsConfigPtr = (uintptr_t)vbt; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 430 | |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 431 | struct device *dev = NB_DEV_ROOT; |
| 432 | |
Patrick Georgi | 831d65d | 2016-04-14 11:53:48 +0200 | [diff] [blame] | 433 | if (!dev || !dev->chip_info) { |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 434 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 435 | return; |
| 436 | } |
| 437 | |
| 438 | cfg = dev->chip_info; |
| 439 | |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 440 | /* Parse device tree and disable unused device*/ |
| 441 | parse_devicetree(silconfig); |
| 442 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 443 | silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; |
| 444 | silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; |
| 445 | silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; |
| 446 | silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; |
| 447 | silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; |
| 448 | silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 449 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 450 | if (cfg->emmc_tx_cmd_cntl != 0) |
| 451 | silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; |
| 452 | if (cfg->emmc_tx_data_cntl1 != 0) |
| 453 | silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; |
| 454 | if (cfg->emmc_tx_data_cntl2 != 0) |
| 455 | silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2; |
| 456 | if (cfg->emmc_rx_cmd_data_cntl1 != 0) |
| 457 | silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1; |
| 458 | if (cfg->emmc_rx_strobe_cntl != 0) |
| 459 | silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; |
| 460 | if (cfg->emmc_rx_cmd_data_cntl2 != 0) |
| 461 | silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; |
| 462 | |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 463 | silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; |
| 464 | |
Bora Guvendik | 60cc75d | 2016-07-25 14:44:51 -0700 | [diff] [blame] | 465 | /* Disable monitor mwait since it is broken due to a hardware bug without a fix */ |
| 466 | silconfig->MonitorMwaitEnable = 0; |
| 467 | |
Venkateswarlu Vinjamuri | 1a5e32c | 2016-10-31 17:15:30 -0700 | [diff] [blame^] | 468 | silconfig->SkipMpInit = 1; |
| 469 | |
Furquan Shaikh | cad9b63 | 2016-06-20 16:08:42 -0700 | [diff] [blame] | 470 | /* Disable setting of EISS bit in FSP. */ |
| 471 | silconfig->SpiEiss = 0; |
Ravi Sarawadi | 3a21d0f | 2016-08-10 11:33:56 -0700 | [diff] [blame] | 472 | |
| 473 | /* Disable FSP from locking access to the RTC NVRAM */ |
| 474 | silconfig->RtcLock = 0; |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 475 | |
| 476 | /* Enable Audio clk gate and power gate */ |
| 477 | silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; |
| 478 | silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; |
| 479 | /* Bios config lockdown Audio clk and power gate */ |
| 480 | silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; |
| 481 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 482 | } |
| 483 | |
| 484 | struct chip_operations soc_intel_apollolake_ops = { |
| 485 | CHIP_NAME("Intel Apollolake SOC") |
| 486 | .enable_dev = &enable_dev, |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 487 | .init = &soc_init, |
| 488 | .final = &soc_final |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 489 | }; |
| 490 | |
Lee Leahy | 806fa24 | 2016-08-01 13:55:02 -0700 | [diff] [blame] | 491 | void platform_fsp_notify_status(enum fsp_notify_phase phase) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 492 | { |
Lee Leahy | 806fa24 | 2016-08-01 13:55:02 -0700 | [diff] [blame] | 493 | /* Hide the P2SB device to align with previous behavior. */ |
| 494 | if (phase == END_OF_FIRMWARE) |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 495 | p2sb_hide(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 496 | } |
| 497 | |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 498 | /* |
| 499 | * spi_init() needs to run unconditionally on every boot (including resume) to |
| 500 | * allow write protect to be disabled for eventlog and nvram updates. This needs |
| 501 | * to be done as early as possible in ramstage. Thus, add a callback for entry |
| 502 | * into BS_PRE_DEVICE. |
| 503 | */ |
| 504 | static void spi_init_cb(void *unused) |
| 505 | { |
| 506 | spi_init(); |
| 507 | } |
| 508 | |
| 509 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL); |