Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 20 | #include <bootstate.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 21 | #include <cbmem.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <cpu/cpu.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <fsp/api.h> |
| 27 | #include <fsp/util.h> |
| 28 | #include <memrange.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 29 | #include <soc/iomap.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 30 | #include <soc/cpu.h> |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 31 | #include <soc/intel/common/vbt.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 32 | #include <soc/nvs.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 34 | #include <spi-generic.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame^] | 35 | #include <soc/pm.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 36 | |
| 37 | #include "chip.h" |
| 38 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 39 | static void *vbt; |
| 40 | static struct region_device vbt_rdev; |
| 41 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 42 | static void pci_domain_set_resources(device_t dev) |
| 43 | { |
| 44 | assign_resources(dev->link_list); |
| 45 | } |
| 46 | |
| 47 | static struct device_operations pci_domain_ops = { |
| 48 | .read_resources = pci_domain_read_resources, |
| 49 | .set_resources = pci_domain_set_resources, |
| 50 | .enable_resources = NULL, |
| 51 | .init = NULL, |
| 52 | .scan_bus = pci_domain_scan_bus, |
| 53 | .ops_pci_bus = pci_bus_default_ops, |
| 54 | }; |
| 55 | |
| 56 | static struct device_operations cpu_bus_ops = { |
| 57 | .read_resources = DEVICE_NOOP, |
| 58 | .set_resources = DEVICE_NOOP, |
| 59 | .enable_resources = DEVICE_NOOP, |
| 60 | .init = apollolake_init_cpus, |
| 61 | .scan_bus = NULL, |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 62 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | static void enable_dev(device_t dev) |
| 66 | { |
| 67 | /* Set the operations if it is a special bus type */ |
| 68 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 69 | dev->ops = &pci_domain_ops; |
| 70 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 71 | dev->ops = &cpu_bus_ops; |
| 72 | } |
| 73 | } |
| 74 | |
| 75 | static void soc_init(void *data) |
| 76 | { |
| 77 | struct range_entry range; |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 78 | struct global_nvs_t *gnvs; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 79 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 80 | /* Save VBT info and mapping */ |
| 81 | if (locate_vbt(&vbt_rdev) != CB_ERR) |
| 82 | vbt = rdev_mmap_full(&vbt_rdev); |
| 83 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 84 | /* TODO: tigten this resource range */ |
| 85 | /* TODO: fix for S3 resume, as this would corrupt OS memory */ |
| 86 | range_entry_init(&range, 0x200000, 4ULL*GiB, 0); |
| 87 | fsp_silicon_init(&range); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 88 | |
| 89 | /* Allocate ACPI NVS in CBMEM */ |
| 90 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 91 | } |
| 92 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 93 | static void soc_final(void *data) |
| 94 | { |
| 95 | if (vbt) |
| 96 | rdev_munmap(&vbt_rdev, vbt); |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame^] | 97 | |
| 98 | /* Disable global reset, just in case */ |
| 99 | global_reset_enable(0); |
| 100 | /* Make sure payload/OS can't trigger global reset */ |
| 101 | global_reset_lock(); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 102 | } |
| 103 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 104 | void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) |
| 105 | { |
| 106 | struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
| 107 | static struct soc_intel_apollolake_config *cfg; |
| 108 | |
| 109 | /* Load VBT before devicetree-specific config. */ |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 110 | silconfig->GraphicsConfigPtr = (uintptr_t)vbt; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 111 | |
Alexandru Gagniuc | 944655d | 2016-05-18 10:26:53 -0700 | [diff] [blame] | 112 | struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); |
Patrick Georgi | 831d65d | 2016-04-14 11:53:48 +0200 | [diff] [blame] | 113 | if (!dev || !dev->chip_info) { |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 114 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 115 | return; |
| 116 | } |
| 117 | |
| 118 | cfg = dev->chip_info; |
| 119 | |
| 120 | silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; |
| 121 | silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; |
| 122 | silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; |
| 123 | silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; |
| 124 | silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; |
| 125 | silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 126 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 127 | if (cfg->emmc_tx_cmd_cntl != 0) |
| 128 | silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; |
| 129 | if (cfg->emmc_tx_data_cntl1 != 0) |
| 130 | silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; |
| 131 | if (cfg->emmc_tx_data_cntl2 != 0) |
| 132 | silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2; |
| 133 | if (cfg->emmc_rx_cmd_data_cntl1 != 0) |
| 134 | silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1; |
| 135 | if (cfg->emmc_rx_strobe_cntl != 0) |
| 136 | silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; |
| 137 | if (cfg->emmc_rx_cmd_data_cntl2 != 0) |
| 138 | silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; |
| 139 | |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 140 | /* Our defaults may not match FSP defaults, so set them explicitly */ |
| 141 | silconfig->AcpiBase = ACPI_PMIO_BASE; |
| 142 | /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ |
| 143 | silconfig->PmcBase = PMC_BAR0 + 0x1000; |
| 144 | silconfig->P2sbBase = P2SB_BAR; |
Hannah Williams | 483004f | 2016-03-28 14:45:59 -0700 | [diff] [blame] | 145 | |
| 146 | silconfig->IshEnable = cfg->integrated_sensor_hub_enable; |
Furquan Shaikh | cad9b63 | 2016-06-20 16:08:42 -0700 | [diff] [blame] | 147 | |
| 148 | /* Disable setting of EISS bit in FSP. */ |
| 149 | silconfig->SpiEiss = 0; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | struct chip_operations soc_intel_apollolake_ops = { |
| 153 | CHIP_NAME("Intel Apollolake SOC") |
| 154 | .enable_dev = &enable_dev, |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 155 | .init = &soc_init, |
| 156 | .final = &soc_final |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 157 | }; |
| 158 | |
| 159 | static void fsp_notify_dummy(void *arg) |
| 160 | { |
| 161 | |
| 162 | enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; |
| 163 | |
| 164 | if (fsp_notify(ph) != FSP_SUCCESS) |
| 165 | printk(BIOS_CRIT, "FspNotify failed!\n"); |
Hannah Williams | 5d9cc78 | 2016-04-29 14:48:20 -0700 | [diff] [blame] | 166 | /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ |
| 167 | if (ph == READY_TO_BOOT) |
| 168 | fsp_notify_dummy((void *)END_OF_FIRMWARE); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 169 | } |
| 170 | |
| 171 | BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, |
| 172 | (void *) AFTER_PCI_ENUM); |
| 173 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, |
| 174 | (void *) READY_TO_BOOT); |
| 175 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, |
| 176 | (void *) READY_TO_BOOT); |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 177 | |
| 178 | /* |
| 179 | * spi_init() needs to run unconditionally on every boot (including resume) to |
| 180 | * allow write protect to be disabled for eventlog and nvram updates. This needs |
| 181 | * to be done as early as possible in ramstage. Thus, add a callback for entry |
| 182 | * into BS_PRE_DEVICE. |
| 183 | */ |
| 184 | static void spi_init_cb(void *unused) |
| 185 | { |
| 186 | spi_init(); |
| 187 | } |
| 188 | |
| 189 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL); |