Angel Pons | c74dae9 | 2020-04-02 23:48:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Uwe Hermann | b80dbf0 | 2007-04-22 19:08:13 +0000 | [diff] [blame] | 2 | |
| 3 | /* |
Martin Roth | 99f83bb | 2019-09-15 20:57:18 -0700 | [diff] [blame] | 4 | * Originally based on the Linux kernel (drivers/pci/pci.c). |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 5 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 8 | #include <acpi/acpi.h> |
Bill XIE | 513d359 | 2022-08-02 22:55:51 +0800 | [diff] [blame] | 9 | #include <assert.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
Edward O'Callaghan | 6c99250 | 2014-06-20 21:19:06 +1000 | [diff] [blame] | 11 | #include <bootmode.h> |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 12 | #include <console/console.h> |
Furquan Shaikh | 871baf2 | 2020-03-12 17:51:24 -0700 | [diff] [blame] | 13 | #include <cpu/cpu.h> |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 14 | #include <stdlib.h> |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 15 | #include <string.h> |
Edward O'Callaghan | 6c99250 | 2014-06-20 21:19:06 +1000 | [diff] [blame] | 16 | #include <delay.h> |
Edward O'Callaghan | 6c99250 | 2014-06-20 21:19:06 +1000 | [diff] [blame] | 17 | #include <device/cardbus.h> |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 21 | #include <device/pcix.h> |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 22 | #include <device/pciexp.h> |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 23 | #include <lib.h> |
Stefan Reinauer | 4d933dd | 2009-07-21 21:36:41 +0000 | [diff] [blame] | 24 | #include <pc80/i8259.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 25 | #include <security/vboot/vbnv.h> |
Martin Roth | 5dd4a2a | 2018-03-06 16:10:45 -0700 | [diff] [blame] | 26 | #include <timestamp.h> |
Johanna Schander | db7a3ae | 2019-07-24 10:14:26 +0200 | [diff] [blame] | 27 | #include <types.h> |
| 28 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 29 | u8 pci_moving_config8(struct device *dev, unsigned int reg) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 30 | { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 31 | u8 value, ones, zeroes; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 32 | |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 33 | value = pci_read_config8(dev, reg); |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 34 | |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 35 | pci_write_config8(dev, reg, 0xff); |
| 36 | ones = pci_read_config8(dev, reg); |
| 37 | |
| 38 | pci_write_config8(dev, reg, 0x00); |
| 39 | zeroes = pci_read_config8(dev, reg); |
| 40 | |
| 41 | pci_write_config8(dev, reg, value); |
| 42 | |
| 43 | return ones ^ zeroes; |
| 44 | } |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 45 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 46 | u16 pci_moving_config16(struct device *dev, unsigned int reg) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 47 | { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 48 | u16 value, ones, zeroes; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 49 | |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 50 | value = pci_read_config16(dev, reg); |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 51 | |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 52 | pci_write_config16(dev, reg, 0xffff); |
| 53 | ones = pci_read_config16(dev, reg); |
| 54 | |
| 55 | pci_write_config16(dev, reg, 0x0000); |
| 56 | zeroes = pci_read_config16(dev, reg); |
| 57 | |
| 58 | pci_write_config16(dev, reg, value); |
| 59 | |
| 60 | return ones ^ zeroes; |
| 61 | } |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 62 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 63 | u32 pci_moving_config32(struct device *dev, unsigned int reg) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 64 | { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 65 | u32 value, ones, zeroes; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 66 | |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 67 | value = pci_read_config32(dev, reg); |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 68 | |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 69 | pci_write_config32(dev, reg, 0xffffffff); |
| 70 | ones = pci_read_config32(dev, reg); |
| 71 | |
| 72 | pci_write_config32(dev, reg, 0x00000000); |
| 73 | zeroes = pci_read_config32(dev, reg); |
| 74 | |
| 75 | pci_write_config32(dev, reg, value); |
| 76 | |
| 77 | return ones ^ zeroes; |
| 78 | } |
| 79 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 80 | /** |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 81 | * Given a device and register, read the size of the BAR for that register. |
| 82 | * |
| 83 | * @param dev Pointer to the device structure. |
| 84 | * @param index Address of the PCI configuration register. |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 85 | * @return TODO |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 86 | */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 87 | struct resource *pci_get_resource(struct device *dev, unsigned long index) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 88 | { |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 89 | struct resource *resource; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 90 | unsigned long value, attr; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 91 | resource_t moving, limit; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 92 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 93 | /* Initialize the resources to nothing. */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 94 | resource = new_resource(dev, index); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 95 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 96 | /* Get the initial value. */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 97 | value = pci_read_config32(dev, index); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 98 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 99 | /* See which bits move. */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 100 | moving = pci_moving_config32(dev, index); |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 101 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 102 | /* Initialize attr to the bits that do not move. */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 103 | attr = value & ~moving; |
| 104 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 105 | /* If it is a 64bit resource look at the high half as well. */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 106 | if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) && |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 107 | ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == |
| 108 | PCI_BASE_ADDRESS_MEM_LIMIT_64)) { |
| 109 | /* Find the high bits that move. */ |
| 110 | moving |= |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 111 | ((resource_t)pci_moving_config32(dev, index + 4)) << 32; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 112 | } |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 113 | |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 114 | /* Find the resource constraints. |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 115 | * Start by finding the bits that move. From there: |
| 116 | * - Size is the least significant bit of the bits that move. |
| 117 | * - Limit is all of the bits that move plus all of the lower bits. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 118 | * See PCI Spec 6.2.5.1. |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 119 | */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 120 | limit = 0; |
| 121 | if (moving) { |
| 122 | resource->size = 1; |
| 123 | resource->align = resource->gran = 0; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 124 | while (!(moving & resource->size)) { |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 125 | resource->size <<= 1; |
| 126 | resource->align += 1; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 127 | resource->gran += 1; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 128 | } |
| 129 | resource->limit = limit = moving | (resource->size - 1); |
Nico Huber | 8193b06 | 2015-10-21 15:43:41 +0200 | [diff] [blame] | 130 | |
| 131 | if (pci_base_address_is_memory_space(attr)) { |
| 132 | /* Page-align to allow individual mapping of devices. */ |
| 133 | if (resource->align < 12) |
| 134 | resource->align = 12; |
| 135 | } |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 136 | } |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 137 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 138 | /* |
| 139 | * Some broken hardware has read-only registers that do not |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 140 | * really size correctly. |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 141 | * |
| 142 | * Example: the Acer M7229 has BARs 1-4 normally read-only, |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 143 | * so BAR1 at offset 0x10 reads 0x1f1. If you size that register |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 144 | * by writing 0xffffffff to it, it will read back as 0x1f1 -- which |
| 145 | * is a violation of the spec. |
| 146 | * |
| 147 | * We catch this case and ignore it by observing which bits move. |
| 148 | * |
| 149 | * This also catches the common case of unimplemented registers |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 150 | * that always read back as 0. |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 151 | */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 152 | if (moving == 0) { |
| 153 | if (value != 0) { |
Angel Pons | d19cc11 | 2021-07-04 11:41:31 +0200 | [diff] [blame] | 154 | printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n", |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 155 | dev_path(dev), index, value); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 156 | } |
| 157 | resource->flags = 0; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 158 | } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) { |
| 159 | /* An I/O mapped base address. */ |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 160 | resource->flags |= IORESOURCE_IO; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 161 | /* I don't want to deal with 32bit I/O resources. */ |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 162 | resource->limit = 0xffff; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 163 | } else { |
| 164 | /* A Memory mapped base address. */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 165 | attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 166 | resource->flags |= IORESOURCE_MEM; |
Nico Huber | 577c6b9 | 2022-08-15 00:08:58 +0200 | [diff] [blame] | 167 | if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) { |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 168 | resource->flags |= IORESOURCE_PREFETCH; |
Nico Huber | 577c6b9 | 2022-08-15 00:08:58 +0200 | [diff] [blame] | 169 | if (CONFIG(PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G) |
| 170 | && dev_path_hotplug(dev)) |
| 171 | resource->flags |= IORESOURCE_ABOVE_4G; |
| 172 | } |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 173 | attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; |
| 174 | if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 175 | /* 32bit limit. */ |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 176 | resource->limit = 0xffffffffUL; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 177 | } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { |
| 178 | /* 1MB limit. */ |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 179 | resource->limit = 0x000fffffUL; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 180 | } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { |
| 181 | /* 64bit limit. */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 182 | resource->limit = 0xffffffffffffffffULL; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 183 | resource->flags |= IORESOURCE_PCI64; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 184 | } else { |
| 185 | /* Invalid value. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 186 | printk(BIOS_ERR, "Broken BAR with value %lx\n", attr); |
| 187 | printk(BIOS_ERR, " on dev %s at index %02lx\n", |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 188 | dev_path(dev), index); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 189 | resource->flags = 0; |
| 190 | } |
| 191 | } |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 192 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 193 | /* Don't let the limit exceed which bits can move. */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 194 | if (resource->limit > limit) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 195 | resource->limit = limit; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 196 | |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 197 | return resource; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 198 | } |
| 199 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 200 | /** |
| 201 | * Given a device and an index, read the size of the BAR for that register. |
| 202 | * |
| 203 | * @param dev Pointer to the device structure. |
| 204 | * @param index Address of the PCI configuration register. |
| 205 | */ |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 206 | static void pci_get_rom_resource(struct device *dev, unsigned long index) |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 207 | { |
| 208 | struct resource *resource; |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 209 | unsigned long value; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 210 | resource_t moving; |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 211 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 212 | /* Initialize the resources to nothing. */ |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 213 | resource = new_resource(dev, index); |
| 214 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 215 | /* Get the initial value. */ |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 216 | value = pci_read_config32(dev, index); |
| 217 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 218 | /* See which bits move. */ |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 219 | moving = pci_moving_config32(dev, index); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 220 | |
| 221 | /* Clear the Enable bit. */ |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 222 | moving = moving & ~PCI_ROM_ADDRESS_ENABLE; |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 223 | |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 224 | /* Find the resource constraints. |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 225 | * Start by finding the bits that move. From there: |
| 226 | * - Size is the least significant bit of the bits that move. |
| 227 | * - Limit is all of the bits that move plus all of the lower bits. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 228 | * See PCI Spec 6.2.5.1. |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 229 | */ |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 230 | if (moving) { |
| 231 | resource->size = 1; |
| 232 | resource->align = resource->gran = 0; |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 233 | while (!(moving & resource->size)) { |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 234 | resource->size <<= 1; |
| 235 | resource->align += 1; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 236 | resource->gran += 1; |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 237 | } |
Patrick Georgi | 16cdbb2 | 2009-04-21 20:14:31 +0000 | [diff] [blame] | 238 | resource->limit = moving | (resource->size - 1); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 239 | resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY; |
| 240 | } else { |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 241 | if (value != 0) { |
Angel Pons | d19cc11 | 2021-07-04 11:41:31 +0200 | [diff] [blame] | 242 | printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n", |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 243 | dev_path(dev), index, value); |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 244 | } |
| 245 | resource->flags = 0; |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 246 | } |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 247 | compact_resources(dev); |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 248 | } |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 249 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 250 | /** |
Patrick Rudolph | 4e2f95b | 2018-05-16 14:56:22 +0200 | [diff] [blame] | 251 | * Given a device, read the size of the MSI-X table. |
| 252 | * |
| 253 | * @param dev Pointer to the device structure. |
| 254 | * @return MSI-X table size or 0 if not MSI-X capable device |
| 255 | */ |
| 256 | size_t pci_msix_table_size(struct device *dev) |
| 257 | { |
| 258 | const size_t pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
| 259 | if (!pos) |
| 260 | return 0; |
| 261 | |
| 262 | const u16 control = pci_read_config16(dev, pos + PCI_MSIX_FLAGS); |
| 263 | return (control & PCI_MSIX_FLAGS_QSIZE) + 1; |
| 264 | } |
| 265 | |
| 266 | /** |
| 267 | * Given a device, return the table offset and bar the MSI-X tables resides in. |
| 268 | * |
| 269 | * @param dev Pointer to the device structure. |
| 270 | * @param offset Returned value gives the offset in bytes inside the PCI BAR. |
| 271 | * @param idx The returned value is the index of the PCI_BASE_ADDRESS register |
| 272 | * the MSI-X table is located in. |
| 273 | * @return Zero on success |
| 274 | */ |
| 275 | int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx) |
| 276 | { |
| 277 | const size_t pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
| 278 | if (!pos || !offset || !idx) |
| 279 | return 1; |
| 280 | |
| 281 | *offset = pci_read_config32(dev, pos + PCI_MSIX_TABLE); |
| 282 | *idx = (u8)(*offset & PCI_MSIX_PBA_BIR); |
| 283 | *offset &= PCI_MSIX_PBA_OFFSET; |
| 284 | |
| 285 | return 0; |
| 286 | } |
| 287 | |
| 288 | /** |
| 289 | * Given a device, return a msix_entry pointer or NULL if no table was found. |
| 290 | * |
| 291 | * @param dev Pointer to the device structure. |
| 292 | * |
| 293 | * @return NULL on error |
| 294 | */ |
| 295 | struct msix_entry *pci_msix_get_table(struct device *dev) |
| 296 | { |
| 297 | struct resource *res; |
| 298 | u32 offset; |
| 299 | u8 idx; |
| 300 | |
| 301 | if (pci_msix_table_bar(dev, &offset, &idx)) |
| 302 | return NULL; |
| 303 | |
| 304 | if (idx > 5) |
| 305 | return NULL; |
| 306 | |
| 307 | res = probe_resource(dev, idx * 4 + PCI_BASE_ADDRESS_0); |
| 308 | if (!res || !res->base || offset >= res->size) |
| 309 | return NULL; |
| 310 | |
| 311 | if ((res->flags & IORESOURCE_PCI64) && |
| 312 | (uintptr_t)res->base != res->base) |
| 313 | return NULL; |
| 314 | |
| 315 | return (struct msix_entry *)((uintptr_t)res->base + offset); |
| 316 | } |
| 317 | |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 318 | static unsigned int get_rebar_offset(const struct device *dev, unsigned long index) |
| 319 | { |
Nico Huber | 5ffc2c8 | 2022-08-05 12:58:18 +0200 | [diff] [blame] | 320 | uint32_t offset = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_RESIZABLE_BAR, 0); |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 321 | if (!offset) |
| 322 | return 0; |
| 323 | |
| 324 | /* Convert PCI_BASE_ADDRESS_0, ..._1, ..._2 into 0, 1, 2... */ |
| 325 | const unsigned int find_bar_idx = (index - PCI_BASE_ADDRESS_0) / |
| 326 | sizeof(uint32_t); |
| 327 | |
| 328 | /* Although all of the Resizable BAR Control Registers contain an |
| 329 | "NBARs" field, it is only valid in the Control Register for BAR 0 */ |
| 330 | const uint32_t rebar_ctrl0 = pci_read_config32(dev, offset + PCI_REBAR_CTRL_OFFSET); |
| 331 | const unsigned int nbars = (rebar_ctrl0 & PCI_REBAR_CTRL_NBARS_MASK) >> |
| 332 | PCI_REBAR_CTRL_NBARS_SHIFT; |
| 333 | |
| 334 | for (unsigned int i = 0; i < nbars; i++, offset += sizeof(uint64_t)) { |
| 335 | const uint32_t rebar_ctrl = pci_read_config32( |
| 336 | dev, offset + PCI_REBAR_CTRL_OFFSET); |
| 337 | const uint32_t bar_idx = rebar_ctrl & PCI_REBAR_CTRL_IDX_MASK; |
| 338 | if (bar_idx == find_bar_idx) |
| 339 | return offset; |
| 340 | } |
| 341 | |
| 342 | return 0; |
| 343 | } |
| 344 | |
| 345 | /* Bit 20 = 1 MiB, bit 21 = 2 MiB, bit 22 = 4 MiB, ... bit 63 = 8 EiB */ |
| 346 | static uint64_t get_rebar_sizes_mask(const struct device *dev, |
| 347 | unsigned long index) |
| 348 | { |
| 349 | uint64_t size_mask = 0ULL; |
| 350 | const uint32_t offset = get_rebar_offset(dev, index); |
| 351 | if (!offset) |
| 352 | return 0; |
| 353 | |
| 354 | /* Get 1 MB - 128 TB support from CAP register */ |
| 355 | const uint32_t cap = pci_read_config32(dev, offset + PCI_REBAR_CAP_OFFSET); |
| 356 | /* Shift the bits from 4-31 to 0-27 (i.e., down by 4 bits) */ |
| 357 | size_mask |= ((cap & PCI_REBAR_CAP_SIZE_MASK) >> 4); |
| 358 | |
| 359 | /* Get 256 TB - 8 EB support from CTRL register and store it in bits 28-43 */ |
| 360 | const uint64_t ctrl = pci_read_config32(dev, offset + PCI_REBAR_CTRL_OFFSET); |
| 361 | /* Shift ctrl mask from bit 16 to bit 28, so that the two |
| 362 | masks (fom cap and ctrl) form a contiguous bitmask when |
| 363 | concatenated (i.e., up by 12 bits). */ |
| 364 | size_mask |= ((ctrl & PCI_REBAR_CTRL_SIZE_MASK) << 12); |
| 365 | |
| 366 | /* Now that the mask occupies bits 0-43, shift it up to 20-63, so they |
| 367 | represent the actual powers of 2. */ |
| 368 | return size_mask << 20; |
| 369 | } |
| 370 | |
| 371 | static void pci_store_rebar_size(const struct device *dev, |
| 372 | const struct resource *resource) |
| 373 | { |
| 374 | const unsigned int num_bits = __fls64(resource->size); |
| 375 | const uint32_t offset = get_rebar_offset(dev, resource->index); |
| 376 | if (!offset) |
| 377 | return; |
| 378 | |
| 379 | pci_update_config32(dev, offset + PCI_REBAR_CTRL_OFFSET, |
| 380 | ~PCI_REBAR_CTRL_SIZE_MASK, |
| 381 | num_bits << PCI_REBAR_CTRL_SIZE_SHIFT); |
| 382 | } |
| 383 | |
| 384 | static void configure_adjustable_base(const struct device *dev, |
| 385 | unsigned long index, |
| 386 | struct resource *res) |
| 387 | { |
| 388 | /* |
| 389 | * Excerpt from an implementation note from the PCIe spec: |
| 390 | * |
| 391 | * System software uses this capability in place of the above mentioned |
| 392 | * method of determining the resource size[0], and prior to assigning |
| 393 | * the base address to the BAR. Potential usable resource sizes are |
| 394 | * reported by the Function via its Resizable BAR Capability and Control |
| 395 | * registers. It is intended that the software allocate the largest of |
| 396 | * the reported sizes that it can, since allocating less address space |
| 397 | * than the largest reported size can result in lower |
| 398 | * performance. Software then writes the size to the Resizable BAR |
| 399 | * Control register for the appropriate BAR for the Function. Following |
| 400 | * this, the base address is written to the BAR. |
| 401 | * |
| 402 | * [0] Referring to using the moving bits in the BAR to determine the |
| 403 | * requested size of the MMIO region |
| 404 | */ |
| 405 | const uint64_t size_mask = get_rebar_sizes_mask(dev, index); |
| 406 | if (!size_mask) |
| 407 | return; |
| 408 | |
| 409 | int max_requested_bits = __fls64(size_mask); |
| 410 | if (max_requested_bits > CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS) { |
Elyes Haouas | aba1c94 | 2022-11-09 15:05:23 +0100 | [diff] [blame] | 411 | printk(BIOS_WARNING, "Device %s requests a BAR with" |
Paul Menzel | d579d80 | 2022-09-06 08:25:28 +0200 | [diff] [blame] | 412 | " %u bits of address space, which coreboot is not" |
| 413 | " configured to hand out, truncating to %u bits\n", |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 414 | dev_path(dev), max_requested_bits, |
| 415 | CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS); |
| 416 | max_requested_bits = CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS; |
| 417 | } |
| 418 | |
| 419 | if (!(res->flags & IORESOURCE_PCI64) && max_requested_bits > 32) { |
Elyes Haouas | aba1c94 | 2022-11-09 15:05:23 +0100 | [diff] [blame] | 420 | printk(BIOS_ERR, "Resizable BAR requested" |
Paul Menzel | d579d80 | 2022-09-06 08:25:28 +0200 | [diff] [blame] | 421 | " above 32 bits, but PCI function reported a" |
| 422 | " 32-bit BAR."); |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 423 | return; |
| 424 | } |
| 425 | |
| 426 | /* Configure the resource parameters for the adjustable BAR */ |
| 427 | res->size = 1ULL << max_requested_bits; |
| 428 | res->align = max_requested_bits; |
| 429 | res->gran = max_requested_bits; |
| 430 | res->limit = (res->flags & IORESOURCE_PCI64) ? UINT64_MAX : UINT32_MAX; |
Tim Wawrzynczak | 2b83fa7 | 2022-05-27 12:27:50 -0600 | [diff] [blame] | 431 | res->flags |= (res->flags & IORESOURCE_PCI64) ? |
| 432 | IORESOURCE_PCIE_RESIZABLE_BAR | IORESOURCE_ABOVE_4G : |
| 433 | IORESOURCE_PCIE_RESIZABLE_BAR; |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 434 | |
| 435 | printk(BIOS_INFO, "%s: Adjusting resource index %lu: base: %llx size: %llx " |
| 436 | "align: %d gran: %d limit: %llx\n", |
| 437 | dev_path(dev), res->index, res->base, res->size, |
| 438 | res->align, res->gran, res->limit); |
| 439 | } |
| 440 | |
Patrick Rudolph | 4e2f95b | 2018-05-16 14:56:22 +0200 | [diff] [blame] | 441 | /** |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 442 | * Read the base address registers for a given device. |
| 443 | * |
| 444 | * @param dev Pointer to the dev structure. |
| 445 | * @param howmany How many registers to read (6 for device, 2 for bridge). |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 446 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 447 | static void pci_read_bases(struct device *dev, unsigned int howmany) |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 448 | { |
| 449 | unsigned long index; |
| 450 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 451 | for (index = PCI_BASE_ADDRESS_0; |
| 452 | (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 453 | struct resource *resource; |
| 454 | resource = pci_get_resource(dev, index); |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 455 | |
| 456 | const bool is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE) != 0; |
| 457 | if (CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS) && is_pcie) |
| 458 | configure_adjustable_base(dev, index, resource); |
| 459 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 460 | index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 461 | } |
Li-Ta Lo | e8b1c9d | 2004-12-27 04:25:41 +0000 | [diff] [blame] | 462 | |
| 463 | compact_resources(dev); |
Li-Ta Lo | 9a5b496 | 2004-12-23 21:48:01 +0000 | [diff] [blame] | 464 | } |
| 465 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 466 | static void pci_record_bridge_resource(struct device *dev, resource_t moving, |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 467 | unsigned int index, unsigned long type) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 468 | { |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 469 | struct resource *resource; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 470 | unsigned long gran; |
| 471 | resource_t step; |
| 472 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 473 | resource = NULL; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 474 | |
| 475 | if (!moving) |
| 476 | return; |
| 477 | |
| 478 | /* Initialize the constraints on the current bus. */ |
| 479 | resource = new_resource(dev, index); |
| 480 | resource->size = 0; |
| 481 | gran = 0; |
| 482 | step = 1; |
| 483 | while ((moving & step) == 0) { |
| 484 | gran += 1; |
| 485 | step <<= 1; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 486 | } |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 487 | resource->gran = gran; |
| 488 | resource->align = gran; |
| 489 | resource->limit = moving | (step - 1); |
| 490 | resource->flags = type | IORESOURCE_PCI_BRIDGE | |
| 491 | IORESOURCE_BRIDGE; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 492 | } |
| 493 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 494 | static void pci_bridge_read_bases(struct device *dev) |
| 495 | { |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 496 | resource_t moving_base, moving_limit, moving; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 497 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 498 | /* See if the bridge I/O resources are implemented. */ |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 499 | moving_base = ((u32)pci_moving_config8(dev, PCI_IO_BASE)) << 8; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 500 | moving_base |= |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 501 | ((u32)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 502 | |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 503 | moving_limit = ((u32)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 504 | moving_limit |= |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 505 | ((u32)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 506 | |
| 507 | moving = moving_base & moving_limit; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 508 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 509 | /* Initialize the I/O space constraints on the current bus. */ |
| 510 | pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 511 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 512 | /* See if the bridge prefmem resources are implemented. */ |
| 513 | moving_base = |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 514 | ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 515 | moving_base |= |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 516 | ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 517 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 518 | moving_limit = |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 519 | ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 520 | moving_limit |= |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 521 | ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32; |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 522 | |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 523 | moving = moving_base & moving_limit; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 524 | /* Initialize the prefetchable memory constraints on the current bus. */ |
| 525 | pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE, |
| 526 | IORESOURCE_MEM | IORESOURCE_PREFETCH); |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 527 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 528 | /* See if the bridge mem resources are implemented. */ |
Elyes Haouas | d369c66 | 2022-11-18 15:06:21 +0100 | [diff] [blame] | 529 | moving_base = ((u32)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16; |
| 530 | moving_limit = ((u32)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 531 | |
| 532 | moving = moving_base & moving_limit; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 533 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 534 | /* Initialize the memory resources on the current bus. */ |
| 535 | pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE, |
| 536 | IORESOURCE_MEM); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 537 | |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 538 | compact_resources(dev); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 539 | } |
| 540 | |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 541 | void pci_dev_read_resources(struct device *dev) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 542 | { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 543 | pci_read_bases(dev, 6); |
| 544 | pci_get_rom_resource(dev, PCI_ROM_ADDRESS); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 545 | } |
| 546 | |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 547 | void pci_bus_read_resources(struct device *dev) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 548 | { |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 549 | pci_bridge_read_bases(dev); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 550 | pci_read_bases(dev, 2); |
| 551 | pci_get_rom_resource(dev, PCI_ROM_ADDRESS1); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 552 | } |
| 553 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 554 | void pci_domain_read_resources(struct device *dev) |
| 555 | { |
| 556 | struct resource *res; |
| 557 | |
| 558 | /* Initialize the system-wide I/O space constraints. */ |
| 559 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 560 | res->limit = 0xffffUL; |
| 561 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 562 | IORESOURCE_ASSIGNED; |
| 563 | |
| 564 | /* Initialize the system-wide memory resources constraints. */ |
| 565 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
Furquan Shaikh | 871baf2 | 2020-03-12 17:51:24 -0700 | [diff] [blame] | 566 | res->limit = (1ULL << cpu_phys_address_size()) - 1; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 567 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 568 | IORESOURCE_ASSIGNED; |
| 569 | } |
| 570 | |
Raul E Rangel | 5cb34e2 | 2020-05-04 16:41:22 -0600 | [diff] [blame] | 571 | void pci_domain_set_resources(struct device *dev) |
| 572 | { |
| 573 | assign_resources(dev->link_list); |
| 574 | } |
| 575 | |
Nico Huber | 730b261 | 2020-05-20 00:32:50 +0200 | [diff] [blame] | 576 | static void pci_store_resource(const struct device *const dev, |
| 577 | const struct resource *const resource) |
| 578 | { |
| 579 | unsigned long base_lo, base_hi; |
| 580 | |
| 581 | base_lo = resource->base & 0xffffffff; |
| 582 | base_hi = (resource->base >> 32) & 0xffffffff; |
| 583 | |
| 584 | /* |
| 585 | * Some chipsets allow us to set/clear the I/O bit |
| 586 | * (e.g. VIA 82C686A). So set it to be safe. |
| 587 | */ |
| 588 | if (resource->flags & IORESOURCE_IO) |
| 589 | base_lo |= PCI_BASE_ADDRESS_SPACE_IO; |
| 590 | |
| 591 | pci_write_config32(dev, resource->index, base_lo); |
| 592 | if (resource->flags & IORESOURCE_PCI64) |
| 593 | pci_write_config32(dev, resource->index + 4, base_hi); |
| 594 | } |
| 595 | |
| 596 | static void pci_store_bridge_resource(const struct device *const dev, |
| 597 | struct resource *const resource) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 598 | { |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 599 | resource_t base, end; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 600 | |
Nico Huber | 730b261 | 2020-05-20 00:32:50 +0200 | [diff] [blame] | 601 | /* |
| 602 | * PCI bridges have no enable bit. They are disabled if the base of |
| 603 | * the range is greater than the limit. If the size is zero, disable |
| 604 | * by setting the base = limit and end = limit - 2^gran. |
| 605 | */ |
| 606 | if (resource->size == 0) { |
| 607 | base = resource->limit; |
| 608 | end = resource->limit - (1 << resource->gran); |
| 609 | resource->base = base; |
| 610 | } else { |
| 611 | base = resource->base; |
| 612 | end = resource_end(resource); |
| 613 | } |
| 614 | |
| 615 | if (resource->index == PCI_IO_BASE) { |
| 616 | /* Set the I/O ranges. */ |
| 617 | pci_write_config8(dev, PCI_IO_BASE, base >> 8); |
| 618 | pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16); |
| 619 | pci_write_config8(dev, PCI_IO_LIMIT, end >> 8); |
| 620 | pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16); |
| 621 | } else if (resource->index == PCI_MEMORY_BASE) { |
| 622 | /* Set the memory range. */ |
| 623 | pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); |
| 624 | pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16); |
| 625 | } else if (resource->index == PCI_PREF_MEMORY_BASE) { |
| 626 | /* Set the prefetchable memory range. */ |
| 627 | pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16); |
| 628 | pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32); |
| 629 | pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16); |
| 630 | pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32); |
| 631 | } else { |
| 632 | /* Don't let me think I stored the resource. */ |
| 633 | resource->flags &= ~IORESOURCE_STORED; |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 634 | printk(BIOS_ERR, "invalid resource->index %lx\n", resource->index); |
Nico Huber | 730b261 | 2020-05-20 00:32:50 +0200 | [diff] [blame] | 635 | } |
| 636 | } |
| 637 | |
| 638 | static void pci_set_resource(struct device *dev, struct resource *resource) |
| 639 | { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 640 | /* Make certain the resource has actually been assigned a value. */ |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 641 | if (!(resource->flags & IORESOURCE_ASSIGNED)) { |
Nico Huber | f531244 | 2020-05-20 01:02:18 +0200 | [diff] [blame] | 642 | if (resource->flags & IORESOURCE_BRIDGE) { |
| 643 | /* If a bridge resource has no value assigned, |
| 644 | we can treat it like an empty resource. */ |
| 645 | resource->size = 0; |
| 646 | } else { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 647 | printk(BIOS_ERR, "%s %02lx %s size: 0x%010llx not assigned\n", |
Angel Pons | d19cc11 | 2021-07-04 11:41:31 +0200 | [diff] [blame] | 648 | dev_path(dev), resource->index, |
Nico Huber | f531244 | 2020-05-20 01:02:18 +0200 | [diff] [blame] | 649 | resource_type(resource), resource->size); |
| 650 | return; |
| 651 | } |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 652 | } |
| 653 | |
Myles Watson | eb81a5b | 2009-11-05 20:06:19 +0000 | [diff] [blame] | 654 | /* If this resource is fixed don't worry about it. */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 655 | if (resource->flags & IORESOURCE_FIXED) |
Myles Watson | eb81a5b | 2009-11-05 20:06:19 +0000 | [diff] [blame] | 656 | return; |
Myles Watson | eb81a5b | 2009-11-05 20:06:19 +0000 | [diff] [blame] | 657 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 658 | /* If I have already stored this resource don't worry about it. */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 659 | if (resource->flags & IORESOURCE_STORED) |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 660 | return; |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 661 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 662 | /* If the resource is subtractive don't worry about it. */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 663 | if (resource->flags & IORESOURCE_SUBTRACTIVE) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 664 | return; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 665 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 666 | /* Only handle PCI memory and I/O resources for now. */ |
| 667 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 668 | return; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 669 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 670 | /* Enable the resources in the command register. */ |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 671 | if (resource->size) { |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 672 | if (resource->flags & IORESOURCE_MEM) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 673 | dev->command |= PCI_COMMAND_MEMORY; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 674 | if (resource->flags & IORESOURCE_IO) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 675 | dev->command |= PCI_COMMAND_IO; |
Felix Singer | 205b53e | 2020-09-07 15:21:21 +0200 | [diff] [blame] | 676 | if (resource->flags & IORESOURCE_PCI_BRIDGE && |
| 677 | CONFIG(PCI_SET_BUS_MASTER_PCI_BRIDGES)) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 678 | dev->command |= PCI_COMMAND_MASTER; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 679 | } |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 680 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 681 | /* Now store the resource. */ |
Eric Biederman | 5cd8173 | 2004-03-11 15:01:31 +0000 | [diff] [blame] | 682 | resource->flags |= IORESOURCE_STORED; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 683 | |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 684 | if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) { |
| 685 | if (CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS) && |
| 686 | (resource->flags & IORESOURCE_PCIE_RESIZABLE_BAR)) |
| 687 | pci_store_rebar_size(dev, resource); |
| 688 | |
Nico Huber | 730b261 | 2020-05-20 00:32:50 +0200 | [diff] [blame] | 689 | pci_store_resource(dev, resource); |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 690 | |
Tim Wawrzynczak | 8c93fed | 2022-01-13 16:45:07 -0700 | [diff] [blame] | 691 | } else { |
| 692 | pci_store_bridge_resource(dev, resource); |
| 693 | } |
| 694 | |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 695 | report_resource_stored(dev, resource, ""); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 696 | } |
| 697 | |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 698 | void pci_dev_set_resources(struct device *dev) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 699 | { |
Myles Watson | c25cc11 | 2010-05-21 14:33:48 +0000 | [diff] [blame] | 700 | struct resource *res; |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 701 | struct bus *bus; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 702 | u8 line; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 703 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 704 | for (res = dev->resource_list; res; res = res->next) |
Myles Watson | c25cc11 | 2010-05-21 14:33:48 +0000 | [diff] [blame] | 705 | pci_set_resource(dev, res); |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 706 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 707 | for (bus = dev->link_list; bus; bus = bus->next) { |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 708 | if (bus->children) |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 709 | assign_resources(bus); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 710 | } |
| 711 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 712 | /* Set a default latency timer. */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 713 | pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 714 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 715 | /* Set a default secondary latency timer. */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 716 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 717 | pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 718 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 719 | /* Zero the IRQ settings. */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 720 | line = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 721 | if (line) |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 722 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 723 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 724 | /* Set the cache line size, so far 64 bytes is good for everyone. */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 725 | pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 726 | } |
| 727 | |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 728 | void pci_dev_enable_resources(struct device *dev) |
| 729 | { |
Kyösti Mälkki | cac0231 | 2019-06-30 08:40:04 +0300 | [diff] [blame] | 730 | const struct pci_operations *ops = NULL; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 731 | u16 command; |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 732 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 733 | /* Set the subsystem vendor and device ID for mainboard devices. */ |
Kyösti Mälkki | cac0231 | 2019-06-30 08:40:04 +0300 | [diff] [blame] | 734 | if (dev->ops) |
| 735 | ops = dev->ops->ops_pci; |
Eric Biederman | dbec2d4 | 2004-10-21 10:44:08 +0000 | [diff] [blame] | 736 | if (dev->on_mainboard && ops && ops->set_subsystem) { |
Duncan Laurie | 7e1c83e | 2013-08-09 07:55:10 -0700 | [diff] [blame] | 737 | if (CONFIG_SUBSYSTEM_VENDOR_ID) |
| 738 | dev->subsystem_vendor = CONFIG_SUBSYSTEM_VENDOR_ID; |
Rizwan Qureshi | fd89129 | 2017-04-26 21:00:37 +0530 | [diff] [blame] | 739 | else if (!dev->subsystem_vendor) |
| 740 | dev->subsystem_vendor = pci_read_config16(dev, |
| 741 | PCI_VENDOR_ID); |
Duncan Laurie | 7e1c83e | 2013-08-09 07:55:10 -0700 | [diff] [blame] | 742 | if (CONFIG_SUBSYSTEM_DEVICE_ID) |
| 743 | dev->subsystem_device = CONFIG_SUBSYSTEM_DEVICE_ID; |
Rizwan Qureshi | fd89129 | 2017-04-26 21:00:37 +0530 | [diff] [blame] | 744 | else if (!dev->subsystem_device) |
| 745 | dev->subsystem_device = pci_read_config16(dev, |
| 746 | PCI_DEVICE_ID); |
| 747 | |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 748 | printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n", |
| 749 | dev_path(dev), dev->subsystem_vendor, |
| 750 | dev->subsystem_device); |
| 751 | ops->set_subsystem(dev, dev->subsystem_vendor, |
| 752 | dev->subsystem_device); |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 753 | } |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 754 | command = pci_read_config16(dev, PCI_COMMAND); |
| 755 | command |= dev->command; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 756 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 757 | /* v3 has |
| 758 | * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check. |
| 759 | */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 760 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 761 | printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 762 | pci_write_config16(dev, PCI_COMMAND, command); |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 763 | } |
| 764 | |
| 765 | void pci_bus_enable_resources(struct device *dev) |
| 766 | { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 767 | u16 ctrl; |
| 768 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 769 | /* |
| 770 | * Enable I/O in command register if there is VGA card |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 771 | * connected with (even it does not claim I/O resource). |
| 772 | */ |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 773 | if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
Li-Ta Lo | 515f6c7 | 2005-01-11 22:48:54 +0000 | [diff] [blame] | 774 | dev->command |= PCI_COMMAND_IO; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 775 | ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 776 | ctrl |= dev->link_list->bridge_ctrl; |
Kyösti Mälkki | 382e216 | 2019-09-21 16:19:32 +0300 | [diff] [blame] | 777 | ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* Error check. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 778 | printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 779 | pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); |
| 780 | |
| 781 | pci_dev_enable_resources(dev); |
| 782 | } |
| 783 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 784 | void pci_bus_reset(struct bus *bus) |
| 785 | { |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 786 | u16 ctl; |
| 787 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 788 | ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); |
| 789 | ctl |= PCI_BRIDGE_CTL_BUS_RESET; |
| 790 | pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl); |
| 791 | mdelay(10); |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 792 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 793 | ctl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
| 794 | pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl); |
| 795 | delay(1); |
| 796 | } |
| 797 | |
Elyes HAOUAS | 88030b7 | 2018-09-20 17:26:10 +0200 | [diff] [blame] | 798 | void pci_dev_set_subsystem(struct device *dev, unsigned int vendor, |
| 799 | unsigned int device) |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 800 | { |
Subrata Banik | 9514d47 | 2019-03-20 14:56:27 +0530 | [diff] [blame] | 801 | uint8_t offset; |
| 802 | |
| 803 | /* Header type */ |
| 804 | switch (dev->hdr_type & 0x7f) { |
| 805 | case PCI_HEADER_TYPE_NORMAL: |
| 806 | offset = PCI_SUBSYSTEM_VENDOR_ID; |
| 807 | break; |
| 808 | case PCI_HEADER_TYPE_BRIDGE: |
| 809 | offset = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
| 810 | if (!offset) |
| 811 | return; |
| 812 | offset += 4; /* Vendor ID at offset 4 */ |
| 813 | break; |
| 814 | case PCI_HEADER_TYPE_CARDBUS: |
| 815 | offset = PCI_CB_SUBSYSTEM_VENDOR_ID; |
| 816 | break; |
| 817 | default: |
| 818 | return; |
| 819 | } |
| 820 | |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 821 | if (!vendor || !device) { |
Subrata Banik | 9514d47 | 2019-03-20 14:56:27 +0530 | [diff] [blame] | 822 | pci_write_config32(dev, offset, |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 823 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 824 | } else { |
Subrata Banik | 9514d47 | 2019-03-20 14:56:27 +0530 | [diff] [blame] | 825 | pci_write_config32(dev, offset, |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 826 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 827 | } |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 828 | } |
| 829 | |
Frans Hendriks | b71181a | 2019-10-04 14:06:33 +0200 | [diff] [blame] | 830 | static int should_run_oprom(struct device *dev, struct rom_header *rom) |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 831 | { |
| 832 | static int should_run = -1; |
| 833 | |
Frans Hendriks | b71181a | 2019-10-04 14:06:33 +0200 | [diff] [blame] | 834 | if (CONFIG(VENDORCODE_ELTAN_VBOOT)) |
| 835 | if (rom != NULL) |
| 836 | if (!verified_boot_should_run_oprom(rom)) |
| 837 | return 0; |
| 838 | |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 839 | if (should_run >= 0) |
| 840 | return should_run; |
| 841 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 842 | if (CONFIG(ALWAYS_RUN_OPROM)) { |
Aaron Durbin | 1051025 | 2018-01-30 10:04:02 -0700 | [diff] [blame] | 843 | should_run = 1; |
| 844 | return should_run; |
| 845 | } |
| 846 | |
Kyösti Mälkki | 9ab1c10 | 2013-12-22 00:22:49 +0200 | [diff] [blame] | 847 | /* Don't run VGA option ROMs, unless we have to print |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 848 | * something on the screen before the kernel is loaded. |
| 849 | */ |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 850 | should_run = display_init_required(); |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 851 | |
Kyösti Mälkki | 9ab1c10 | 2013-12-22 00:22:49 +0200 | [diff] [blame] | 852 | if (!should_run) |
| 853 | printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 854 | return should_run; |
| 855 | } |
| 856 | |
| 857 | static int should_load_oprom(struct device *dev) |
| 858 | { |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 859 | /* If S3_VGA_ROM_RUN is disabled, skip running VGA option |
| 860 | * ROMs when coming out of an S3 resume. |
| 861 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 862 | if (!CONFIG(S3_VGA_ROM_RUN) && acpi_is_wakeup_s3() && |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 863 | ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) |
| 864 | return 0; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 865 | if (CONFIG(ALWAYS_LOAD_OPROM)) |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 866 | return 1; |
Frans Hendriks | b71181a | 2019-10-04 14:06:33 +0200 | [diff] [blame] | 867 | if (should_run_oprom(dev, NULL)) |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 868 | return 1; |
| 869 | |
| 870 | return 0; |
| 871 | } |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 872 | |
Kyösti Mälkki | 0f30063 | 2020-12-19 23:43:56 +0200 | [diff] [blame] | 873 | static void oprom_pre_graphics_stall(void) |
| 874 | { |
Paul Menzel | c4062c7 | 2021-02-11 10:43:14 +0100 | [diff] [blame] | 875 | if (CONFIG_PRE_GRAPHICS_DELAY_MS) |
| 876 | mdelay(CONFIG_PRE_GRAPHICS_DELAY_MS); |
Kyösti Mälkki | 0f30063 | 2020-12-19 23:43:56 +0200 | [diff] [blame] | 877 | } |
| 878 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 879 | /** Default handler: only runs the relevant PCI BIOS. */ |
Li-Ta Lo | 883b879 | 2005-01-10 23:16:22 +0000 | [diff] [blame] | 880 | void pci_dev_init(struct device *dev) |
| 881 | { |
| 882 | struct rom_header *rom, *ram; |
| 883 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 884 | if (!CONFIG(VGA_ROM_RUN)) |
Aaron Durbin | fbed9a5 | 2018-01-30 09:58:51 -0700 | [diff] [blame] | 885 | return; |
| 886 | |
Vladimir Serbinenko | b32816e | 2013-12-20 17:47:19 +0100 | [diff] [blame] | 887 | /* Only execute VGA ROMs. */ |
| 888 | if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) |
Myles Watson | 17aeeca | 2009-10-07 18:41:08 +0000 | [diff] [blame] | 889 | return; |
Roman Kononov | 778a42b | 2007-04-06 18:34:39 +0000 | [diff] [blame] | 890 | |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 891 | if (!should_load_oprom(dev)) |
Stefan Reinauer | 74a0efe | 2012-03-30 17:10:49 -0700 | [diff] [blame] | 892 | return; |
Martin Roth | 5dd4a2a | 2018-03-06 16:10:45 -0700 | [diff] [blame] | 893 | timestamp_add_now(TS_OPROM_INITIALIZE); |
Aaron Durbin | ce872cb | 2013-03-28 15:59:19 -0500 | [diff] [blame] | 894 | |
| 895 | rom = pci_rom_probe(dev); |
| 896 | if (rom == NULL) |
| 897 | return; |
| 898 | |
| 899 | ram = pci_rom_load(dev, rom); |
| 900 | if (ram == NULL) |
| 901 | return; |
Martin Roth | 5dd4a2a | 2018-03-06 16:10:45 -0700 | [diff] [blame] | 902 | timestamp_add_now(TS_OPROM_COPY_END); |
Aaron Durbin | ce872cb | 2013-03-28 15:59:19 -0500 | [diff] [blame] | 903 | |
Frans Hendriks | b71181a | 2019-10-04 14:06:33 +0200 | [diff] [blame] | 904 | if (!should_run_oprom(dev, rom)) |
Kyösti Mälkki | 580e564 | 2014-05-01 16:31:34 +0300 | [diff] [blame] | 905 | return; |
| 906 | |
Kyösti Mälkki | 0f30063 | 2020-12-19 23:43:56 +0200 | [diff] [blame] | 907 | /* Wait for any configured pre-graphics delay */ |
| 908 | oprom_pre_graphics_stall(); |
| 909 | |
Stefan Reinauer | d98cf5b | 2008-08-01 11:25:41 +0000 | [diff] [blame] | 910 | run_bios(dev, (unsigned long)ram); |
Johanna Schander | db7a3ae | 2019-07-24 10:14:26 +0200 | [diff] [blame] | 911 | |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 912 | gfx_set_init_done(1); |
| 913 | printk(BIOS_DEBUG, "VGA Option ROM was run\n"); |
Martin Roth | 5dd4a2a | 2018-03-06 16:10:45 -0700 | [diff] [blame] | 914 | timestamp_add_now(TS_OPROM_END); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 915 | } |
Li-Ta Lo | 883b879 | 2005-01-10 23:16:22 +0000 | [diff] [blame] | 916 | |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 917 | /** Default device operation for PCI devices */ |
Subrata Banik | ffc790b | 2017-12-11 10:29:49 +0530 | [diff] [blame] | 918 | struct pci_operations pci_dev_ops_pci = { |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 919 | .set_subsystem = pci_dev_set_subsystem, |
| 920 | }; |
| 921 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 922 | struct device_operations default_pci_ops_dev = { |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 923 | .read_resources = pci_dev_read_resources, |
| 924 | .set_resources = pci_dev_set_resources, |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 925 | .enable_resources = pci_dev_enable_resources, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 926 | #if CONFIG(HAVE_ACPI_TABLES) |
Patrick Rudolph | a5c2ac6 | 2016-03-31 20:04:23 +0200 | [diff] [blame] | 927 | .write_acpi_tables = pci_rom_write_acpi_tables, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 928 | .acpi_fill_ssdt = pci_rom_ssdt, |
Patrick Rudolph | a5c2ac6 | 2016-03-31 20:04:23 +0200 | [diff] [blame] | 929 | #endif |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 930 | .init = pci_dev_init, |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 931 | .ops_pci = &pci_dev_ops_pci, |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 932 | }; |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 933 | |
| 934 | /** Default device operations for PCI bridges */ |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 935 | struct device_operations default_pci_ops_bus = { |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 936 | .read_resources = pci_bus_read_resources, |
| 937 | .set_resources = pci_dev_set_resources, |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 938 | .enable_resources = pci_bus_enable_resources, |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 939 | .scan_bus = pci_scan_bridge, |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 940 | .reset_bus = pci_bus_reset, |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 941 | }; |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 942 | |
Tim Wawrzynczak | dbcf7b1 | 2020-05-13 16:15:08 -0600 | [diff] [blame] | 943 | /** Default device operations for PCI devices marked 'hidden' */ |
| 944 | static struct device_operations default_hidden_pci_ops_dev = { |
| 945 | .read_resources = noop_read_resources, |
| 946 | .set_resources = noop_set_resources, |
| 947 | .scan_bus = scan_static_bus, |
| 948 | }; |
| 949 | |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 950 | /** |
Nico Huber | 061b905 | 2019-09-21 15:58:23 +0200 | [diff] [blame] | 951 | * Check for compatibility to route legacy VGA cycles through a bridge. |
| 952 | * |
| 953 | * Originally, when decoding i/o ports for legacy VGA cycles, bridges |
| 954 | * should only consider the 10 least significant bits of the port address. |
| 955 | * This means all VGA registers were aliased every 1024 ports! |
| 956 | * e.g. 0x3b0 was also decoded as 0x7b0, 0xbb0 etc. |
| 957 | * |
| 958 | * To avoid this mess, a bridge control bit (VGA16) was introduced in |
| 959 | * 2003 to enable decoding of 16-bit port addresses. As we don't want |
| 960 | * to make this any more complex for now, we use this bit if possible |
| 961 | * and only warn if it's not supported (in set_vga_bridge_bits()). |
| 962 | */ |
| 963 | static void pci_bridge_vga_compat(struct bus *const bus) |
| 964 | { |
| 965 | uint16_t bridge_ctrl; |
| 966 | |
| 967 | bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); |
| 968 | |
| 969 | /* Ensure VGA decoding is disabled during probing (it should |
| 970 | be by default, but we run blobs nowadays) */ |
| 971 | bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA; |
| 972 | pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); |
| 973 | |
| 974 | /* If the upstream bridge doesn't support VGA16, we don't have to check */ |
| 975 | bus->no_vga16 |= bus->dev->bus->no_vga16; |
| 976 | if (bus->no_vga16) |
| 977 | return; |
| 978 | |
| 979 | /* Test if we can enable 16-bit decoding */ |
| 980 | bridge_ctrl |= PCI_BRIDGE_CTL_VGA16; |
| 981 | pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); |
| 982 | bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); |
| 983 | |
| 984 | bus->no_vga16 = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16); |
| 985 | } |
| 986 | |
| 987 | /** |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 988 | * Detect the type of downstream bridge. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 989 | * |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 990 | * This function is a heuristic to detect which type of bus is downstream |
| 991 | * of a PCI-to-PCI bridge. This functions by looking for various capability |
| 992 | * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and |
| 993 | * Hypertransport all seem to have appropriate capabilities. |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 994 | * |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 995 | * When only a PCI-Express capability is found the type is examined to see |
| 996 | * which type of bridge we have. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 997 | * |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 998 | * @param dev Pointer to the device structure of the bridge. |
| 999 | * @return Appropriate bridge operations. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1000 | */ |
Aaron Durbin | c30d913 | 2017-08-07 16:55:43 -0600 | [diff] [blame] | 1001 | static struct device_operations *get_pci_bridge_ops(struct device *dev) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1002 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1003 | #if CONFIG(PCIX_PLUGIN_SUPPORT) |
Ronald G. Minnich | 78a1667 | 2012-11-29 16:28:21 -0800 | [diff] [blame] | 1004 | unsigned int pcixpos; |
| 1005 | pcixpos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
| 1006 | if (pcixpos) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1007 | printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev)); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1008 | return &default_pcix_ops_bus; |
| 1009 | } |
| 1010 | #endif |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1011 | #if CONFIG(PCIEXP_PLUGIN_SUPPORT) |
Ronald G. Minnich | 78a1667 | 2012-11-29 16:28:21 -0800 | [diff] [blame] | 1012 | unsigned int pciexpos; |
| 1013 | pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 1014 | if (pciexpos) { |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1015 | u16 flags; |
Ronald G. Minnich | 78a1667 | 2012-11-29 16:28:21 -0800 | [diff] [blame] | 1016 | flags = pci_read_config16(dev, pciexpos + PCI_EXP_FLAGS); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1017 | switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1018 | case PCI_EXP_TYPE_ROOT_PORT: |
| 1019 | case PCI_EXP_TYPE_UPSTREAM: |
| 1020 | case PCI_EXP_TYPE_DOWNSTREAM: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1021 | printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n", |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1022 | dev_path(dev)); |
Arthur Heymans | 24837e7 | 2021-03-11 20:34:05 +0100 | [diff] [blame] | 1023 | if (CONFIG(PCIEXP_HOTPLUG)) { |
| 1024 | u16 sltcap; |
| 1025 | sltcap = pci_read_config16(dev, pciexpos + PCI_EXP_SLTCAP); |
| 1026 | if (sltcap & PCI_EXP_SLTCAP_HPC) { |
| 1027 | printk(BIOS_DEBUG, "%s hot-plug capable\n", |
| 1028 | dev_path(dev)); |
| 1029 | return &default_pciexp_hotplug_ops_bus; |
| 1030 | } |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 1031 | } |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1032 | return &default_pciexp_ops_bus; |
| 1033 | case PCI_EXP_TYPE_PCI_BRIDGE: |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1034 | printk(BIOS_DEBUG, "%s subordinate PCI\n", |
| 1035 | dev_path(dev)); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1036 | return &default_pci_ops_bus; |
| 1037 | default: |
| 1038 | break; |
| 1039 | } |
| 1040 | } |
| 1041 | #endif |
| 1042 | return &default_pci_ops_bus; |
| 1043 | } |
| 1044 | |
| 1045 | /** |
Vadim Bendebury | 8049fc9 | 2012-04-24 12:53:19 -0700 | [diff] [blame] | 1046 | * Check if a device id matches a PCI driver entry. |
| 1047 | * |
| 1048 | * The driver entry can either point at a zero terminated array of acceptable |
| 1049 | * device IDs, or include a single device ID. |
| 1050 | * |
Martin Roth | 98b698c | 2015-01-06 21:02:52 -0700 | [diff] [blame] | 1051 | * @param driver pointer to the PCI driver entry being checked |
| 1052 | * @param device_id PCI device ID of the device being matched |
Vadim Bendebury | 8049fc9 | 2012-04-24 12:53:19 -0700 | [diff] [blame] | 1053 | */ |
| 1054 | static int device_id_match(struct pci_driver *driver, unsigned short device_id) |
| 1055 | { |
| 1056 | if (driver->devices) { |
| 1057 | unsigned short check_id; |
| 1058 | const unsigned short *device_list = driver->devices; |
| 1059 | while ((check_id = *device_list++) != 0) |
| 1060 | if (check_id == device_id) |
| 1061 | return 1; |
| 1062 | } |
| 1063 | |
| 1064 | return (driver->device == device_id); |
| 1065 | } |
| 1066 | |
| 1067 | /** |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1068 | * Set up PCI device operation. |
| 1069 | * |
| 1070 | * Check if it already has a driver. If not, use find_device_operations(), |
| 1071 | * or set to a default based on type. |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1072 | * |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1073 | * @param dev Pointer to the device whose pci_ops you want to set. |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1074 | * @see pci_drivers |
| 1075 | */ |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1076 | static void set_pci_ops(struct device *dev) |
| 1077 | { |
| 1078 | struct pci_driver *driver; |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1079 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1080 | if (dev->ops) |
| 1081 | return; |
| 1082 | |
| 1083 | /* |
| 1084 | * Look through the list of setup drivers and find one for |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1085 | * this PCI device. |
Eric Biederman | b78c197 | 2004-10-14 20:54:17 +0000 | [diff] [blame] | 1086 | */ |
Aaron Durbin | 0375815 | 2015-09-03 17:23:08 -0500 | [diff] [blame] | 1087 | for (driver = &_pci_drivers[0]; driver != &_epci_drivers[0]; driver++) { |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1088 | if ((driver->vendor == dev->vendor) && |
Vadim Bendebury | 8049fc9 | 2012-04-24 12:53:19 -0700 | [diff] [blame] | 1089 | device_id_match(driver, dev->device)) { |
Uwe Hermann | 312673c | 2009-10-27 21:49:33 +0000 | [diff] [blame] | 1090 | dev->ops = (struct device_operations *)driver->ops; |
Nico Huber | 7e3e1ea | 2020-10-12 16:25:40 +0200 | [diff] [blame] | 1091 | break; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1092 | } |
| 1093 | } |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1094 | |
Nico Huber | 7e3e1ea | 2020-10-12 16:25:40 +0200 | [diff] [blame] | 1095 | if (dev->ops) { |
| 1096 | printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", dev_path(dev), |
| 1097 | driver->vendor, driver->device, (driver->ops->scan_bus ? "bus " : "")); |
| 1098 | return; |
| 1099 | } |
| 1100 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1101 | /* If I don't have a specific driver use the default operations. */ |
| 1102 | switch (dev->hdr_type & 0x7f) { /* Header type */ |
| 1103 | case PCI_HEADER_TYPE_NORMAL: |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1104 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) |
| 1105 | goto bad; |
| 1106 | dev->ops = &default_pci_ops_dev; |
| 1107 | break; |
| 1108 | case PCI_HEADER_TYPE_BRIDGE: |
| 1109 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
| 1110 | goto bad; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1111 | dev->ops = get_pci_bridge_ops(dev); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1112 | break; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1113 | #if CONFIG(CARDBUS_PLUGIN_SUPPORT) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1114 | case PCI_HEADER_TYPE_CARDBUS: |
| 1115 | dev->ops = &default_cardbus_ops_bus; |
| 1116 | break; |
| 1117 | #endif |
Felix Singer | c96ee7e | 2021-01-07 06:14:27 +0000 | [diff] [blame] | 1118 | default: |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1119 | bad: |
Li-Ta Lo | 69c5a90 | 2004-04-29 20:08:54 +0000 | [diff] [blame] | 1120 | if (dev->enabled) { |
Angel Pons | d19cc11 | 2021-07-04 11:41:31 +0200 | [diff] [blame] | 1121 | printk(BIOS_ERR, |
| 1122 | "%s [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n", |
| 1123 | dev_path(dev), dev->vendor, dev->device, |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1124 | dev->class >> 8, dev->hdr_type); |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 1125 | } |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1126 | } |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1127 | } |
| 1128 | |
| 1129 | /** |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1130 | * See if we have already allocated a device structure for a given devfn. |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1131 | * |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1132 | * Given a PCI bus structure and a devfn number, find the device structure |
| 1133 | * corresponding to the devfn, if present. Then move the device structure |
| 1134 | * as the last child on the bus. |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1135 | * |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1136 | * @param bus Pointer to the bus structure. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1137 | * @param devfn A device/function number. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1138 | * @return Pointer to the device structure found or NULL if we have not |
Li-Ta Lo | 3a81285 | 2004-12-03 22:39:34 +0000 | [diff] [blame] | 1139 | * allocated a device for this devfn yet. |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1140 | */ |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1141 | static struct device *pci_scan_get_dev(struct bus *bus, unsigned int devfn) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1142 | { |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1143 | struct device *dev, **prev; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1144 | |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1145 | prev = &bus->children; |
| 1146 | for (dev = bus->children; dev; dev = dev->sibling) { |
Duncan Laurie | bf69622 | 2020-10-18 15:10:00 -0700 | [diff] [blame] | 1147 | if (dev->path.type == DEVICE_PATH_PCI && dev->path.pci.devfn == devfn) { |
| 1148 | /* Unlink from the list. */ |
| 1149 | *prev = dev->sibling; |
| 1150 | dev->sibling = NULL; |
| 1151 | break; |
Eric Biederman | ad1b35a | 2003-10-14 02:36:51 +0000 | [diff] [blame] | 1152 | } |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1153 | prev = &dev->sibling; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1154 | } |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1155 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1156 | /* |
| 1157 | * Just like alloc_dev() add the device to the list of devices on the |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1158 | * bus. When the list of devices was formed we removed all of the |
| 1159 | * parents children, and now we are interleaving static and dynamic |
| 1160 | * devices in order on the bus. |
Eric Biederman | b78c197 | 2004-10-14 20:54:17 +0000 | [diff] [blame] | 1161 | */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 1162 | if (dev) { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1163 | struct device *child; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1164 | |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1165 | /* Find the last child on the bus. */ |
| 1166 | for (child = bus->children; child && child->sibling;) |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 1167 | child = child->sibling; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1168 | |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1169 | /* Place the device as last on the bus. */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1170 | if (child) |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 1171 | child->sibling = dev; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1172 | else |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1173 | bus->children = dev; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 1174 | } |
| 1175 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1176 | return dev; |
| 1177 | } |
| 1178 | |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1179 | /** |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1180 | * Scan a PCI bus. |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1181 | * |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1182 | * Determine the existence of a given PCI device. Allocate a new struct device |
| 1183 | * if dev==NULL was passed in and the device exists in hardware. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1184 | * |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1185 | * @param dev Pointer to the dev structure. |
| 1186 | * @param bus Pointer to the bus structure. |
| 1187 | * @param devfn A device/function number to look at. |
| 1188 | * @return The device structure for the device (if found), NULL otherwise. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1189 | */ |
Aaron Durbin | c30d913 | 2017-08-07 16:55:43 -0600 | [diff] [blame] | 1190 | struct device *pci_probe_dev(struct device *dev, struct bus *bus, |
| 1191 | unsigned int devfn) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1192 | { |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1193 | u32 id, class; |
| 1194 | u8 hdr_type; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1195 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1196 | /* Detect if a device is present. */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1197 | if (!dev) { |
| 1198 | struct device dummy; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1199 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1200 | dummy.bus = bus; |
| 1201 | dummy.path.type = DEVICE_PATH_PCI; |
Stefan Reinauer | 2b34db8 | 2009-02-28 20:10:20 +0000 | [diff] [blame] | 1202 | dummy.path.pci.devfn = devfn; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1203 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1204 | id = pci_read_config32(&dummy, PCI_VENDOR_ID); |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1205 | /* |
| 1206 | * Have we found something? Some broken boards return 0 if a |
| 1207 | * slot is empty, but the expected answer is 0xffffffff. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1208 | */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1209 | if (id == 0xffffffff) |
Stefan Reinauer | 7355c75 | 2010-04-02 16:30:25 +0000 | [diff] [blame] | 1210 | return NULL; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1211 | |
Stefan Reinauer | 7355c75 | 2010-04-02 16:30:25 +0000 | [diff] [blame] | 1212 | if ((id == 0x00000000) || (id == 0x0000ffff) || |
| 1213 | (id == 0xffff0000)) { |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1214 | printk(BIOS_SPEW, "%s, bad id 0x%x\n", |
| 1215 | dev_path(&dummy), id); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1216 | return NULL; |
| 1217 | } |
| 1218 | dev = alloc_dev(bus, &dummy.path); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1219 | } else { |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1220 | /* |
| 1221 | * Enable/disable the device. Once we have found the device- |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1222 | * specific operations this operations we will disable the |
| 1223 | * device with those as well. |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1224 | * |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1225 | * This is geared toward devices that have subfunctions |
| 1226 | * that do not show up by default. |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1227 | * |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1228 | * If a device is a stuff option on the motherboard |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1229 | * it may be absent and enable_dev() must cope. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1230 | */ |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1231 | /* Run the magic enable sequence for the device. */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1232 | if (dev->chip_ops && dev->chip_ops->enable_dev) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1233 | dev->chip_ops->enable_dev(dev); |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1234 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1235 | /* Now read the vendor and device ID. */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1236 | id = pci_read_config32(dev, PCI_VENDOR_ID); |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1237 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1238 | /* |
| 1239 | * If the device does not have a PCI ID disable it. Possibly |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1240 | * this is because we have already disabled the device. But |
| 1241 | * this also handles optional devices that may not always |
| 1242 | * show up. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1243 | */ |
| 1244 | /* If the chain is fully enumerated quit */ |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1245 | if ((id == 0xffffffff) || (id == 0x00000000) || |
| 1246 | (id == 0x0000ffff) || (id == 0xffff0000)) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1247 | if (dev->enabled) { |
Angel Pons | d19cc11 | 2021-07-04 11:41:31 +0200 | [diff] [blame] | 1248 | printk(BIOS_INFO, |
| 1249 | "PCI: Static device %s not found, disabling it.\n", |
| 1250 | dev_path(dev)); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1251 | dev->enabled = 0; |
| 1252 | } |
| 1253 | return dev; |
| 1254 | } |
| 1255 | } |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1256 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1257 | /* Read the rest of the PCI configuration information. */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1258 | hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 1259 | class = pci_read_config32(dev, PCI_CLASS_REVISION); |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1260 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1261 | /* Store the interesting information in the device structure. */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1262 | dev->vendor = id & 0xffff; |
| 1263 | dev->device = (id >> 16) & 0xffff; |
| 1264 | dev->hdr_type = hdr_type; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1265 | |
| 1266 | /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1267 | dev->class = class >> 8; |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1268 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1269 | /* Architectural/System devices always need to be bus masters. */ |
Felix Singer | d3d0fd7 | 2020-09-07 16:15:14 +0200 | [diff] [blame] | 1270 | if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM && |
| 1271 | CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE)) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1272 | dev->command |= PCI_COMMAND_MASTER; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1273 | |
| 1274 | /* |
| 1275 | * Look at the vendor and device ID, or at least the header type and |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1276 | * class and figure out which set of configuration methods to use. |
| 1277 | * Unless we already have some PCI ops. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1278 | */ |
| 1279 | set_pci_ops(dev); |
| 1280 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1281 | /* Now run the magic enable/disable sequence for the device. */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1282 | if (dev->ops && dev->ops->enable) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1283 | dev->ops->enable(dev); |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1284 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1285 | /* Display the device. */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1286 | printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n", dev_path(dev), |
| 1287 | dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled", |
| 1288 | dev->ops ? "" : " No operations"); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1289 | |
| 1290 | return dev; |
| 1291 | } |
| 1292 | |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1293 | /** |
Kyösti Mälkki | c73acdb | 2013-06-15 17:16:56 +0300 | [diff] [blame] | 1294 | * Test for match between romstage and ramstage device instance. |
| 1295 | * |
| 1296 | * @param dev Pointer to the device structure. |
| 1297 | * @param sdev Simple device model identifier, created with PCI_DEV(). |
| 1298 | * @return Non-zero if bus:dev.fn of device matches. |
| 1299 | */ |
Aaron Durbin | c30d913 | 2017-08-07 16:55:43 -0600 | [diff] [blame] | 1300 | unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev) |
Kyösti Mälkki | c73acdb | 2013-06-15 17:16:56 +0300 | [diff] [blame] | 1301 | { |
| 1302 | return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && |
| 1303 | dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); |
| 1304 | } |
| 1305 | |
| 1306 | /** |
Bill XIE | 513d359 | 2022-08-02 22:55:51 +0800 | [diff] [blame] | 1307 | * Test whether a capability is available along the whole path from the given |
| 1308 | * device to the host bridge. |
| 1309 | * |
| 1310 | * @param dev Pointer to the device structure. |
| 1311 | * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for. |
| 1312 | * @return The next matching capability of the given device, if it is available |
| 1313 | * along the whole path, or zero if not. |
| 1314 | */ |
| 1315 | uint16_t pci_find_cap_recursive(const struct device *dev, uint16_t cap) |
| 1316 | { |
| 1317 | assert(dev->bus); |
| 1318 | uint16_t pos = pci_find_capability(dev, cap); |
| 1319 | const struct device *bridge = dev->bus->dev; |
| 1320 | while (bridge && (bridge->path.type == DEVICE_PATH_PCI)) { |
| 1321 | assert(bridge->bus); |
| 1322 | if (!pci_find_capability(bridge, cap)) |
| 1323 | return 0; |
| 1324 | bridge = bridge->bus->dev; |
| 1325 | } |
| 1326 | return pos; |
| 1327 | } |
| 1328 | |
| 1329 | /** |
Tim Wawrzynczak | dbcf7b1 | 2020-05-13 16:15:08 -0600 | [diff] [blame] | 1330 | * PCI devices that are marked as "hidden" do not get probed. However, the same |
| 1331 | * initialization logic is still performed as if it were. This is useful when |
| 1332 | * devices would like to be described in the devicetree.cb file, and/or present |
| 1333 | * static PCI resources to the allocator, but the platform firmware hides the |
| 1334 | * device (makes the device invisible to PCI enumeration) before PCI enumeration |
| 1335 | * takes place. |
| 1336 | * |
| 1337 | * The expected semantics of PCI devices marked as 'hidden': |
| 1338 | * 1) The device is actually present under the specified BDF |
| 1339 | * 2) The device config space can still be accessed somehow, but the Vendor ID |
| 1340 | * indicates there is no device there (it reads as 0xffffffff). |
| 1341 | * 3) The device may still consume PCI resources. Typically, these would have |
| 1342 | * been hardcoded elsewhere. |
| 1343 | * |
| 1344 | * @param dev Pointer to the device structure. |
| 1345 | */ |
| 1346 | static void pci_scan_hidden_device(struct device *dev) |
| 1347 | { |
| 1348 | if (dev->chip_ops && dev->chip_ops->enable_dev) |
| 1349 | dev->chip_ops->enable_dev(dev); |
| 1350 | |
| 1351 | /* |
| 1352 | * If chip_ops->enable_dev did not set dev->ops, then set to a default |
| 1353 | * .ops, because PCI enumeration is effectively being skipped, therefore |
| 1354 | * no PCI driver will bind to this device. However, children may want to |
| 1355 | * be enumerated, so this provides scan_static_bus for the .scan_bus |
| 1356 | * callback. |
| 1357 | */ |
| 1358 | if (dev->ops == NULL) |
| 1359 | dev->ops = &default_hidden_pci_ops_dev; |
| 1360 | |
| 1361 | if (dev->ops->enable) |
| 1362 | dev->ops->enable(dev); |
| 1363 | |
| 1364 | /* Display the device almost as if it were probed normally */ |
| 1365 | printk(BIOS_DEBUG, "%s [0000/%04x] hidden%s\n", dev_path(dev), |
| 1366 | dev->device, dev->ops ? "" : " No operations"); |
| 1367 | } |
| 1368 | |
| 1369 | /** |
Jianjun Wang | 777ffff | 2021-07-24 14:50:36 +0800 | [diff] [blame] | 1370 | * A PCIe Downstream Port normally leads to a Link with only Device 0 on it |
| 1371 | * (PCIe spec r5.0, sec 7.3.1). As an optimization, scan only for Device 0 in |
| 1372 | * that situation. |
| 1373 | * |
| 1374 | * @param bus Pointer to the bus structure. |
| 1375 | */ |
| 1376 | static bool pci_bus_only_one_child(struct bus *bus) |
| 1377 | { |
| 1378 | struct device *bridge = bus->dev; |
| 1379 | u16 pcie_pos, pcie_flags_reg; |
| 1380 | int pcie_type; |
| 1381 | |
Arthur Heymans | db199cc | 2022-01-06 20:56:01 +0100 | [diff] [blame] | 1382 | if (!bridge) |
| 1383 | return false; |
| 1384 | |
Nico Huber | f514b8a | 2022-02-25 14:25:57 +0100 | [diff] [blame] | 1385 | if (bridge->path.type != DEVICE_PATH_PCI) |
| 1386 | return false; |
| 1387 | |
Jianjun Wang | 777ffff | 2021-07-24 14:50:36 +0800 | [diff] [blame] | 1388 | pcie_pos = pci_find_capability(bridge, PCI_CAP_ID_PCIE); |
| 1389 | if (!pcie_pos) |
| 1390 | return false; |
| 1391 | |
| 1392 | pcie_flags_reg = pci_read_config16(bridge, pcie_pos + PCI_EXP_FLAGS); |
| 1393 | |
| 1394 | pcie_type = (pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; |
| 1395 | |
| 1396 | return pciexp_is_downstream_port(pcie_type); |
| 1397 | } |
| 1398 | |
| 1399 | /** |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1400 | * Scan a PCI bus. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1401 | * |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1402 | * Determine the existence of devices and bridges on a PCI bus. If there are |
| 1403 | * bridges on the bus, recursively scan the buses behind the bridges. |
| 1404 | * |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1405 | * @param bus Pointer to the bus structure. |
| 1406 | * @param min_devfn Minimum devfn to look at in the scan, usually 0x00. |
| 1407 | * @param max_devfn Maximum devfn to look at in the scan, usually 0xff. |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1408 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 1409 | void pci_scan_bus(struct bus *bus, unsigned int min_devfn, |
| 1410 | unsigned int max_devfn) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1411 | { |
| 1412 | unsigned int devfn; |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1413 | struct device *dev, **prev; |
| 1414 | int once = 0; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1415 | |
Elyes HAOUAS | f984aec | 2021-01-16 17:29:17 +0100 | [diff] [blame] | 1416 | printk(BIOS_DEBUG, "PCI: %s for bus %02x\n", __func__, bus->secondary); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1417 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1418 | /* Maximum sane devfn is 0xFF. */ |
Juhana Helovuo | 50b78b6 | 2010-09-13 14:43:02 +0000 | [diff] [blame] | 1419 | if (max_devfn > 0xff) { |
Elyes HAOUAS | f984aec | 2021-01-16 17:29:17 +0100 | [diff] [blame] | 1420 | printk(BIOS_ERR, "PCI: %s limits devfn %x - devfn %x\n", |
| 1421 | __func__, min_devfn, max_devfn); |
| 1422 | printk(BIOS_ERR, "PCI: %s upper limit too big. Using 0xff.\n", __func__); |
Juhana Helovuo | 50b78b6 | 2010-09-13 14:43:02 +0000 | [diff] [blame] | 1423 | max_devfn=0xff; |
| 1424 | } |
| 1425 | |
Martin Roth | 9a8667a | 2022-11-03 18:40:10 -0600 | [diff] [blame] | 1426 | post_code(POST_ENTER_PCI_SCAN_BUS); |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1427 | |
Jianjun Wang | 777ffff | 2021-07-24 14:50:36 +0800 | [diff] [blame] | 1428 | if (pci_bus_only_one_child(bus)) |
| 1429 | max_devfn = MIN(max_devfn, 0x07); |
| 1430 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1431 | /* |
| 1432 | * Probe all devices/functions on this bus with some optimization for |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1433 | * non-existence and single function devices. |
Eric Biederman | b78c197 | 2004-10-14 20:54:17 +0000 | [diff] [blame] | 1434 | */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 1435 | for (devfn = min_devfn; devfn <= max_devfn; devfn++) { |
Ronald G. Minnich | 466ca2c | 2019-10-22 02:02:24 +0000 | [diff] [blame] | 1436 | if (CONFIG(MINIMAL_PCI_SCANNING)) { |
| 1437 | dev = pcidev_path_behind(bus, devfn); |
| 1438 | if (!dev || !dev->mandatory) |
| 1439 | continue; |
| 1440 | } |
| 1441 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1442 | /* First thing setup the device structure. */ |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1443 | dev = pci_scan_get_dev(bus, devfn); |
Li-Ta Lo | 9782f75 | 2004-05-05 21:15:42 +0000 | [diff] [blame] | 1444 | |
Tim Wawrzynczak | dbcf7b1 | 2020-05-13 16:15:08 -0600 | [diff] [blame] | 1445 | /* Devices marked 'hidden' do not get probed */ |
| 1446 | if (dev && dev->hidden) { |
| 1447 | pci_scan_hidden_device(dev); |
| 1448 | |
| 1449 | /* Skip pci_probe_dev, go to next devfn */ |
| 1450 | continue; |
| 1451 | } |
| 1452 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1453 | /* See if a device is present and setup the device structure. */ |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1454 | dev = pci_probe_dev(dev, bus, devfn); |
Eric Biederman | 03acab6 | 2004-10-14 21:25:53 +0000 | [diff] [blame] | 1455 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1456 | /* |
| 1457 | * If this is not a multi function device, or the device is |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1458 | * not present don't waste time probing another function. |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 1459 | * Skip to next device. |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1460 | */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1461 | if ((PCI_FUNC(devfn) == 0x00) && (!dev |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1462 | || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) { |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1463 | devfn += 0x07; |
| 1464 | } |
| 1465 | } |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1466 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1467 | /* |
Elyes HAOUAS | 0ce7416 | 2021-01-16 14:43:49 +0100 | [diff] [blame] | 1468 | * Warn if any leftover static devices are found. |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1469 | * There's probably a problem in devicetree.cb. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1470 | */ |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1471 | |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1472 | prev = &bus->children; |
| 1473 | for (dev = bus->children; dev; dev = dev->sibling) { |
Duncan Laurie | bf69622 | 2020-10-18 15:10:00 -0700 | [diff] [blame] | 1474 | |
| 1475 | /* |
| 1476 | * If static device is not PCI then enable it here and don't |
| 1477 | * treat it as a leftover device. |
| 1478 | */ |
| 1479 | if (dev->path.type != DEVICE_PATH_PCI) { |
| 1480 | enable_static_device(dev); |
| 1481 | continue; |
| 1482 | } |
| 1483 | |
Tim Wawrzynczak | dbcf7b1 | 2020-05-13 16:15:08 -0600 | [diff] [blame] | 1484 | /* |
| 1485 | * The device is only considered leftover if it is not hidden |
| 1486 | * and it has a Vendor ID of 0 (the default for a device that |
| 1487 | * could not be probed). |
| 1488 | */ |
| 1489 | if (dev->vendor != 0 || dev->hidden) { |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1490 | prev = &dev->sibling; |
| 1491 | continue; |
| 1492 | } |
| 1493 | |
| 1494 | /* Unlink it from list. */ |
| 1495 | *prev = dev->sibling; |
| 1496 | |
| 1497 | if (!once++) |
| 1498 | printk(BIOS_WARNING, "PCI: Leftover static devices:\n"); |
| 1499 | printk(BIOS_WARNING, "%s\n", dev_path(dev)); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1500 | } |
| 1501 | |
Kyösti Mälkki | 8712aa1 | 2019-01-09 11:31:25 +0200 | [diff] [blame] | 1502 | if (once) |
| 1503 | printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n"); |
| 1504 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1505 | /* |
| 1506 | * For all children that implement scan_bus() (i.e. bridges) |
Eric Biederman | b78c197 | 2004-10-14 20:54:17 +0000 | [diff] [blame] | 1507 | * scan the bus behind that child. |
| 1508 | */ |
Kyösti Mälkki | de271a8 | 2015-03-18 13:09:47 +0200 | [diff] [blame] | 1509 | |
Kyösti Mälkki | 2d2367c | 2015-02-20 21:28:31 +0200 | [diff] [blame] | 1510 | scan_bridges(bus); |
Kyösti Mälkki | de271a8 | 2015-03-18 13:09:47 +0200 | [diff] [blame] | 1511 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1512 | /* |
| 1513 | * We've scanned the bus and so we know all about what's on the other |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1514 | * side of any bridges that may be on this bus plus any devices. |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1515 | * Return how far we've got finding sub-buses. |
| 1516 | */ |
Martin Roth | 9a8667a | 2022-11-03 18:40:10 -0600 | [diff] [blame] | 1517 | post_code(POST_EXIT_PCI_SCAN_BUS); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1518 | } |
| 1519 | |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1520 | typedef enum { |
| 1521 | PCI_ROUTE_CLOSE, |
| 1522 | PCI_ROUTE_SCAN, |
| 1523 | PCI_ROUTE_FINAL, |
| 1524 | } scan_state; |
| 1525 | |
| 1526 | static void pci_bridge_route(struct bus *link, scan_state state) |
| 1527 | { |
| 1528 | struct device *dev = link->dev; |
| 1529 | struct bus *parent = dev->bus; |
Arthur Heymans | f879d36 | 2021-11-10 22:09:58 +0100 | [diff] [blame] | 1530 | uint8_t primary, secondary, subordinate; |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1531 | |
Kyösti Mälkki | 757c8b4 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1532 | if (state == PCI_ROUTE_SCAN) { |
| 1533 | link->secondary = parent->subordinate + 1; |
Jeremy Soller | cf2ac54 | 2019-10-09 21:40:36 -0600 | [diff] [blame] | 1534 | link->subordinate = link->secondary + dev->hotplug_buses; |
Arthur Heymans | 20d2577 | 2021-11-17 17:25:48 +0100 | [diff] [blame] | 1535 | link->max_subordinate = parent->max_subordinate |
| 1536 | ? parent->max_subordinate |
| 1537 | : (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); |
| 1538 | } |
| 1539 | |
| 1540 | if (link->secondary > link->max_subordinate) |
| 1541 | die("%s: No more busses available!\n", __func__); |
| 1542 | |
| 1543 | /* This ought to only happen with hotplug buses. */ |
| 1544 | if (link->subordinate > link->max_subordinate) { |
| 1545 | printk(BIOS_WARNING, "%s: Limiting subordinate busses\n", __func__); |
| 1546 | link->subordinate = link->max_subordinate; |
Kyösti Mälkki | 757c8b4 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1547 | } |
| 1548 | |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1549 | if (state == PCI_ROUTE_CLOSE) { |
Arthur Heymans | f879d36 | 2021-11-10 22:09:58 +0100 | [diff] [blame] | 1550 | primary = 0; |
| 1551 | secondary = 0xff; |
| 1552 | subordinate = 0xfe; |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1553 | } else if (state == PCI_ROUTE_SCAN) { |
Arthur Heymans | f879d36 | 2021-11-10 22:09:58 +0100 | [diff] [blame] | 1554 | primary = parent->secondary; |
| 1555 | secondary = link->secondary; |
Arthur Heymans | 20d2577 | 2021-11-17 17:25:48 +0100 | [diff] [blame] | 1556 | subordinate = link->max_subordinate; |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1557 | } else if (state == PCI_ROUTE_FINAL) { |
Arthur Heymans | f879d36 | 2021-11-10 22:09:58 +0100 | [diff] [blame] | 1558 | primary = parent->secondary; |
| 1559 | secondary = link->secondary; |
| 1560 | subordinate = link->subordinate; |
Arthur Heymans | 4a3331d | 2022-03-23 17:58:46 +0100 | [diff] [blame] | 1561 | } else { |
| 1562 | return; |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1563 | } |
| 1564 | |
| 1565 | if (state == PCI_ROUTE_SCAN) { |
| 1566 | /* Clear all status bits and turn off memory, I/O and master enables. */ |
| 1567 | link->bridge_cmd = pci_read_config16(dev, PCI_COMMAND); |
| 1568 | pci_write_config16(dev, PCI_COMMAND, 0x0000); |
| 1569 | pci_write_config16(dev, PCI_STATUS, 0xffff); |
| 1570 | } |
| 1571 | |
| 1572 | /* |
| 1573 | * Configure the bus numbers for this bridge: the configuration |
| 1574 | * transactions will not be propagated by the bridge if it is not |
| 1575 | * correctly configured. |
| 1576 | */ |
Arthur Heymans | f879d36 | 2021-11-10 22:09:58 +0100 | [diff] [blame] | 1577 | pci_write_config8(dev, PCI_PRIMARY_BUS, primary); |
| 1578 | pci_write_config8(dev, PCI_SECONDARY_BUS, secondary); |
| 1579 | pci_write_config8(dev, PCI_SUBORDINATE_BUS, subordinate); |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1580 | |
| 1581 | if (state == PCI_ROUTE_FINAL) { |
| 1582 | pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd); |
Kyösti Mälkki | 757c8b4 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1583 | parent->subordinate = link->subordinate; |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1584 | } |
| 1585 | } |
| 1586 | |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1587 | /** |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1588 | * Scan a PCI bridge and the buses behind the bridge. |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1589 | * |
| 1590 | * Determine the existence of buses behind the bridge. Set up the bridge |
| 1591 | * according to the result of the scan. |
| 1592 | * |
| 1593 | * This function is the default scan_bus() method for PCI bridge devices. |
| 1594 | * |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1595 | * @param dev Pointer to the bridge device. |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1596 | * @param do_scan_bus TODO |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1597 | */ |
Kyösti Mälkki | 580e722 | 2015-03-19 21:04:23 +0200 | [diff] [blame] | 1598 | void do_pci_scan_bridge(struct device *dev, |
Kyösti Mälkki | de271a8 | 2015-03-18 13:09:47 +0200 | [diff] [blame] | 1599 | void (*do_scan_bus) (struct bus * bus, |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 1600 | unsigned int min_devfn, |
| 1601 | unsigned int max_devfn)) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1602 | { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 1603 | struct bus *bus; |
Eric Biederman | 83b991a | 2003-10-11 06:20:25 +0000 | [diff] [blame] | 1604 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1605 | printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev)); |
Li-Ta Lo | 3a81285 | 2004-12-03 22:39:34 +0000 | [diff] [blame] | 1606 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 1607 | if (dev->link_list == NULL) { |
| 1608 | struct bus *link; |
| 1609 | link = malloc(sizeof(*link)); |
| 1610 | if (link == NULL) |
| 1611 | die("Couldn't allocate a link!\n"); |
| 1612 | memset(link, 0, sizeof(*link)); |
| 1613 | link->dev = dev; |
| 1614 | dev->link_list = link; |
| 1615 | } |
| 1616 | |
| 1617 | bus = dev->link_list; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 1618 | |
Nico Huber | 061b905 | 2019-09-21 15:58:23 +0200 | [diff] [blame] | 1619 | pci_bridge_vga_compat(bus); |
| 1620 | |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1621 | pci_bridge_route(bus, PCI_ROUTE_SCAN); |
Li-Ta Lo | 3a81285 | 2004-12-03 22:39:34 +0000 | [diff] [blame] | 1622 | |
Kyösti Mälkki | de271a8 | 2015-03-18 13:09:47 +0200 | [diff] [blame] | 1623 | do_scan_bus(bus, 0x00, 0xff); |
Kyösti Mälkki | 3345240 | 2015-02-23 06:58:26 +0200 | [diff] [blame] | 1624 | |
| 1625 | pci_bridge_route(bus, PCI_ROUTE_FINAL); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1626 | } |
Li-Ta Lo | e526669 | 2004-03-23 21:28:05 +0000 | [diff] [blame] | 1627 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1628 | /** |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1629 | * Scan a PCI bridge and the buses behind the bridge. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1630 | * |
| 1631 | * Determine the existence of buses behind the bridge. Set up the bridge |
| 1632 | * according to the result of the scan. |
| 1633 | * |
| 1634 | * This function is the default scan_bus() method for PCI bridge devices. |
| 1635 | * |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1636 | * @param dev Pointer to the bridge device. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1637 | */ |
Kyösti Mälkki | 580e722 | 2015-03-19 21:04:23 +0200 | [diff] [blame] | 1638 | void pci_scan_bridge(struct device *dev) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1639 | { |
Kyösti Mälkki | 580e722 | 2015-03-19 21:04:23 +0200 | [diff] [blame] | 1640 | do_pci_scan_bridge(dev, pci_scan_bus); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 1641 | } |
| 1642 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1643 | /** |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1644 | * Scan a PCI domain. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1645 | * |
| 1646 | * This function is the default scan_bus() method for PCI domains. |
| 1647 | * |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1648 | * @param dev Pointer to the domain. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1649 | */ |
Aaron Durbin | c30d913 | 2017-08-07 16:55:43 -0600 | [diff] [blame] | 1650 | void pci_domain_scan_bus(struct device *dev) |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1651 | { |
Kyösti Mälkki | 6f37017 | 2015-03-19 15:26:52 +0200 | [diff] [blame] | 1652 | struct bus *link = dev->link_list; |
Kyösti Mälkki | de271a8 | 2015-03-18 13:09:47 +0200 | [diff] [blame] | 1653 | pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1654 | } |
| 1655 | |
Angel Pons | b651981 | 2021-12-31 13:33:50 +0100 | [diff] [blame] | 1656 | void pci_dev_disable_bus_master(const struct device *dev) |
| 1657 | { |
| 1658 | pci_update_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER, 0x0); |
| 1659 | } |
| 1660 | |
Mike Loptien | 0f5cf5e | 2014-05-12 21:46:31 -0600 | [diff] [blame] | 1661 | /** |
| 1662 | * Take an INT_PIN number (0, 1 - 4) and convert |
| 1663 | * it to a string ("NO PIN", "PIN A" - "PIN D") |
| 1664 | * |
| 1665 | * @param pin PCI Interrupt Pin number (0, 1 - 4) |
| 1666 | * @return A string corresponding to the pin number or "Invalid" |
| 1667 | */ |
| 1668 | const char *pin_to_str(int pin) |
| 1669 | { |
| 1670 | const char *str[5] = { |
| 1671 | "NO PIN", |
| 1672 | "PIN A", |
| 1673 | "PIN B", |
| 1674 | "PIN C", |
| 1675 | "PIN D", |
| 1676 | }; |
| 1677 | |
| 1678 | if (pin >= 0 && pin <= 4) |
| 1679 | return str[pin]; |
| 1680 | else |
| 1681 | return "Invalid PIN, not 0 - 4"; |
| 1682 | } |
| 1683 | |
| 1684 | /** |
| 1685 | * Get the PCI INT_PIN swizzle for a device defined as: |
| 1686 | * pin_parent = (pin_child + devn_child) % 4 + 1 |
| 1687 | * where PIN A = 1 ... PIN_D = 4 |
| 1688 | * |
| 1689 | * Given a PCI device structure 'dev', find the interrupt pin |
| 1690 | * that will be triggered on its parent bridge device when |
| 1691 | * generating an interrupt. For example: Device 1:3.2 may |
| 1692 | * use INT_PIN A but will trigger PIN D on its parent bridge |
| 1693 | * device. In this case, this function will return 4 (PIN D). |
| 1694 | * |
| 1695 | * @param dev A PCI device structure to swizzle interrupt pins for |
Martin Roth | 32bc6b6 | 2015-01-04 16:54:35 -0700 | [diff] [blame] | 1696 | * @param *parent_bridge The PCI device structure for the bridge |
Mike Loptien | 0f5cf5e | 2014-05-12 21:46:31 -0600 | [diff] [blame] | 1697 | * device 'dev' is attached to |
| 1698 | * @return The interrupt pin number (1 - 4) that 'dev' will |
| 1699 | * trigger when generating an interrupt |
| 1700 | */ |
Aaron Durbin | c30d913 | 2017-08-07 16:55:43 -0600 | [diff] [blame] | 1701 | static int swizzle_irq_pins(struct device *dev, struct device **parent_bridge) |
Mike Loptien | 0f5cf5e | 2014-05-12 21:46:31 -0600 | [diff] [blame] | 1702 | { |
Aaron Durbin | c30d913 | 2017-08-07 16:55:43 -0600 | [diff] [blame] | 1703 | struct device *parent; /* Our current device's parent device */ |
| 1704 | struct device *child; /* The child device of the parent */ |
Mike Loptien | 0f5cf5e | 2014-05-12 21:46:31 -0600 | [diff] [blame] | 1705 | uint8_t parent_bus = 0; /* Parent Bus number */ |
| 1706 | uint16_t parent_devfn = 0; /* Parent Device and Function number */ |
| 1707 | uint16_t child_devfn = 0; /* Child Device and Function number */ |
| 1708 | uint8_t swizzled_pin = 0; /* Pin swizzled across a bridge */ |
| 1709 | |
| 1710 | /* Start with PIN A = 0 ... D = 3 */ |
| 1711 | swizzled_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN) - 1; |
| 1712 | |
| 1713 | /* While our current device has parent devices */ |
| 1714 | child = dev; |
| 1715 | for (parent = child->bus->dev; parent; parent = parent->bus->dev) { |
| 1716 | parent_bus = parent->bus->secondary; |
| 1717 | parent_devfn = parent->path.pci.devfn; |
| 1718 | child_devfn = child->path.pci.devfn; |
| 1719 | |
| 1720 | /* Swizzle the INT_PIN for any bridges not on root bus */ |
| 1721 | swizzled_pin = (PCI_SLOT(child_devfn) + swizzled_pin) % 4; |
| 1722 | printk(BIOS_SPEW, "\tWith INT_PIN swizzled to %s\n" |
| 1723 | "\tAttached to bridge device %01X:%02Xh.%02Xh\n", |
| 1724 | pin_to_str(swizzled_pin + 1), parent_bus, |
| 1725 | PCI_SLOT(parent_devfn), PCI_FUNC(parent_devfn)); |
| 1726 | |
| 1727 | /* Continue until we find the root bus */ |
| 1728 | if (parent_bus > 0) { |
| 1729 | /* |
| 1730 | * We will go on to the next parent so this parent |
| 1731 | * becomes the child |
| 1732 | */ |
| 1733 | child = parent; |
| 1734 | continue; |
| 1735 | } else { |
| 1736 | /* |
| 1737 | * Found the root bridge device, |
| 1738 | * fill in the structure and exit |
| 1739 | */ |
| 1740 | *parent_bridge = parent; |
| 1741 | break; |
| 1742 | } |
| 1743 | } |
| 1744 | |
| 1745 | /* End with PIN A = 1 ... D = 4 */ |
| 1746 | return swizzled_pin + 1; |
| 1747 | } |
| 1748 | |
| 1749 | /** |
| 1750 | * Given a device structure 'dev', find its interrupt pin |
| 1751 | * and its parent bridge 'parent_bdg' device structure. |
| 1752 | * If it is behind a bridge, it will return the interrupt |
| 1753 | * pin number (1 - 4) of the parent bridge that the device |
| 1754 | * interrupt pin has been swizzled to, otherwise it will |
| 1755 | * return the interrupt pin that is programmed into the |
| 1756 | * PCI config space of the target device. If 'dev' is |
| 1757 | * behind a bridge, it will fill in 'parent_bdg' with the |
| 1758 | * device structure of the bridge it is behind, otherwise |
| 1759 | * it will copy 'dev' into 'parent_bdg'. |
| 1760 | * |
| 1761 | * @param dev A PCI device structure to get interrupt pins for. |
| 1762 | * @param *parent_bdg The PCI device structure for the bridge |
| 1763 | * device 'dev' is attached to. |
| 1764 | * @return The interrupt pin number (1 - 4) that 'dev' will |
| 1765 | * trigger when generating an interrupt. |
| 1766 | * Errors: -1 is returned if the device is not enabled |
| 1767 | * -2 is returned if a parent bridge could not be found. |
| 1768 | */ |
Aaron Durbin | c30d913 | 2017-08-07 16:55:43 -0600 | [diff] [blame] | 1769 | int get_pci_irq_pins(struct device *dev, struct device **parent_bdg) |
Mike Loptien | 0f5cf5e | 2014-05-12 21:46:31 -0600 | [diff] [blame] | 1770 | { |
| 1771 | uint8_t bus = 0; /* The bus this device is on */ |
| 1772 | uint16_t devfn = 0; /* This device's device and function numbers */ |
| 1773 | uint8_t int_pin = 0; /* Interrupt pin used by the device */ |
| 1774 | uint8_t target_pin = 0; /* Interrupt pin we want to assign an IRQ to */ |
| 1775 | |
| 1776 | /* Make sure this device is enabled */ |
| 1777 | if (!(dev->enabled && (dev->path.type == DEVICE_PATH_PCI))) |
| 1778 | return -1; |
| 1779 | |
| 1780 | bus = dev->bus->secondary; |
| 1781 | devfn = dev->path.pci.devfn; |
| 1782 | |
| 1783 | /* Get and validate the interrupt pin used. Only 1-4 are allowed */ |
| 1784 | int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
| 1785 | if (int_pin < 1 || int_pin > 4) |
| 1786 | return -1; |
| 1787 | |
| 1788 | printk(BIOS_SPEW, "PCI IRQ: Found device %01X:%02X.%02X using %s\n", |
| 1789 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pin_to_str(int_pin)); |
| 1790 | |
| 1791 | /* If this device is on a bridge, swizzle its INT_PIN */ |
| 1792 | if (bus) { |
| 1793 | /* Swizzle its INT_PINs */ |
| 1794 | target_pin = swizzle_irq_pins(dev, parent_bdg); |
| 1795 | |
| 1796 | /* Make sure the swizzle returned valid structures */ |
| 1797 | if (parent_bdg == NULL) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 1798 | printk(BIOS_WARNING, "Could not find parent bridge for this device!\n"); |
Mike Loptien | 0f5cf5e | 2014-05-12 21:46:31 -0600 | [diff] [blame] | 1799 | return -2; |
| 1800 | } |
| 1801 | } else { /* Device is not behind a bridge */ |
| 1802 | target_pin = int_pin; /* Return its own interrupt pin */ |
| 1803 | *parent_bdg = dev; /* Return its own structure */ |
| 1804 | } |
| 1805 | |
| 1806 | /* Target pin is the interrupt pin we want to assign an IRQ to */ |
| 1807 | return target_pin; |
| 1808 | } |
| 1809 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1810 | #if CONFIG(PC80_SYSTEM) |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1811 | /** |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1812 | * Assign IRQ numbers. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1813 | * |
Stefan Reinauer | 4d933dd | 2009-07-21 21:36:41 +0000 | [diff] [blame] | 1814 | * This function assigns IRQs for all functions contained within the indicated |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1815 | * device address. If the device does not exist or does not require interrupts |
Stefan Reinauer | 4d933dd | 2009-07-21 21:36:41 +0000 | [diff] [blame] | 1816 | * then this function has no effect. |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 1817 | * |
| 1818 | * This function should be called for each PCI slot in your system. |
| 1819 | * |
Kyösti Mälkki | c19d6a6 | 2019-07-04 21:39:28 +0300 | [diff] [blame] | 1820 | * @param dev Pointer to dev structure. |
Uwe Hermann | c1ee429 | 2010-10-17 19:01:48 +0000 | [diff] [blame] | 1821 | * @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD |
| 1822 | * of this slot. The particular IRQ #s that are passed in depend on the |
| 1823 | * routing inside your southbridge and on your board. |
Stefan Reinauer | 4d933dd | 2009-07-21 21:36:41 +0000 | [diff] [blame] | 1824 | */ |
Kyösti Mälkki | c19d6a6 | 2019-07-04 21:39:28 +0300 | [diff] [blame] | 1825 | void pci_assign_irqs(struct device *dev, const unsigned char pIntAtoD[4]) |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame] | 1826 | { |
Kyösti Mälkki | c19d6a6 | 2019-07-04 21:39:28 +0300 | [diff] [blame] | 1827 | u8 slot, line, irq; |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame] | 1828 | |
Kyösti Mälkki | c19d6a6 | 2019-07-04 21:39:28 +0300 | [diff] [blame] | 1829 | /* Each device may contain up to eight functions. */ |
| 1830 | slot = dev->path.pci.devfn >> 3; |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame] | 1831 | |
Kyösti Mälkki | c19d6a6 | 2019-07-04 21:39:28 +0300 | [diff] [blame] | 1832 | for (; dev ; dev = dev->sibling) { |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame] | 1833 | |
Kyösti Mälkki | c19d6a6 | 2019-07-04 21:39:28 +0300 | [diff] [blame] | 1834 | if (dev->path.pci.devfn >> 3 != slot) |
| 1835 | break; |
| 1836 | |
| 1837 | line = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame] | 1838 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1839 | /* PCI spec says all values except 1..4 are reserved. */ |
Stefan Reinauer | 4d933dd | 2009-07-21 21:36:41 +0000 | [diff] [blame] | 1840 | if ((line < 1) || (line > 4)) |
| 1841 | continue; |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame] | 1842 | |
Stefan Reinauer | 4d933dd | 2009-07-21 21:36:41 +0000 | [diff] [blame] | 1843 | irq = pIntAtoD[line - 1]; |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame] | 1844 | |
Kyösti Mälkki | c19d6a6 | 2019-07-04 21:39:28 +0300 | [diff] [blame] | 1845 | printk(BIOS_DEBUG, "Assigning IRQ %d to %s\n", irq, dev_path(dev)); |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame] | 1846 | |
Angel Pons | ceca5de | 2021-06-28 11:59:33 +0200 | [diff] [blame] | 1847 | pci_write_config8(dev, PCI_INTERRUPT_LINE, irq); |
Stefan Reinauer | 4d933dd | 2009-07-21 21:36:41 +0000 | [diff] [blame] | 1848 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 1849 | /* Change to level triggered. */ |
Angel Pons | ceca5de | 2021-06-28 11:59:33 +0200 | [diff] [blame] | 1850 | i8259_configure_irq_trigger(irq, IRQ_LEVEL_TRIGGERED); |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame] | 1851 | } |
| 1852 | } |
Stefan Reinauer | 4d933dd | 2009-07-21 21:36:41 +0000 | [diff] [blame] | 1853 | #endif |