Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 1 | /* |
| 2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
| 3 | * |
| 4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
| 5 | * David Mosberger-Tang |
| 6 | * |
| 7 | * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz> |
| 8 | * |
| 9 | * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com> |
| 10 | */ |
| 11 | |
| 12 | #include <console/console.h> |
| 13 | #include <stdlib.h> |
| 14 | #include <stdint.h> |
| 15 | #include <bitops.h> |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 16 | #include <string.h> |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame^] | 17 | #include <arch/io.h> |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 21 | #include <part/hard_reset.h> |
Eric Biederman | 30e143a | 2003-09-01 23:45:32 +0000 | [diff] [blame] | 22 | #include <part/fallback_boot.h> |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 23 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 24 | /** Given a device and register, read the size of the BAR for that register. |
| 25 | * @param dev Pointer to the device structure |
| 26 | * @param resource Pointer to the resource structure |
| 27 | * @param index Address of the pci configuration register |
| 28 | */ |
| 29 | static void pci_get_resource(struct device *dev, struct resource *resource, unsigned long index) |
| 30 | { |
| 31 | uint32_t addr, size, base; |
| 32 | unsigned long type; |
| 33 | |
| 34 | /* Initialize the resources to nothing */ |
| 35 | resource->base = 0; |
| 36 | resource->size = 0; |
| 37 | resource->align = 0; |
| 38 | resource->gran = 0; |
| 39 | resource->limit = 0; |
| 40 | resource->flags = 0; |
| 41 | resource->index = index; |
| 42 | |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 43 | addr = pci_read_config32(dev, index); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 44 | |
| 45 | /* FIXME: more consideration for 64-bit PCI devices, |
| 46 | * we currently detect their size but otherwise |
| 47 | * treat them as 32-bit resources |
| 48 | */ |
| 49 | /* get the size */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 50 | pci_write_config32(dev, index, ~0); |
| 51 | size = pci_read_config32(dev, index); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 52 | |
| 53 | /* get the minimum value the bar can be set to */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 54 | pci_write_config32(dev, index, 0); |
| 55 | base = pci_read_config32(dev, index); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 56 | |
| 57 | /* restore addr */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 58 | pci_write_config32(dev, index, addr); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 59 | |
| 60 | /* |
| 61 | * some broken hardware has read-only registers that do not |
| 62 | * really size correctly. You can tell this if addr == size |
| 63 | * Example: the acer m7229 has BARs 1-4 normally read-only. |
| 64 | * so BAR1 at offset 0x10 reads 0x1f1. If you size that register |
| 65 | * by writing 0xffffffff to it, it will read back as 0x1f1 -- a |
| 66 | * violation of the spec. |
| 67 | * We catch this case and ignore it by settting size and type to 0. |
| 68 | * This incidentally catches the common case where registers |
| 69 | * read back as 0 for both address and size. |
| 70 | */ |
| 71 | if ((addr == size) && (addr == base)) { |
| 72 | if (size != 0) { |
| 73 | printk_debug( |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 74 | "%s register %02x(%08x), read-only ignoring it\n", |
| 75 | dev_path(dev), |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 76 | index, addr); |
| 77 | } |
| 78 | resource->flags = 0; |
| 79 | } |
| 80 | /* Now compute the actual size, See PCI Spec 6.2.5.1 ... */ |
| 81 | else if (size & PCI_BASE_ADDRESS_SPACE_IO) { |
| 82 | type = size & (~PCI_BASE_ADDRESS_IO_MASK); |
| 83 | /* BUG! Top 16 bits can be zero (or not) |
| 84 | * So set them to 0xffff so they go away ... |
| 85 | */ |
| 86 | resource->size = (~((size | 0xffff0000) & PCI_BASE_ADDRESS_IO_MASK)) +1; |
| 87 | resource->align = log2(resource->size); |
| 88 | resource->gran = resource->align; |
| 89 | resource->flags = IORESOURCE_IO; |
| 90 | resource->limit = 0xffff; |
| 91 | } |
| 92 | else { |
| 93 | /* A Memory mapped base address */ |
| 94 | type = size & (~PCI_BASE_ADDRESS_MEM_MASK); |
| 95 | resource->size = (~(size &PCI_BASE_ADDRESS_MEM_MASK)) +1; |
| 96 | resource->align = log2(resource->size); |
| 97 | resource->gran = resource->align; |
| 98 | resource->flags = IORESOURCE_MEM; |
| 99 | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { |
| 100 | resource->flags |= IORESOURCE_PREFETCH; |
| 101 | } |
| 102 | type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
| 103 | if (type == PCI_BASE_ADDRESS_MEM_TYPE_32) { |
| 104 | /* 32bit limit */ |
| 105 | resource->limit = 0xffffffffUL; |
| 106 | } |
| 107 | else if (type == PCI_BASE_ADDRESS_MEM_TYPE_1M) { |
| 108 | /* 1MB limit */ |
| 109 | resource->limit = 0x000fffffUL; |
| 110 | } |
| 111 | else if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) { |
| 112 | unsigned long index_hi; |
| 113 | /* 64bit limit |
| 114 | * For now just treat this as a 32bit limit |
| 115 | */ |
| 116 | index_hi = index + 4; |
| 117 | resource->limit = 0xffffffffUL; |
| 118 | resource->flags |= IORESOURCE_PCI64; |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 119 | addr = pci_read_config32( dev, index_hi); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 120 | /* get the extended size */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 121 | pci_write_config32(dev, index_hi, 0xffffffffUL); |
| 122 | size = pci_read_config32( dev, index_hi); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 123 | |
| 124 | /* get the minimum value the bar can be set to */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 125 | pci_write_config32(dev, index_hi, 0); |
| 126 | base = pci_read_config32(dev, index_hi); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 127 | |
| 128 | /* restore addr */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 129 | pci_write_config32(dev, index_hi, addr); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 130 | |
| 131 | if ((size == 0xffffffff) && (base == 0)) { |
| 132 | /* Clear the top half of the bar */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 133 | pci_write_config32(dev, index_hi, 0); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 134 | } |
| 135 | else { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 136 | printk_err("%s Unable to handle 64-bit address\n", |
| 137 | dev_path(dev)); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 138 | resource->flags = IORESOURCE_PCI64; |
| 139 | } |
| 140 | } |
| 141 | else { |
| 142 | /* Invalid value */ |
| 143 | resource->flags = 0; |
| 144 | } |
| 145 | } |
| 146 | /* dev->size holds the flags... */ |
| 147 | return; |
| 148 | } |
| 149 | |
| 150 | /** Read the base address registers for a given device. |
| 151 | * @param dev Pointer to the dev structure |
| 152 | * @param howmany How many registers to read (6 for device, 2 for bridge) |
| 153 | */ |
| 154 | static void pci_read_bases(struct device *dev, unsigned int howmany) |
| 155 | { |
| 156 | unsigned int reg; |
| 157 | unsigned long index; |
| 158 | |
| 159 | reg = dev->resources; |
| 160 | for(index = PCI_BASE_ADDRESS_0; |
| 161 | (reg < MAX_RESOURCES) && (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) { |
| 162 | struct resource *resource; |
| 163 | resource = &dev->resource[reg]; |
| 164 | pci_get_resource(dev, resource, index); |
| 165 | reg += (resource->flags & (IORESOURCE_IO | IORESOURCE_MEM))? 1:0; |
| 166 | index += (resource->flags & IORESOURCE_PCI64)?8:4; |
| 167 | } |
| 168 | dev->resources = reg; |
| 169 | } |
| 170 | |
| 171 | |
| 172 | static void pci_bridge_read_bases(struct device *dev) |
| 173 | { |
| 174 | unsigned int reg = dev->resources; |
| 175 | |
| 176 | /* FIXME handle bridges without some of the optional resources */ |
| 177 | |
Ronald G. Minnich | 99dcf23 | 2003-09-30 02:16:47 +0000 | [diff] [blame] | 178 | printk_spew("%s: path %s\n", __FUNCTION__, dev_path(dev)); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 179 | /* Initialize the io space constraints on the current bus */ |
| 180 | dev->resource[reg].base = 0; |
| 181 | dev->resource[reg].size = 0; |
| 182 | dev->resource[reg].align = log2(PCI_IO_BRIDGE_ALIGN); |
| 183 | dev->resource[reg].gran = log2(PCI_IO_BRIDGE_ALIGN); |
| 184 | dev->resource[reg].limit = 0xffffUL; |
| 185 | dev->resource[reg].flags = IORESOURCE_IO | IORESOURCE_PCI_BRIDGE; |
| 186 | dev->resource[reg].index = PCI_IO_BASE; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 187 | compute_allocate_resource(&dev->link[0], &dev->resource[reg], |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 188 | IORESOURCE_IO, IORESOURCE_IO); |
| 189 | reg++; |
| 190 | |
| 191 | /* Initiliaze the prefetchable memory constraints on the current bus */ |
| 192 | dev->resource[reg].base = 0; |
| 193 | dev->resource[reg].size = 0; |
| 194 | dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN); |
| 195 | dev->resource[reg].gran = log2(PCI_MEM_BRIDGE_ALIGN); |
| 196 | dev->resource[reg].limit = 0xffffffffUL; |
| 197 | dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_PCI_BRIDGE; |
| 198 | dev->resource[reg].index = PCI_PREF_MEMORY_BASE; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 199 | compute_allocate_resource(&dev->link[0], &dev->resource[reg], |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 200 | IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 201 | IORESOURCE_MEM | IORESOURCE_PREFETCH); |
| 202 | reg++; |
| 203 | |
| 204 | /* Initialize the memory resources on the current bus */ |
| 205 | dev->resource[reg].base = 0; |
| 206 | dev->resource[reg].size = 0; |
| 207 | dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN); |
| 208 | dev->resource[reg].gran = log2(PCI_MEM_BRIDGE_ALIGN); |
| 209 | dev->resource[reg].limit = 0xffffffffUL; |
| 210 | dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PCI_BRIDGE; |
| 211 | dev->resource[reg].index = PCI_MEMORY_BASE; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 212 | compute_allocate_resource(&dev->link[0], &dev->resource[reg], |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 213 | IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 214 | IORESOURCE_MEM); |
| 215 | reg++; |
| 216 | |
| 217 | dev->resources = reg; |
Ronald G. Minnich | 99dcf23 | 2003-09-30 02:16:47 +0000 | [diff] [blame] | 218 | printk_spew("DONE %s: path %s\n", __FUNCTION__, dev_path(dev)); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 219 | } |
| 220 | |
| 221 | |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 222 | void pci_dev_read_resources(struct device *dev) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 223 | { |
| 224 | uint32_t addr; |
| 225 | dev->resources = 0; |
| 226 | memset(&dev->resource[0], 0, sizeof(dev->resource)); |
| 227 | pci_read_bases(dev, 6); |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 228 | addr = pci_read_config32(dev, PCI_ROM_ADDRESS); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 229 | dev->rom_address = (addr == 0xffffffff)? 0 : addr; |
| 230 | } |
| 231 | |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 232 | void pci_bus_read_resources(struct device *dev) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 233 | { |
| 234 | uint32_t addr; |
| 235 | dev->resources = 0; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 236 | memset(&dev->resource, 0, sizeof(dev->resource)); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 237 | pci_bridge_read_bases(dev); |
| 238 | pci_read_bases(dev, 2); |
| 239 | |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 240 | addr = pci_read_config32(dev, PCI_ROM_ADDRESS1); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 241 | dev->rom_address = (addr == 0xffffffff)? 0 : addr; |
| 242 | |
| 243 | } |
| 244 | |
| 245 | |
| 246 | static void pci_set_resource(struct device *dev, struct resource *resource) |
| 247 | { |
| 248 | unsigned long base, limit; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 249 | unsigned char buf[10]; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 250 | unsigned long align; |
| 251 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 252 | /* Make certain the resource has actually been set */ |
| 253 | if (!(resource->flags & IORESOURCE_SET)) { |
| 254 | #if 1 |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 255 | printk_err("ERROR: %s %02x not allocated\n", |
| 256 | dev_path(dev), resource->index); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 257 | #endif |
| 258 | return; |
| 259 | } |
| 260 | |
| 261 | /* Only handle PCI memory and IO resources for now */ |
| 262 | if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO))) |
| 263 | return; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 264 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 265 | if (resource->flags & IORESOURCE_MEM) { |
| 266 | dev->command |= PCI_COMMAND_MEMORY; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 267 | } |
| 268 | if (resource->flags & IORESOURCE_IO) { |
| 269 | dev->command |= PCI_COMMAND_IO; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 270 | } |
| 271 | if (resource->flags & IORESOURCE_PCI_BRIDGE) { |
| 272 | dev->command |= PCI_COMMAND_MASTER; |
| 273 | } |
| 274 | /* Get the base address */ |
| 275 | base = resource->base; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 276 | /* Get the resource alignment */ |
| 277 | align = 1UL << resource->align; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 278 | |
| 279 | /* Get the limit (rounded up) */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 280 | limit = base + ((resource->size + align - 1UL) & ~(align - 1UL)) -1UL; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 281 | |
| 282 | if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) { |
| 283 | /* |
| 284 | * some chipsets allow us to set/clear the IO bit. |
| 285 | * (e.g. VIA 82c686a.) So set it to be safe) |
| 286 | */ |
| 287 | limit = base + resource->size -1; |
| 288 | if (resource->flags & IORESOURCE_IO) { |
| 289 | base |= PCI_BASE_ADDRESS_SPACE_IO; |
| 290 | } |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 291 | pci_write_config32(dev, resource->index, base & 0xffffffff); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 292 | if (resource->flags & IORESOURCE_PCI64) { |
| 293 | /* FIXME handle real 64bit base addresses */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 294 | pci_write_config32(dev, resource->index + 4, 0); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 295 | } |
| 296 | } |
| 297 | else if (resource->index == PCI_IO_BASE) { |
| 298 | /* set the IO ranges |
| 299 | * WARNING: we don't really do 32-bit addressing for IO yet! |
| 300 | */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 301 | compute_allocate_resource(&dev->link[0], resource, |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 302 | IORESOURCE_IO, IORESOURCE_IO); |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 303 | pci_write_config8(dev, PCI_IO_BASE, base >> 8); |
| 304 | pci_write_config8(dev, PCI_IO_LIMIT, limit >> 8); |
Eric Biederman | 5fb929e | 2003-07-17 02:15:46 +0000 | [diff] [blame] | 305 | pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0); |
| 306 | pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 307 | } |
| 308 | else if (resource->index == PCI_MEMORY_BASE) { |
| 309 | /* set the memory range |
| 310 | */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 311 | compute_allocate_resource(&dev->link[0], resource, |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 312 | IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 313 | IORESOURCE_MEM); |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 314 | pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); |
| 315 | pci_write_config16(dev, PCI_MEMORY_LIMIT, limit >> 16); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 316 | } |
| 317 | else if (resource->index == PCI_PREF_MEMORY_BASE) { |
| 318 | /* set the prefetchable memory range |
| 319 | * WARNING: we don't really do 64-bit addressing for prefetchable memory yet! |
| 320 | */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 321 | compute_allocate_resource(&dev->link[0], resource, |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 322 | IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 323 | IORESOURCE_MEM | IORESOURCE_PREFETCH); |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 324 | pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16); |
| 325 | pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16); |
Eric Biederman | 5fb929e | 2003-07-17 02:15:46 +0000 | [diff] [blame] | 326 | pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0); |
| 327 | pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 328 | } |
| 329 | else { |
| 330 | printk_err("ERROR: invalid resource->index %x\n", |
| 331 | resource->index); |
| 332 | } |
| 333 | buf[0] = '\0'; |
| 334 | if (resource->flags & IORESOURCE_PCI_BRIDGE) { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 335 | sprintf(buf, "bus %d ", dev->link[0].secondary); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 336 | } |
| 337 | |
| 338 | printk_debug( |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 339 | "%s %02x <- [0x%08lx - 0x%08lx] %s%s\n", |
| 340 | dev_path(dev), |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 341 | resource->index, |
| 342 | resource->base, limit, |
| 343 | buf, |
| 344 | (resource->flags & IORESOURCE_IO)? "io": |
| 345 | (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem"); |
| 346 | return; |
| 347 | } |
| 348 | |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 349 | void pci_dev_set_resources(struct device *dev) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 350 | { |
| 351 | struct resource *resource, *last; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 352 | unsigned link; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 353 | uint8_t line; |
| 354 | |
| 355 | last = &dev->resource[dev->resources]; |
| 356 | |
| 357 | for(resource = &dev->resource[0]; resource < last; resource++) { |
| 358 | pci_set_resource(dev, resource); |
| 359 | } |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 360 | for(link = 0; link < dev->links; link++) { |
| 361 | struct bus *bus; |
| 362 | bus = &dev->link[link]; |
| 363 | if (bus->children) { |
| 364 | assign_resources(bus); |
| 365 | } |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | /* set a default latency timer */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 369 | pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 370 | |
| 371 | /* set a default secondary latency timer */ |
| 372 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 373 | pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 374 | } |
| 375 | |
| 376 | /* zero the irq settings */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 377 | line = pci_read_config8(dev, PCI_INTERRUPT_PIN); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 378 | if (line) { |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 379 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 380 | } |
| 381 | /* set the cache line size, so far 64 bytes is good for everyone */ |
Eric Biederman | 7a5416a | 2003-06-12 19:23:51 +0000 | [diff] [blame] | 382 | pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 383 | } |
| 384 | |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 385 | void pci_dev_enable_resources(struct device *dev) |
| 386 | { |
| 387 | uint16_t command; |
| 388 | command = pci_read_config16(dev, PCI_COMMAND); |
| 389 | command |= dev->command; |
| 390 | printk_debug("%s cmd <- %02x\n", dev_path(dev), command); |
| 391 | pci_write_config16(dev, PCI_COMMAND, command); |
| 392 | |
| 393 | enable_childrens_resources(dev); |
| 394 | } |
| 395 | |
| 396 | void pci_bus_enable_resources(struct device *dev) |
| 397 | { |
| 398 | uint16_t ctrl; |
| 399 | ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); |
| 400 | ctrl |= dev->link[0].bridge_ctrl; |
| 401 | printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); |
| 402 | pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); |
| 403 | |
| 404 | pci_dev_enable_resources(dev); |
| 405 | } |
| 406 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 407 | struct device_operations default_pci_ops_dev = { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 408 | .read_resources = pci_dev_read_resources, |
| 409 | .set_resources = pci_dev_set_resources, |
| 410 | .enable_resources = pci_dev_enable_resources, |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 411 | .init = 0, |
| 412 | .scan_bus = 0, |
| 413 | }; |
| 414 | struct device_operations default_pci_ops_bus = { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 415 | .read_resources = pci_bus_read_resources, |
| 416 | .set_resources = pci_dev_set_resources, |
| 417 | .enable_resources = pci_bus_enable_resources, |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 418 | .init = 0, |
| 419 | .scan_bus = pci_scan_bridge, |
| 420 | }; |
| 421 | static void set_pci_ops(struct device *dev) |
| 422 | { |
| 423 | struct pci_driver *driver; |
| 424 | if (dev->ops) { |
| 425 | return; |
| 426 | } |
| 427 | /* Look through the list of setup drivers and find one for |
| 428 | * this pci device |
| 429 | */ |
| 430 | for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) { |
| 431 | if ((driver->vendor == dev->vendor) && |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 432 | (driver->device == dev->device)) { |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 433 | dev->ops = driver->ops; |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 434 | #if 1 |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 435 | printk_debug("%s [%04x/%04x] %sops\n", |
| 436 | dev_path(dev), |
| 437 | driver->vendor, driver->device, |
| 438 | (driver->ops->scan_bus?"bus ":"") |
Eric Biederman | 5899fd8 | 2003-04-24 06:25:08 +0000 | [diff] [blame] | 439 | ); |
| 440 | #endif |
| 441 | return; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 442 | } |
| 443 | } |
| 444 | /* If I don't have a specific driver use the default operations */ |
| 445 | switch(dev->hdr_type & 0x7f) { /* header type */ |
| 446 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
| 447 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) |
| 448 | goto bad; |
| 449 | dev->ops = &default_pci_ops_dev; |
| 450 | break; |
| 451 | case PCI_HEADER_TYPE_BRIDGE: |
| 452 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
| 453 | goto bad; |
| 454 | dev->ops = &default_pci_ops_bus; |
| 455 | break; |
| 456 | default: |
| 457 | bad: |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 458 | printk_err("%s [%04x/%04x/%06x] has unknown header " |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 459 | "type %02x, ignoring.\n", |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 460 | dev_path(dev), |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 461 | dev->vendor, dev->device, |
| 462 | dev->class >> 8, dev->hdr_type); |
| 463 | } |
| 464 | return; |
| 465 | } |
| 466 | |
| 467 | /** |
| 468 | * Given a bus and a devfn number, find the device structure |
| 469 | * @param bus The bus structure |
| 470 | * @param devfn a device/function number |
| 471 | * @return pointer to the device structure |
| 472 | */ |
| 473 | static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn) |
| 474 | { |
| 475 | struct device *dev = 0; |
| 476 | for(; *list; list = &(*list)->sibling) { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 477 | if ((*list)->path.u.pci.devfn == devfn) { |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 478 | /* Unlink from the list */ |
| 479 | dev = *list; |
| 480 | *list = (*list)->sibling; |
| 481 | dev->sibling = 0; |
| 482 | break; |
| 483 | } |
| 484 | } |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 485 | if (dev) { |
| 486 | device_t child; |
| 487 | /* Find the last child of our parent */ |
| 488 | for(child = dev->bus->children; child && child->sibling; ) { |
| 489 | child = child->sibling; |
| 490 | } |
| 491 | /* Place the device on the list of children of it's parent. */ |
| 492 | if (child) { |
| 493 | child->sibling = dev; |
| 494 | } else { |
| 495 | dev->bus->children = dev; |
| 496 | } |
| 497 | } |
| 498 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 499 | return dev; |
| 500 | } |
| 501 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 502 | /** Scan the pci bus devices and bridges. |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 503 | * @param bus pointer to the bus structure |
| 504 | * @param min_devfn minimum devfn to look at in the scan usually 0x00 |
| 505 | * @param max_devfn maximum devfn to look at in the scan usually 0xff |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 506 | * @param max current bus number |
| 507 | * @return The maximum bus number found, after scanning all subordinate busses |
| 508 | */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 509 | unsigned int pci_scan_bus(struct bus *bus, |
| 510 | unsigned min_devfn, unsigned max_devfn, |
| 511 | unsigned int max) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 512 | { |
| 513 | unsigned int devfn; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 514 | device_t dev; |
| 515 | device_t old_devices; |
| 516 | device_t child; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 517 | |
| 518 | printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary); |
| 519 | |
| 520 | old_devices = bus->children; |
| 521 | bus->children = 0; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 522 | |
| 523 | post_code(0x24); |
| 524 | |
| 525 | |
| 526 | /* probe all devices on this bus with some optimization for non-existance and |
| 527 | single funcion devices */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 528 | for (devfn = min_devfn; devfn <= max_devfn; devfn++) { |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 529 | uint32_t id, class; |
Eric Biederman | 30e143a | 2003-09-01 23:45:32 +0000 | [diff] [blame] | 530 | uint8_t hdr_type; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 531 | |
| 532 | /* First thing setup the device structure */ |
| 533 | dev = pci_scan_get_dev(&old_devices, devfn); |
| 534 | |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 535 | /* Detect if a device is present */ |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 536 | if (!dev) { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 537 | struct device dummy; |
| 538 | dummy.bus = bus; |
| 539 | dummy.path.type = DEVICE_PATH_PCI; |
| 540 | dummy.path.u.pci.devfn = devfn; |
| 541 | id = pci_read_config32(&dummy, PCI_VENDOR_ID); |
| 542 | /* some broken boards return 0 if a slot is empty: */ |
| 543 | if ( (id == 0xffffffff) || (id == 0x00000000) || |
| 544 | (id == 0x0000ffff) || (id == 0xffff0000)) |
| 545 | { |
| 546 | printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id); |
| 547 | if (PCI_FUNC(devfn) == 0x00) { |
| 548 | /* if this is a function 0 device and it is not present, |
| 549 | skip to next device */ |
| 550 | devfn += 0x07; |
| 551 | } |
| 552 | /* multi function device, skip to next function */ |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 553 | continue; |
| 554 | } |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 555 | dev = alloc_dev(bus, &dummy.path); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 556 | } |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 557 | else { |
| 558 | /* Run the magic enable/disable sequence for the device */ |
| 559 | if (dev->ops && dev->ops->enable) { |
| 560 | dev->ops->enable(dev); |
| 561 | } |
| 562 | /* Now read the vendor and device id */ |
| 563 | id = pci_read_config32(dev, PCI_VENDOR_ID); |
| 564 | } |
| 565 | |
| 566 | /* Read the rest of the pci configuration information */ |
| 567 | hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 568 | class = pci_read_config32(dev, PCI_CLASS_REVISION); |
| 569 | |
| 570 | /* Store the interesting information in the device structure */ |
| 571 | dev->vendor = id & 0xffff; |
| 572 | dev->device = (id >> 16) & 0xffff; |
| 573 | dev->hdr_type = hdr_type; |
| 574 | /* class code, the upper 3 bytes of PCI_CLASS_REVISION */ |
| 575 | dev->class = class >> 8; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 576 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 577 | /* Look at the vendor and device id, or at least the |
| 578 | * header type and class and figure out which set of configuration |
| 579 | * methods to use. |
| 580 | */ |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 581 | if (!dev->ops) { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 582 | set_pci_ops(dev); |
| 583 | /* Error if we don't have some pci operations for it */ |
| 584 | if (!dev->ops) { |
| 585 | printk_err("%s No device operations\n", |
| 586 | dev_path(dev)); |
| 587 | continue; |
| 588 | } |
| 589 | /* Now run the magic enable/disable sequence for the device */ |
| 590 | if (dev->ops && dev->ops->enable) { |
| 591 | dev->ops->enable(dev); |
| 592 | } |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 593 | } |
Eric Biederman | 4086d16 | 2003-07-17 03:26:03 +0000 | [diff] [blame] | 594 | |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 595 | printk_debug("%s [%04x/%04x] %s\n", |
| 596 | dev_path(dev), |
Eric Biederman | 4086d16 | 2003-07-17 03:26:03 +0000 | [diff] [blame] | 597 | dev->vendor, dev->device, |
| 598 | dev->enable?"enabled": "disabled"); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 599 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 600 | if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) { |
| 601 | /* if this is not a multi function device, don't waste time probe |
| 602 | another function. Skip to next device. */ |
| 603 | devfn += 0x07; |
| 604 | } |
| 605 | } |
| 606 | post_code(0x25); |
| 607 | |
| 608 | for(child = bus->children; child; child = child->sibling) { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 609 | if (!child->ops->scan_bus) { |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 610 | continue; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 611 | } |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 612 | max = child->ops->scan_bus(child, max); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 613 | } |
| 614 | /* |
| 615 | * We've scanned the bus and so we know all about what's on |
| 616 | * the other side of any bridges that may be on this bus plus |
| 617 | * any devices. |
| 618 | * |
| 619 | * Return how far we've got finding sub-buses. |
| 620 | */ |
| 621 | printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max); |
| 622 | post_code(0x55); |
| 623 | return max; |
| 624 | } |
| 625 | |
| 626 | /** Scan the bus, first for bridges and next for devices. |
| 627 | * @param pci_bus pointer to the bus structure |
| 628 | * @return The maximum bus number found, after scanning all subordinate busses |
| 629 | */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 630 | unsigned int pci_scan_bridge(struct device *dev, unsigned int max) |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 631 | { |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 632 | struct bus *bus; |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 633 | uint32_t buses; |
| 634 | uint16_t cr; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 635 | |
Ronald G. Minnich | 99dcf23 | 2003-09-30 02:16:47 +0000 | [diff] [blame] | 636 | printk_spew("%s: dev %p, max %d\n", __FUNCTION__, dev, max); |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 637 | bus = &dev->link[0]; |
| 638 | dev->links = 1; |
| 639 | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 640 | /* Set up the primary, secondary and subordinate bus numbers. We have |
| 641 | * no idea how many buses are behind this bridge yet, so we set the |
| 642 | * subordinate bus number to 0xff for the moment |
| 643 | */ |
| 644 | bus->secondary = ++max; |
| 645 | bus->subordinate = 0xff; |
| 646 | |
| 647 | /* Clear all status bits and turn off memory, I/O and master enables. */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 648 | cr = pci_read_config16(dev, PCI_COMMAND); |
| 649 | pci_write_config16(dev, PCI_COMMAND, 0x0000); |
| 650 | pci_write_config16(dev, PCI_STATUS, 0xffff); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 651 | |
| 652 | /* |
| 653 | * Read the existing primary/secondary/subordinate bus |
| 654 | * number configuration. |
| 655 | */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 656 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 657 | |
| 658 | /* Configure the bus numbers for this bridge: the configuration |
| 659 | * transactions will not be propagated by the bridge if it is not |
| 660 | * correctly configured |
| 661 | */ |
| 662 | buses &= 0xff000000; |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 663 | buses |= (((unsigned int) (dev->bus->secondary) << 0) | |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 664 | ((unsigned int) (bus->secondary) << 8) | |
| 665 | ((unsigned int) (bus->subordinate) << 16)); |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 666 | pci_write_config32(dev, PCI_PRIMARY_BUS, buses); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 667 | |
| 668 | /* Now we can scan all subordinate buses i.e. the bus hehind the bridge */ |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 669 | max = pci_scan_bus(bus, 0x00, 0xff, max); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 670 | |
| 671 | /* We know the number of buses behind this bridge. Set the subordinate |
| 672 | * bus number to its real value |
| 673 | */ |
| 674 | bus->subordinate = max; |
| 675 | buses = (buses & 0xff00ffff) | |
| 676 | ((unsigned int) (bus->subordinate) << 16); |
Eric Biederman | e9a271e3 | 2003-09-02 03:36:25 +0000 | [diff] [blame] | 677 | pci_write_config32(dev, PCI_PRIMARY_BUS, buses); |
| 678 | pci_write_config16(dev, PCI_COMMAND, cr); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 679 | |
Ronald G. Minnich | 99dcf23 | 2003-09-30 02:16:47 +0000 | [diff] [blame] | 680 | printk_spew("%s returns max %d\n", __FUNCTION__, max); |
Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame] | 681 | return max; |
| 682 | } |
Ronald G. Minnich | 6dd6c685 | 2003-10-02 00:08:42 +0000 | [diff] [blame^] | 683 | /* |
| 684 | Tell the EISA int controller this int must be level triggered |
| 685 | THIS IS A KLUDGE -- sorry, this needs to get cleaned up. |
| 686 | */ |
| 687 | static void pci_level_irq(unsigned char intNum) |
| 688 | { |
| 689 | unsigned intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8); |
| 690 | |
| 691 | intBits |= (1 << intNum); |
| 692 | |
| 693 | // Write new values |
| 694 | outb((unsigned char) intBits, 0x4d0); |
| 695 | outb((unsigned char) (intBits >> 8), 0x4d1); |
| 696 | } |
| 697 | |
| 698 | |
| 699 | /* |
| 700 | This function assigns IRQs for all functions contained within |
| 701 | the indicated device address. If the device does not exist or does |
| 702 | not require interrupts then this function has no effect. |
| 703 | |
| 704 | This function should be called for each PCI slot in your system. |
| 705 | |
| 706 | pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of |
| 707 | this slot. |
| 708 | The particular irq #s that are passed in depend on the routing inside |
| 709 | your southbridge and on your motherboard. |
| 710 | |
| 711 | -kevinh@ispiri.com |
| 712 | */ |
| 713 | void pci_assign_irqs(unsigned bus, unsigned slot, |
| 714 | const unsigned char pIntAtoD[4]) |
| 715 | { |
| 716 | unsigned functNum; |
| 717 | device_t pdev; |
| 718 | unsigned char line; |
| 719 | unsigned char irq; |
| 720 | unsigned char readback; |
| 721 | |
| 722 | /* Each slot may contain up to eight functions */ |
| 723 | for (functNum = 0; functNum < 8; functNum++) { |
| 724 | pdev = dev_find_slot(bus, (slot << 3) + functNum); |
| 725 | |
| 726 | if (pdev) { |
| 727 | line = pci_read_config8(pdev, PCI_INTERRUPT_PIN); |
| 728 | |
| 729 | // PCI spec says all other values are reserved |
| 730 | if ((line >= 1) && (line <= 4)) { |
| 731 | irq = pIntAtoD[line - 1]; |
| 732 | |
| 733 | printk_debug("Assigning IRQ %d to %d:%x.%d\n", \ |
| 734 | irq, bus, slot, functNum); |
| 735 | |
| 736 | pci_write_config8(pdev, PCI_INTERRUPT_LINE,\ |
| 737 | pIntAtoD[line - 1]); |
| 738 | |
| 739 | readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE); |
| 740 | printk_debug(" Readback = %d\n", readback); |
| 741 | |
| 742 | // Change to level triggered |
| 743 | pci_level_irq(pIntAtoD[line - 1]); |
| 744 | } |
| 745 | } |
| 746 | } |
| 747 | } |