Eric Biederman | 8ca8d76 | 2003-04-22 19:02:15 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
| 3 | * |
| 4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
| 5 | * David Mosberger-Tang |
| 6 | * |
| 7 | * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz> |
| 8 | * |
| 9 | * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com> |
| 10 | */ |
| 11 | |
| 12 | #include <console/console.h> |
| 13 | #include <stdlib.h> |
| 14 | #include <stdint.h> |
| 15 | #include <bitops.h> |
| 16 | #include <pci.h> |
| 17 | #include <pci_ids.h> |
| 18 | #include <string.h> |
| 19 | |
| 20 | static unsigned int pci_scan_bridge(struct device *bus, unsigned int max); |
| 21 | |
| 22 | /** Given a device and register, read the size of the BAR for that register. |
| 23 | * @param dev Pointer to the device structure |
| 24 | * @param resource Pointer to the resource structure |
| 25 | * @param index Address of the pci configuration register |
| 26 | */ |
| 27 | static void pci_get_resource(struct device *dev, struct resource *resource, unsigned long index) |
| 28 | { |
| 29 | uint32_t addr, size, base; |
| 30 | unsigned long type; |
| 31 | |
| 32 | /* Initialize the resources to nothing */ |
| 33 | resource->base = 0; |
| 34 | resource->size = 0; |
| 35 | resource->align = 0; |
| 36 | resource->gran = 0; |
| 37 | resource->limit = 0; |
| 38 | resource->flags = 0; |
| 39 | resource->index = index; |
| 40 | |
| 41 | pci_read_config_dword(dev, index, &addr); |
| 42 | if (addr == 0xffffffffUL) |
| 43 | return; |
| 44 | |
| 45 | /* FIXME: more consideration for 64-bit PCI devices, |
| 46 | * we currently detect their size but otherwise |
| 47 | * treat them as 32-bit resources |
| 48 | */ |
| 49 | /* get the size */ |
| 50 | pci_write_config_dword(dev, index, ~0); |
| 51 | pci_read_config_dword(dev, index, &size); |
| 52 | |
| 53 | /* get the minimum value the bar can be set to */ |
| 54 | pci_write_config_dword(dev, index, 0); |
| 55 | pci_read_config_dword(dev, index, &base); |
| 56 | |
| 57 | /* restore addr */ |
| 58 | pci_write_config_dword(dev, index, addr); |
| 59 | |
| 60 | /* |
| 61 | * some broken hardware has read-only registers that do not |
| 62 | * really size correctly. You can tell this if addr == size |
| 63 | * Example: the acer m7229 has BARs 1-4 normally read-only. |
| 64 | * so BAR1 at offset 0x10 reads 0x1f1. If you size that register |
| 65 | * by writing 0xffffffff to it, it will read back as 0x1f1 -- a |
| 66 | * violation of the spec. |
| 67 | * We catch this case and ignore it by settting size and type to 0. |
| 68 | * This incidentally catches the common case where registers |
| 69 | * read back as 0 for both address and size. |
| 70 | */ |
| 71 | if ((addr == size) && (addr == base)) { |
| 72 | if (size != 0) { |
| 73 | printk_debug( |
| 74 | "PCI: %02x:%02x.%01x register %02x(%08x), read-only ignoring it\n", |
| 75 | dev->bus->secondary, |
| 76 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
| 77 | index, addr); |
| 78 | } |
| 79 | resource->flags = 0; |
| 80 | } |
| 81 | /* Now compute the actual size, See PCI Spec 6.2.5.1 ... */ |
| 82 | else if (size & PCI_BASE_ADDRESS_SPACE_IO) { |
| 83 | type = size & (~PCI_BASE_ADDRESS_IO_MASK); |
| 84 | /* BUG! Top 16 bits can be zero (or not) |
| 85 | * So set them to 0xffff so they go away ... |
| 86 | */ |
| 87 | resource->size = (~((size | 0xffff0000) & PCI_BASE_ADDRESS_IO_MASK)) +1; |
| 88 | resource->align = log2(resource->size); |
| 89 | resource->gran = resource->align; |
| 90 | resource->flags = IORESOURCE_IO; |
| 91 | resource->limit = 0xffff; |
| 92 | } |
| 93 | else { |
| 94 | /* A Memory mapped base address */ |
| 95 | type = size & (~PCI_BASE_ADDRESS_MEM_MASK); |
| 96 | resource->size = (~(size &PCI_BASE_ADDRESS_MEM_MASK)) +1; |
| 97 | resource->align = log2(resource->size); |
| 98 | resource->gran = resource->align; |
| 99 | resource->flags = IORESOURCE_MEM; |
| 100 | if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) { |
| 101 | resource->flags |= IORESOURCE_PREFETCH; |
| 102 | } |
| 103 | type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
| 104 | if (type == PCI_BASE_ADDRESS_MEM_TYPE_32) { |
| 105 | /* 32bit limit */ |
| 106 | resource->limit = 0xffffffffUL; |
| 107 | } |
| 108 | else if (type == PCI_BASE_ADDRESS_MEM_TYPE_1M) { |
| 109 | /* 1MB limit */ |
| 110 | resource->limit = 0x000fffffUL; |
| 111 | } |
| 112 | else if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) { |
| 113 | unsigned long index_hi; |
| 114 | /* 64bit limit |
| 115 | * For now just treat this as a 32bit limit |
| 116 | */ |
| 117 | index_hi = index + 4; |
| 118 | resource->limit = 0xffffffffUL; |
| 119 | resource->flags |= IORESOURCE_PCI64; |
| 120 | pci_read_config_dword( dev, index_hi, &addr); |
| 121 | /* get the extended size */ |
| 122 | pci_write_config_dword(dev, index_hi, 0xffffffffUL); |
| 123 | pci_read_config_dword( dev, index_hi, &size); |
| 124 | |
| 125 | /* get the minimum value the bar can be set to */ |
| 126 | pci_write_config_dword(dev, index_hi, 0); |
| 127 | pci_read_config_dword(dev, index_hi, &base); |
| 128 | |
| 129 | /* restore addr */ |
| 130 | pci_write_config_dword(dev, index_hi, addr); |
| 131 | |
| 132 | if ((size == 0xffffffff) && (base == 0)) { |
| 133 | /* Clear the top half of the bar */ |
| 134 | pci_write_config_dword(dev, index_hi, 0); |
| 135 | } |
| 136 | else { |
| 137 | printk_err("PCI: %02x:%02x.%01x Unable to handle 64-bit address\n", |
| 138 | dev->bus->secondary, |
| 139 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); |
| 140 | resource->flags = IORESOURCE_PCI64; |
| 141 | } |
| 142 | } |
| 143 | else { |
| 144 | /* Invalid value */ |
| 145 | resource->flags = 0; |
| 146 | } |
| 147 | } |
| 148 | /* dev->size holds the flags... */ |
| 149 | return; |
| 150 | } |
| 151 | |
| 152 | /** Read the base address registers for a given device. |
| 153 | * @param dev Pointer to the dev structure |
| 154 | * @param howmany How many registers to read (6 for device, 2 for bridge) |
| 155 | */ |
| 156 | static void pci_read_bases(struct device *dev, unsigned int howmany) |
| 157 | { |
| 158 | unsigned int reg; |
| 159 | unsigned long index; |
| 160 | |
| 161 | reg = dev->resources; |
| 162 | for(index = PCI_BASE_ADDRESS_0; |
| 163 | (reg < MAX_RESOURCES) && (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) { |
| 164 | struct resource *resource; |
| 165 | resource = &dev->resource[reg]; |
| 166 | pci_get_resource(dev, resource, index); |
| 167 | reg += (resource->flags & (IORESOURCE_IO | IORESOURCE_MEM))? 1:0; |
| 168 | index += (resource->flags & IORESOURCE_PCI64)?8:4; |
| 169 | } |
| 170 | dev->resources = reg; |
| 171 | } |
| 172 | |
| 173 | |
| 174 | static void pci_bridge_read_bases(struct device *dev) |
| 175 | { |
| 176 | unsigned int reg = dev->resources; |
| 177 | |
| 178 | /* FIXME handle bridges without some of the optional resources */ |
| 179 | |
| 180 | /* Initialize the io space constraints on the current bus */ |
| 181 | dev->resource[reg].base = 0; |
| 182 | dev->resource[reg].size = 0; |
| 183 | dev->resource[reg].align = log2(PCI_IO_BRIDGE_ALIGN); |
| 184 | dev->resource[reg].gran = log2(PCI_IO_BRIDGE_ALIGN); |
| 185 | dev->resource[reg].limit = 0xffffUL; |
| 186 | dev->resource[reg].flags = IORESOURCE_IO | IORESOURCE_PCI_BRIDGE; |
| 187 | dev->resource[reg].index = PCI_IO_BASE; |
| 188 | compute_allocate_resource(dev, &dev->resource[reg], |
| 189 | IORESOURCE_IO, IORESOURCE_IO); |
| 190 | reg++; |
| 191 | |
| 192 | /* Initiliaze the prefetchable memory constraints on the current bus */ |
| 193 | dev->resource[reg].base = 0; |
| 194 | dev->resource[reg].size = 0; |
| 195 | dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN); |
| 196 | dev->resource[reg].gran = log2(PCI_MEM_BRIDGE_ALIGN); |
| 197 | dev->resource[reg].limit = 0xffffffffUL; |
| 198 | dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_PCI_BRIDGE; |
| 199 | dev->resource[reg].index = PCI_PREF_MEMORY_BASE; |
| 200 | compute_allocate_resource(dev, &dev->resource[reg], |
| 201 | IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 202 | IORESOURCE_MEM | IORESOURCE_PREFETCH); |
| 203 | reg++; |
| 204 | |
| 205 | /* Initialize the memory resources on the current bus */ |
| 206 | dev->resource[reg].base = 0; |
| 207 | dev->resource[reg].size = 0; |
| 208 | dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN); |
| 209 | dev->resource[reg].gran = log2(PCI_MEM_BRIDGE_ALIGN); |
| 210 | dev->resource[reg].limit = 0xffffffffUL; |
| 211 | dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PCI_BRIDGE; |
| 212 | dev->resource[reg].index = PCI_MEMORY_BASE; |
| 213 | compute_allocate_resource(dev, &dev->resource[reg], |
| 214 | IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 215 | IORESOURCE_MEM); |
| 216 | reg++; |
| 217 | |
| 218 | dev->resources = reg; |
| 219 | } |
| 220 | |
| 221 | |
| 222 | static void pci_dev_read_resources(struct device *dev) |
| 223 | { |
| 224 | uint32_t addr; |
| 225 | dev->resources = 0; |
| 226 | memset(&dev->resource[0], 0, sizeof(dev->resource)); |
| 227 | pci_read_bases(dev, 6); |
| 228 | pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr); |
| 229 | dev->rom_address = (addr == 0xffffffff)? 0 : addr; |
| 230 | } |
| 231 | |
| 232 | static void pci_bus_read_resources(struct device *dev) |
| 233 | { |
| 234 | uint32_t addr; |
| 235 | dev->resources = 0; |
| 236 | memset(&dev->resource[0], 0, sizeof(dev->resource)); |
| 237 | pci_bridge_read_bases(dev); |
| 238 | pci_read_bases(dev, 2); |
| 239 | |
| 240 | pci_read_config_dword(dev, PCI_ROM_ADDRESS1, &addr); |
| 241 | dev->rom_address = (addr == 0xffffffff)? 0 : addr; |
| 242 | |
| 243 | } |
| 244 | |
| 245 | |
| 246 | static void pci_set_resource(struct device *dev, struct resource *resource) |
| 247 | { |
| 248 | unsigned long base, limit; |
| 249 | unsigned long bridge_align = PCI_MEM_BRIDGE_ALIGN; |
| 250 | unsigned char buf[10]; |
| 251 | |
| 252 | /* Make certain the resource has actually been set */ |
| 253 | if (!(resource->flags & IORESOURCE_SET)) { |
| 254 | #if 1 |
| 255 | printk_err("ERROR: %02x:%02x.%01x %02x not allocated\n", |
| 256 | dev->bus->secondary, |
| 257 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
| 258 | resource->index); |
| 259 | #endif |
| 260 | return; |
| 261 | } |
| 262 | |
| 263 | /* Only handle PCI memory and IO resources for now */ |
| 264 | if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO))) |
| 265 | return; |
| 266 | |
| 267 | if (resource->flags & IORESOURCE_MEM) { |
| 268 | dev->command |= PCI_COMMAND_MEMORY; |
| 269 | bridge_align = PCI_MEM_BRIDGE_ALIGN; |
| 270 | } |
| 271 | if (resource->flags & IORESOURCE_IO) { |
| 272 | dev->command |= PCI_COMMAND_IO; |
| 273 | bridge_align = PCI_IO_BRIDGE_ALIGN; |
| 274 | } |
| 275 | if (resource->flags & IORESOURCE_PCI_BRIDGE) { |
| 276 | dev->command |= PCI_COMMAND_MASTER; |
| 277 | } |
| 278 | /* Get the base address */ |
| 279 | base = resource->base; |
| 280 | |
| 281 | /* Get the limit (rounded up) */ |
| 282 | limit = base + ((resource->size + bridge_align - 1UL) & ~(bridge_align -1)) -1UL; |
| 283 | |
| 284 | if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) { |
| 285 | /* |
| 286 | * some chipsets allow us to set/clear the IO bit. |
| 287 | * (e.g. VIA 82c686a.) So set it to be safe) |
| 288 | */ |
| 289 | limit = base + resource->size -1; |
| 290 | if (resource->flags & IORESOURCE_IO) { |
| 291 | base |= PCI_BASE_ADDRESS_SPACE_IO; |
| 292 | } |
| 293 | pci_write_config_dword(dev, resource->index, base & 0xffffffff); |
| 294 | if (resource->flags & IORESOURCE_PCI64) { |
| 295 | /* FIXME handle real 64bit base addresses */ |
| 296 | pci_write_config_dword(dev, resource->index + 4, 0); |
| 297 | } |
| 298 | } |
| 299 | else if (resource->index == PCI_IO_BASE) { |
| 300 | /* set the IO ranges |
| 301 | * WARNING: we don't really do 32-bit addressing for IO yet! |
| 302 | */ |
| 303 | compute_allocate_resource(dev, resource, |
| 304 | IORESOURCE_IO, IORESOURCE_IO); |
| 305 | pci_write_config_byte(dev, PCI_IO_BASE, base >> 8); |
| 306 | pci_write_config_byte(dev, PCI_IO_LIMIT, limit >> 8); |
| 307 | } |
| 308 | else if (resource->index == PCI_MEMORY_BASE) { |
| 309 | /* set the memory range |
| 310 | */ |
| 311 | compute_allocate_resource(dev, resource, |
| 312 | IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 313 | IORESOURCE_MEM); |
| 314 | pci_write_config_word(dev, PCI_MEMORY_BASE, base >> 16); |
| 315 | pci_write_config_word(dev, PCI_MEMORY_LIMIT, limit >> 16); |
| 316 | } |
| 317 | else if (resource->index == PCI_PREF_MEMORY_BASE) { |
| 318 | /* set the prefetchable memory range |
| 319 | * WARNING: we don't really do 64-bit addressing for prefetchable memory yet! |
| 320 | */ |
| 321 | compute_allocate_resource(dev, resource, |
| 322 | IORESOURCE_MEM | IORESOURCE_PREFETCH, |
| 323 | IORESOURCE_MEM | IORESOURCE_PREFETCH); |
| 324 | pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, base >> 16); |
| 325 | pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16); |
| 326 | } |
| 327 | else { |
| 328 | printk_err("ERROR: invalid resource->index %x\n", |
| 329 | resource->index); |
| 330 | } |
| 331 | buf[0] = '\0'; |
| 332 | if (resource->flags & IORESOURCE_PCI_BRIDGE) { |
| 333 | sprintf(buf, "bus %d ", dev->secondary); |
| 334 | } |
| 335 | |
| 336 | printk_debug( |
| 337 | "PCI: %02x:%02x.%01x %02x <- [0x%08lx - 0x%08lx] %s%s\n", |
| 338 | dev->bus->secondary, |
| 339 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
| 340 | resource->index, |
| 341 | resource->base, limit, |
| 342 | buf, |
| 343 | (resource->flags & IORESOURCE_IO)? "io": |
| 344 | (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem"); |
| 345 | return; |
| 346 | } |
| 347 | |
| 348 | static void pci_dev_set_resources(struct device *dev) |
| 349 | { |
| 350 | struct resource *resource, *last; |
| 351 | uint8_t line; |
| 352 | |
| 353 | last = &dev->resource[dev->resources]; |
| 354 | |
| 355 | for(resource = &dev->resource[0]; resource < last; resource++) { |
| 356 | pci_set_resource(dev, resource); |
| 357 | } |
| 358 | if (dev->children) { |
| 359 | assign_resources(dev); |
| 360 | } |
| 361 | |
| 362 | /* set a default latency timer */ |
| 363 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); |
| 364 | |
| 365 | /* set a default secondary latency timer */ |
| 366 | if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { |
| 367 | pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); |
| 368 | } |
| 369 | |
| 370 | /* zero the irq settings */ |
| 371 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &line); |
| 372 | if (line) { |
| 373 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0); |
| 374 | } |
| 375 | /* set the cache line size, so far 64 bytes is good for everyone */ |
| 376 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); |
| 377 | } |
| 378 | |
| 379 | struct device_operations default_pci_ops_dev = { |
| 380 | .read_resources = pci_dev_read_resources, |
| 381 | .set_resources = pci_dev_set_resources, |
| 382 | .init = 0, |
| 383 | .scan_bus = 0, |
| 384 | }; |
| 385 | struct device_operations default_pci_ops_bus = { |
| 386 | .read_resources = pci_bus_read_resources, |
| 387 | .set_resources = pci_dev_set_resources, |
| 388 | .init = 0, |
| 389 | .scan_bus = pci_scan_bridge, |
| 390 | }; |
| 391 | static void set_pci_ops(struct device *dev) |
| 392 | { |
| 393 | struct pci_driver *driver; |
| 394 | if (dev->ops) { |
| 395 | return; |
| 396 | } |
| 397 | /* Look through the list of setup drivers and find one for |
| 398 | * this pci device |
| 399 | */ |
| 400 | for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) { |
| 401 | if ((driver->vendor == dev->vendor) && |
| 402 | (driver->device = dev->device)) { |
| 403 | dev->ops = driver->ops; |
| 404 | break; |
| 405 | } |
| 406 | } |
| 407 | /* If I don't have a specific driver use the default operations */ |
| 408 | switch(dev->hdr_type & 0x7f) { /* header type */ |
| 409 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
| 410 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) |
| 411 | goto bad; |
| 412 | dev->ops = &default_pci_ops_dev; |
| 413 | break; |
| 414 | case PCI_HEADER_TYPE_BRIDGE: |
| 415 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
| 416 | goto bad; |
| 417 | dev->ops = &default_pci_ops_bus; |
| 418 | break; |
| 419 | default: |
| 420 | bad: |
| 421 | printk_err("PCI: %02x:%02x.%01x [%04x/%04x/%06x] has unknown header " |
| 422 | "type %02x, ignoring.\n", |
| 423 | dev->bus->secondary, |
| 424 | PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
| 425 | dev->vendor, dev->device, |
| 426 | dev->class >> 8, dev->hdr_type); |
| 427 | } |
| 428 | return; |
| 429 | } |
| 430 | |
| 431 | /** |
| 432 | * Given a bus and a devfn number, find the device structure |
| 433 | * @param bus The bus structure |
| 434 | * @param devfn a device/function number |
| 435 | * @return pointer to the device structure |
| 436 | */ |
| 437 | static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn) |
| 438 | { |
| 439 | struct device *dev = 0; |
| 440 | for(; *list; list = &(*list)->sibling) { |
| 441 | if ((*list)->devfn == devfn) { |
| 442 | /* Unlink from the list */ |
| 443 | dev = *list; |
| 444 | *list = (*list)->sibling; |
| 445 | dev->sibling = 0; |
| 446 | break; |
| 447 | } |
| 448 | } |
| 449 | return dev; |
| 450 | } |
| 451 | |
| 452 | |
| 453 | /** Scan the pci bus devices and bridges. |
| 454 | * @param pci_bus pointer to the bus structure |
| 455 | * @param max current bus number |
| 456 | * @return The maximum bus number found, after scanning all subordinate busses |
| 457 | */ |
| 458 | unsigned int pci_scan_bus(struct device *bus, unsigned int max) |
| 459 | { |
| 460 | unsigned int devfn; |
| 461 | struct device *dev, **bus_last; |
| 462 | struct device *old_devices; |
| 463 | struct device *child; |
| 464 | |
| 465 | printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary); |
| 466 | |
| 467 | old_devices = bus->children; |
| 468 | bus->children = 0; |
| 469 | bus_last = &bus->children; |
| 470 | |
| 471 | post_code(0x24); |
| 472 | |
| 473 | |
| 474 | /* probe all devices on this bus with some optimization for non-existance and |
| 475 | single funcion devices */ |
| 476 | for (devfn = 0; devfn < 0xff; devfn++) { |
| 477 | struct device dummy; |
| 478 | uint32_t id, class; |
| 479 | uint8_t cmd, tmp, hdr_type; |
| 480 | |
| 481 | /* First thing setup the device structure */ |
| 482 | dev = pci_scan_get_dev(&old_devices, devfn); |
| 483 | |
| 484 | dummy.bus = bus; |
| 485 | dummy.devfn = devfn; |
| 486 | pci_read_config_dword(&dummy, PCI_VENDOR_ID, &id); |
| 487 | /* some broken boards return 0 if a slot is empty: */ |
| 488 | if (!dev && |
| 489 | (id == 0xffffffff || id == 0x00000000 || |
| 490 | id == 0x0000ffff || id == 0xffff0000)) { |
| 491 | printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id); |
| 492 | if (PCI_FUNC(devfn) == 0x00) { |
| 493 | /* if this is a function 0 device and it is not present, |
| 494 | skip to next device */ |
| 495 | devfn += 0x07; |
| 496 | } |
| 497 | /* multi function device, skip to next function */ |
| 498 | continue; |
| 499 | } |
| 500 | pci_read_config_byte(&dummy, PCI_HEADER_TYPE, &hdr_type); |
| 501 | pci_read_config_dword(&dummy, PCI_CLASS_REVISION, &class); |
| 502 | |
| 503 | if (!dev) { |
| 504 | if ((dev = malloc(sizeof(*dev))) == 0) { |
| 505 | printk_err("PCI: out of memory.\n"); |
| 506 | continue; |
| 507 | } |
| 508 | memset(dev, 0, sizeof(*dev)); |
| 509 | } |
| 510 | |
| 511 | dev->bus = bus; |
| 512 | dev->devfn = devfn; |
| 513 | dev->vendor = id & 0xffff; |
| 514 | dev->device = (id >> 16) & 0xffff; |
| 515 | dev->hdr_type = hdr_type; |
| 516 | /* class code, the upper 3 bytes of PCI_CLASS_REVISION */ |
| 517 | dev->class = class >> 8; |
| 518 | |
| 519 | /* non-destructively determine if device can be a master: */ |
| 520 | pci_read_config_byte(dev, PCI_COMMAND, &cmd); |
| 521 | pci_write_config_byte(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); |
| 522 | pci_read_config_byte(dev, PCI_COMMAND, &tmp); |
| 523 | |
| 524 | dev->master = ((tmp & PCI_COMMAND_MASTER) != 0); |
| 525 | pci_write_config_byte(dev, PCI_COMMAND, cmd); |
| 526 | |
| 527 | /* Look at the vendor and device id, or at least the |
| 528 | * header type and class and figure out which set of configuration |
| 529 | * methods to use. |
| 530 | */ |
| 531 | set_pci_ops(dev); |
| 532 | /* Kill the device if we don't have some pci operations for it */ |
| 533 | if (!dev->ops) { |
| 534 | free(dev); |
| 535 | continue; |
| 536 | } |
| 537 | printk_debug("PCI: %02x:%02x.%01x [%04x/%04x]\n", |
| 538 | bus->secondary, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
| 539 | dev->vendor, dev->device); |
| 540 | |
| 541 | /* Put it into the global device chain. */ |
| 542 | append_device(dev); |
| 543 | |
| 544 | /* Now insert it into the list of devices held by the parent bus. */ |
| 545 | *bus_last = dev; |
| 546 | bus_last = &dev->sibling; |
| 547 | |
| 548 | if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) { |
| 549 | /* if this is not a multi function device, don't waste time probe |
| 550 | another function. Skip to next device. */ |
| 551 | devfn += 0x07; |
| 552 | } |
| 553 | } |
| 554 | post_code(0x25); |
| 555 | |
| 556 | for(child = bus->children; child; child = child->sibling) { |
| 557 | if (!child->ops->scan_bus) |
| 558 | continue; |
| 559 | max = child->ops->scan_bus(child, max); |
| 560 | |
| 561 | } |
| 562 | /* |
| 563 | * We've scanned the bus and so we know all about what's on |
| 564 | * the other side of any bridges that may be on this bus plus |
| 565 | * any devices. |
| 566 | * |
| 567 | * Return how far we've got finding sub-buses. |
| 568 | */ |
| 569 | printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max); |
| 570 | post_code(0x55); |
| 571 | return max; |
| 572 | } |
| 573 | |
| 574 | /** Scan the bus, first for bridges and next for devices. |
| 575 | * @param pci_bus pointer to the bus structure |
| 576 | * @return The maximum bus number found, after scanning all subordinate busses |
| 577 | */ |
| 578 | static unsigned int pci_scan_bridge(struct device *bus, unsigned int max) |
| 579 | { |
| 580 | uint32_t buses; |
| 581 | uint16_t cr; |
| 582 | /* Set up the primary, secondary and subordinate bus numbers. We have |
| 583 | * no idea how many buses are behind this bridge yet, so we set the |
| 584 | * subordinate bus number to 0xff for the moment |
| 585 | */ |
| 586 | bus->secondary = ++max; |
| 587 | bus->subordinate = 0xff; |
| 588 | |
| 589 | /* Clear all status bits and turn off memory, I/O and master enables. */ |
| 590 | pci_read_config_word(bus, PCI_COMMAND, &cr); |
| 591 | pci_write_config_word(bus, PCI_COMMAND, 0x0000); |
| 592 | pci_write_config_word(bus, PCI_STATUS, 0xffff); |
| 593 | |
| 594 | /* |
| 595 | * Read the existing primary/secondary/subordinate bus |
| 596 | * number configuration. |
| 597 | */ |
| 598 | pci_read_config_dword(bus, PCI_PRIMARY_BUS, &buses); |
| 599 | |
| 600 | /* Configure the bus numbers for this bridge: the configuration |
| 601 | * transactions will not be propagated by the bridge if it is not |
| 602 | * correctly configured |
| 603 | */ |
| 604 | buses &= 0xff000000; |
| 605 | buses |= (((unsigned int) (bus->bus->secondary) << 0) | |
| 606 | ((unsigned int) (bus->secondary) << 8) | |
| 607 | ((unsigned int) (bus->subordinate) << 16)); |
| 608 | pci_write_config_dword(bus, PCI_PRIMARY_BUS, buses); |
| 609 | |
| 610 | /* Now we can scan all subordinate buses i.e. the bus hehind the bridge */ |
| 611 | max = pci_scan_bus(bus, max); |
| 612 | |
| 613 | /* We know the number of buses behind this bridge. Set the subordinate |
| 614 | * bus number to its real value |
| 615 | */ |
| 616 | bus->subordinate = max; |
| 617 | buses = (buses & 0xff00ffff) | |
| 618 | ((unsigned int) (bus->subordinate) << 16); |
| 619 | pci_write_config_dword(bus, PCI_PRIMARY_BUS, buses); |
| 620 | pci_write_config_word(bus, PCI_COMMAND, cr); |
| 621 | |
| 622 | return max; |
| 623 | } |
| 624 | |
| 625 | |
| 626 | static void pci_root_read_resources(struct device *bus) |
| 627 | { |
| 628 | int res = 0; |
| 629 | /* Initialize the system wide io space constraints */ |
| 630 | bus->resource[res].base = 0x400; |
| 631 | bus->resource[res].size = 0; |
| 632 | bus->resource[res].align = 0; |
| 633 | bus->resource[res].gran = 0; |
| 634 | bus->resource[res].limit = 0xffffUL; |
| 635 | bus->resource[res].flags = IORESOURCE_IO; |
| 636 | bus->resource[res].index = PCI_IO_BASE; |
| 637 | compute_allocate_resource(bus, &bus->resource[res], |
| 638 | IORESOURCE_IO, IORESOURCE_IO); |
| 639 | res++; |
| 640 | |
| 641 | /* Initialize the system wide memory resources constraints */ |
| 642 | bus->resource[res].base = 0; |
| 643 | bus->resource[res].size = 0; |
| 644 | bus->resource[res].align = 0; |
| 645 | bus->resource[res].gran = 0; |
| 646 | bus->resource[res].limit = 0xffffffffUL; |
| 647 | bus->resource[res].flags = IORESOURCE_MEM; |
| 648 | bus->resource[res].index = PCI_MEMORY_BASE; |
| 649 | compute_allocate_resource(bus, &bus->resource[res], |
| 650 | IORESOURCE_MEM, IORESOURCE_MEM); |
| 651 | res++; |
| 652 | |
| 653 | bus->resources = res; |
| 654 | } |
| 655 | static void pci_root_set_resources(struct device *bus) |
| 656 | { |
| 657 | compute_allocate_resource(bus, |
| 658 | &bus->resource[0], IORESOURCE_IO, IORESOURCE_IO); |
| 659 | compute_allocate_resource(bus, |
| 660 | &bus->resource[1], IORESOURCE_MEM, IORESOURCE_MEM); |
| 661 | assign_resources(bus); |
| 662 | } |
| 663 | |
| 664 | struct device_operations default_pci_ops_root = { |
| 665 | .read_resources = pci_root_read_resources, |
| 666 | .set_resources = pci_root_set_resources, |
| 667 | .init = 0, |
| 668 | .scan_bus = pci_scan_bus, |
| 669 | }; |
| 670 | |