device & commonlib: Update pci_scan_bus postcodes
The function pci_scan_bus had 3 post codes in it:
0x24 - beginning
0x25 - middle
0x55 - end
I got rid of the middle postcode and used 0x25 for the code signifying
the end of the function. I don't think all three are needed.
0x24 & 0x25 postcodes are currently also used in intel cache-as-ram
code. Those postcodes should be adjusted to avoid conflicting.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I19c9d5e256505b64234919a99f73a71efbbfdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 16c31ea..8651586 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -1423,7 +1423,7 @@
max_devfn=0xff;
}
- post_code(0x24);
+ post_code(POST_ENTER_PCI_SCAN_BUS);
if (pci_bus_only_one_child(bus))
max_devfn = MIN(max_devfn, 0x07);
@@ -1464,8 +1464,6 @@
}
}
- post_code(0x25);
-
/*
* Warn if any leftover static devices are found.
* There's probably a problem in devicetree.cb.
@@ -1516,7 +1514,7 @@
* side of any bridges that may be on this bus plus any devices.
* Return how far we've got finding sub-buses.
*/
- post_code(0x55);
+ post_code(POST_EXIT_PCI_SCAN_BUS);
}
typedef enum {