Angel Pons | 16c851f | 2020-04-05 13:21:38 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 2 | |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 3 | #include <assert.h> |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 4 | #include <bl31.h> |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 5 | #include <boardid.h> |
Kyösti Mälkki | 91c077f | 2021-11-03 18:34:14 +0200 | [diff] [blame] | 6 | #include <bootmode.h> |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 7 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 9 | #include <delay.h> |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 10 | #include <device/device.h> |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 11 | #include <device/i2c_simple.h> |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 12 | #include <ec/google/chromeec/ec.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 13 | #include <gpio.h> |
| 14 | #include <soc/clock.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 15 | #include <soc/display.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 16 | #include <soc/grf.h> |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 17 | #include <soc/mipi.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 18 | #include <soc/i2c.h> |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 19 | #include <soc/usb.h> |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 20 | #include <string.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 21 | |
Vadim Bendebury | 993dbe1 | 2016-05-22 15:53:37 -0700 | [diff] [blame] | 22 | #include "board.h" |
| 23 | |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 24 | #include <arm-trusted-firmware/include/export/plat/rockchip/common/plat_params_exp.h> |
| 25 | |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 26 | /* |
Caesar Wang | 212a026 | 2017-05-24 18:02:25 +0800 | [diff] [blame] | 27 | * We have to drive the stronger pull-up within 1 second of powering up the |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 28 | * touchpad to prevent its firmware from falling into recovery. Not on |
| 29 | * Scarlet-based boards. |
Caesar Wang | 212a026 | 2017-05-24 18:02:25 +0800 | [diff] [blame] | 30 | */ |
| 31 | static void configure_touchpad(void) |
| 32 | { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 33 | gpio_output(GPIO_TP_RST_L, 1); /* TP's I2C pull-up rail */ |
Caesar Wang | 212a026 | 2017-05-24 18:02:25 +0800 | [diff] [blame] | 34 | } |
| 35 | |
| 36 | /* |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 37 | * Wifi's PDN/RST line is pulled down by its (unpowered) voltage rails, but |
| 38 | * this reset pin is pulled up by default. Let's drive it low as early as we |
Philip Chen | a061820 | 2017-08-23 18:02:25 -0700 | [diff] [blame] | 39 | * can. This only applies to boards with Marvell 8997 WiFi. |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 40 | */ |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 41 | static void assert_wifi_reset(void) |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 42 | { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 43 | gpio_output(GPIO_WLAN_RST_L, 0); /* Assert WLAN_MODULE_RST# */ |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 44 | } |
| 45 | |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 46 | static void configure_emmc(void) |
| 47 | { |
| 48 | /* Host controller does not support programmable clock generator. |
| 49 | * If we don't do this setting, when we use phy to control the |
| 50 | * emmc clock(when clock exceed 50MHz), it will get wrong clock. |
| 51 | * |
| 52 | * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register. |
| 53 | * Please search "_CON11[7:0]" to locate register description. |
| 54 | */ |
| 55 | write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0)); |
| 56 | |
| 57 | rkclk_configure_emmc(); |
| 58 | } |
| 59 | |
Lin Huang | c9fea5c | 2016-08-30 15:34:42 -0700 | [diff] [blame] | 60 | static void register_apio_suspend(void) |
| 61 | { |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 62 | static struct bl_aux_param_rk_apio param_apio = { |
Lin Huang | c9fea5c | 2016-08-30 15:34:42 -0700 | [diff] [blame] | 63 | .h = { |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 64 | .type = BL_AUX_PARAM_RK_SUSPEND_APIO, |
Lin Huang | c9fea5c | 2016-08-30 15:34:42 -0700 | [diff] [blame] | 65 | }, |
| 66 | .apio = { |
| 67 | .apio1 = 1, |
| 68 | .apio2 = 1, |
| 69 | .apio3 = 1, |
| 70 | .apio4 = 1, |
| 71 | .apio5 = 1, |
| 72 | }, |
| 73 | }; |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 74 | register_bl31_aux_param(¶m_apio.h); |
Lin Huang | c9fea5c | 2016-08-30 15:34:42 -0700 | [diff] [blame] | 75 | } |
| 76 | |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 77 | static void register_gpio_suspend(void) |
| 78 | { |
| 79 | /* |
| 80 | * These three GPIO params are used to shut down the 1.5V, 1.8V and |
| 81 | * 3.3V power rails, which need to be shut down ordered by voltage, |
| 82 | * with highest voltage first. |
| 83 | * Since register_bl31() appends to the front of the list, we need to |
| 84 | * register them backwards, with 1.5V coming first. |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 85 | * 1.5V and 1.8V are EC-controlled on Scarlet derivatives, |
| 86 | * so we skip them. |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 87 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 88 | if (!CONFIG(GRU_BASEBOARD_SCARLET)) { |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 89 | static struct bl_aux_param_gpio param_p15_en = { |
| 90 | .h = { .type = BL_AUX_PARAM_RK_SUSPEND_GPIO }, |
| 91 | .gpio = { .polarity = ARM_TF_GPIO_LEVEL_LOW }, |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 92 | }; |
| 93 | param_p15_en.gpio.index = GPIO_P15V_EN.raw; |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 94 | register_bl31_aux_param(¶m_p15_en.h); |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 95 | |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 96 | static struct bl_aux_param_gpio param_p18_audio_en = { |
| 97 | .h = { .type = BL_AUX_PARAM_RK_SUSPEND_GPIO }, |
| 98 | .gpio = { .polarity = ARM_TF_GPIO_LEVEL_LOW }, |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 99 | }; |
| 100 | param_p18_audio_en.gpio.index = GPIO_P18V_AUDIO_PWREN.raw; |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 101 | register_bl31_aux_param(¶m_p18_audio_en.h); |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 102 | } |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 103 | |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 104 | static struct bl_aux_param_gpio param_p30_en = { |
| 105 | .h = { .type = BL_AUX_PARAM_RK_SUSPEND_GPIO }, |
| 106 | .gpio = { .polarity = ARM_TF_GPIO_LEVEL_LOW }, |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 107 | }; |
Julius Werner | 4ed8b30 | 2017-07-14 14:25:39 -0700 | [diff] [blame] | 108 | param_p30_en.gpio.index = GPIO_P30V_EN.raw; |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 109 | register_bl31_aux_param(¶m_p30_en.h); |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 110 | } |
| 111 | |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 112 | static void register_reset_to_bl31(void) |
| 113 | { |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 114 | static struct bl_aux_param_gpio param_reset = { |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 115 | .h = { |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 116 | .type = BL_AUX_PARAM_RK_RESET_GPIO, |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 117 | }, |
| 118 | .gpio = { |
| 119 | .polarity = 1, |
| 120 | }, |
| 121 | }; |
| 122 | |
| 123 | /* gru/kevin reset pin: gpio0b3 */ |
Julius Werner | 4ed8b30 | 2017-07-14 14:25:39 -0700 | [diff] [blame] | 124 | param_reset.gpio.index = GPIO_RESET.raw, |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 125 | |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 126 | register_bl31_aux_param(¶m_reset.h); |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 127 | } |
| 128 | |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 129 | static void register_poweroff_to_bl31(void) |
| 130 | { |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 131 | static struct bl_aux_param_gpio param_poweroff = { |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 132 | .h = { |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 133 | .type = BL_AUX_PARAM_RK_POWEROFF_GPIO, |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 134 | }, |
| 135 | .gpio = { |
| 136 | .polarity = 1, |
| 137 | }, |
| 138 | }; |
| 139 | |
| 140 | /* |
| 141 | * gru/kevin power off pin: gpio1a6, |
| 142 | * reuse with tsadc int pin, so iomux need set back to |
| 143 | * gpio in BL31 and depthcharge before you setting this gpio |
| 144 | */ |
Julius Werner | 4ed8b30 | 2017-07-14 14:25:39 -0700 | [diff] [blame] | 145 | param_poweroff.gpio.index = GPIO_POWEROFF.raw, |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 146 | |
Julius Werner | b3f24b4 | 2019-05-28 21:01:37 -0700 | [diff] [blame] | 147 | register_bl31_aux_param(¶m_poweroff.h); |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 148 | } |
| 149 | |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 150 | static void configure_sdmmc(void) |
| 151 | { |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 152 | gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */ |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 153 | |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 154 | /* set SDMMC_DET_L pin */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 155 | if (CONFIG(GRU_BASEBOARD_SCARLET)) |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 156 | /* |
| 157 | * do not have external pull up, so need to |
| 158 | * set this pin internal pull up |
| 159 | */ |
| 160 | gpio_input_pullup(GPIO(1, B, 3)); |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 161 | else |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 162 | gpio_input(GPIO(4, D, 0)); |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 163 | |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 164 | /* |
| 165 | * Keep sd card io domain 3v |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 166 | * In Scarlet derivatives, this GPIO set to high will get 3v, |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 167 | * With other board variants setting this GPIO low results in 3V. |
| 168 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 169 | if (CONFIG(GRU_BASEBOARD_SCARLET)) |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 170 | gpio_output(GPIO(2, D, 4), 1); |
| 171 | else |
| 172 | gpio_output(GPIO(2, D, 4), 0); |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 173 | |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 174 | gpio_input(GPIO(4, B, 0)); /* SDMMC0_D0 remove pull-up */ |
| 175 | gpio_input(GPIO(4, B, 1)); /* SDMMC0_D1 remove pull-up */ |
| 176 | gpio_input(GPIO(4, B, 2)); /* SDMMC0_D2 remove pull-up */ |
| 177 | gpio_input(GPIO(4, B, 3)); /* SDMMC0_D3 remove pull-up */ |
| 178 | gpio_input(GPIO(4, B, 4)); /* SDMMC0_CLK remove pull-down */ |
| 179 | gpio_input(GPIO(4, B, 5)); /* SDMMC0_CMD remove pull-up */ |
| 180 | |
Vadim Bendebury | ad6ee02 | 2016-05-12 16:54:00 +0800 | [diff] [blame] | 181 | write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0)); |
| 182 | |
| 183 | /* |
| 184 | * Set all outputs' drive strength to 8 mA. Group 4 bank B driver |
| 185 | * strength requires three bits per pin. Value of 2 written in that |
| 186 | * three bit field means '8 mA', as deduced from the kernel code. |
| 187 | * |
| 188 | * Thus the six pins involved in SDMMC interface require 18 bits to |
| 189 | * configure drive strength, but each 32 bit register provides only 16 |
| 190 | * bits for this setting, this covers 5 pins fully and one bit from |
| 191 | * the 6th pin. Two more bits spill over to the next register. This is |
| 192 | * described on page 378 of rk3399 TRM Version 0.3 Part 1. |
| 193 | */ |
| 194 | write32(&rk3399_grf->gpio4b_e01, |
| 195 | RK_CLRSETBITS(0xffff, |
| 196 | (2 << 0) | (2 << 3) | |
| 197 | (2 << 6) | (2 << 9) | (2 << 12))); |
| 198 | write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1)); |
| 199 | |
| 200 | /* And now set the multiplexor to enable SDMMC0. */ |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 201 | write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC); |
| 202 | } |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 203 | |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 204 | static void configure_codec(void) |
| 205 | { |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 206 | gpio_input(GPIO(3, D, 0)); /* I2S0_SCLK remove pull-up */ |
| 207 | gpio_input(GPIO(3, D, 1)); /* I2S0_RX remove pull-up */ |
| 208 | gpio_input(GPIO(3, D, 2)); /* I2S0_TX remove pull-up */ |
| 209 | gpio_input(GPIO(3, D, 3)); /* I2S0_SDI0 remove pull-up */ |
Julius Werner | 5598db2 | 2017-12-08 16:42:59 -0800 | [diff] [blame] | 210 | /* GPIOs 3_D4 - 3_D6 not used for I2S and are SKU ID pins on Scarlet. */ |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 211 | gpio_input(GPIO(3, D, 7)); /* I2S0_SDO0 remove pull-up */ |
| 212 | gpio_input(GPIO(4, A, 0)); /* I2S0_MCLK remove pull-up */ |
| 213 | |
Julius Werner | 5598db2 | 2017-12-08 16:42:59 -0800 | [diff] [blame] | 214 | write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0_SD0); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 215 | write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK); |
| 216 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 217 | if (!CONFIG(GRU_BASEBOARD_SCARLET)) |
Julius Werner | 1ab8c01 | 2017-11-03 15:23:09 -0700 | [diff] [blame] | 218 | gpio_output(GPIO_P18V_AUDIO_PWREN, 1); |
| 219 | gpio_output(GPIO_SPK_PA_EN, 0); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 220 | |
| 221 | rkclk_configure_i2s(12288000); |
| 222 | } |
| 223 | |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 224 | static void configure_display(void) |
| 225 | { |
Ege Mihmanli | beb0468 | 2017-11-20 11:54:02 -0800 | [diff] [blame] | 226 | /* |
| 227 | * Rainier is Scarlet-derived, but uses EDP so use board-specific |
| 228 | * config rather than baseboard. |
| 229 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 230 | if (CONFIG(BOARD_GOOGLE_SCARLET)) { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 231 | gpio_output(GPIO(4, D, 1), 0); /* DISPLAY_RST_L */ |
| 232 | gpio_output(GPIO(4, D, 3), 1); /* PPVARP_LCD */ |
| 233 | mdelay(10); |
| 234 | gpio_output(GPIO(4, D, 4), 1); /* PPVARN_LCD */ |
| 235 | mdelay(20 + 2); /* add 2ms for bias rise time */ |
| 236 | gpio_output(GPIO(4, D, 1), 1); /* DISPLAY_RST_L */ |
| 237 | mdelay(30); |
| 238 | } else { |
| 239 | /* set pinmux for edp HPD */ |
| 240 | gpio_input_pulldown(GPIO(4, C, 7)); |
| 241 | write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 242 | |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 243 | gpio_output(GPIO(4, D, 3), 1); /* P3.3V_DISP */ |
| 244 | } |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 245 | } |
| 246 | |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 247 | static void usb_power_cycle(int port) |
| 248 | { |
| 249 | if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK)) |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 250 | printk(BIOS_ERR, "Cannot force USB%d PD sink\n", port); |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 251 | |
| 252 | mdelay(10); /* Make sure USB stick is fully depowered. */ |
| 253 | |
| 254 | if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON)) |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 255 | printk(BIOS_ERR, "Cannot restore USB%d PD mode\n", port); |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 256 | } |
| 257 | |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 258 | static void setup_usb(int port) |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 259 | { |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 260 | /* Must be PHY0 or PHY1. */ |
| 261 | assert(port == 0 || port == 1); |
| 262 | |
William wu | 605a87c | 2017-01-09 19:02:39 +0800 | [diff] [blame] | 263 | /* |
| 264 | * A few magic PHY tuning values that improve eye diagram amplitude |
| 265 | * and make it extra sure we get reliable communication in firmware |
| 266 | * Set max ODT compensation voltage and current tuning reference. |
| 267 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 268 | write32(&rk3399_grf->usbphy_ctrl[port][3], RK_CLRSETBITS(0xfff, 0x2e3)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 269 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 270 | /* Set max pre-emphasis level on PHY0 and PHY1. */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 271 | write32(&rk3399_grf->usbphy_ctrl[port][12], |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 272 | RK_CLRSETBITS(0xffff, 0xa7)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 273 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 274 | /* |
William wu | ebbdd28 | 2017-01-23 20:54:22 +0800 | [diff] [blame] | 275 | * 1. Disable the pre-emphasize in eop state and chirp |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 276 | * state to avoid mis-trigger the disconnect detection |
| 277 | * and also avoid high-speed handshake fail for PHY0 |
| 278 | * and PHY1 consist of otg-port and host-port. |
William wu | ebbdd28 | 2017-01-23 20:54:22 +0800 | [diff] [blame] | 279 | * |
| 280 | * 2. Configure PHY0 and PHY1 otg-ports squelch detection |
| 281 | * threshold to 125mV (default is 150mV). |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 282 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 283 | write32(&rk3399_grf->usbphy_ctrl[port][0], |
William wu | ebbdd28 | 2017-01-23 20:54:22 +0800 | [diff] [blame] | 284 | RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13)); |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 285 | write32(&rk3399_grf->usbphy_ctrl[port][13], RK_CLRBITS(3 << 0)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 286 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 287 | /* |
| 288 | * ODT auto compensation bypass, and set max driver |
| 289 | * strength only for PHY0 and PHY1 otg-port. |
| 290 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 291 | write32(&rk3399_grf->usbphy_ctrl[port][2], |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 292 | RK_CLRSETBITS(0x7e << 4, 0x60 << 4)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 293 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 294 | /* |
| 295 | * ODT auto refresh bypass, and set the max bias current |
| 296 | * tuning reference only for PHY0 and PHY1 otg-port. |
| 297 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 298 | write32(&rk3399_grf->usbphy_ctrl[port][3], |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 299 | RK_CLRSETBITS(0x21c, 1 << 4)); |
William wu | 605a87c | 2017-01-09 19:02:39 +0800 | [diff] [blame] | 300 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 301 | /* |
| 302 | * ODT auto compensation bypass, and set default driver |
| 303 | * strength only for PHY0 and PHY1 host-port. |
| 304 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 305 | write32(&rk3399_grf->usbphy_ctrl[port][15], RK_SETBITS(1 << 10)); |
William wu | 605a87c | 2017-01-09 19:02:39 +0800 | [diff] [blame] | 306 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 307 | /* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 308 | write32(&rk3399_grf->usbphy_ctrl[port][16], RK_CLRBITS(1 << 9)); |
Julius Werner | 1c8491c | 2016-08-15 17:58:05 -0700 | [diff] [blame] | 309 | |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 310 | if (port == 0) |
| 311 | setup_usb_otg0(); |
| 312 | else |
| 313 | setup_usb_otg1(); |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 314 | |
| 315 | /* |
| 316 | * Need to power-cycle USB ports for use in firmware, since some devices |
| 317 | * can't fall back to USB 2.0 after they saw SuperSpeed terminations. |
| 318 | * This takes about a dozen milliseconds, so only do it in boot modes |
| 319 | * that have firmware UI (which one could select USB boot from). |
| 320 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 321 | if (display_init_required()) |
| 322 | usb_power_cycle(port); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 323 | } |
| 324 | |
Elyes HAOUAS | d129d43 | 2018-05-04 20:23:33 +0200 | [diff] [blame] | 325 | static void mainboard_init(struct device *dev) |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 326 | { |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 327 | configure_sdmmc(); |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 328 | configure_emmc(); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 329 | configure_codec(); |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 330 | if (display_init_required()) |
| 331 | configure_display(); |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 332 | setup_usb(0); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 333 | if (CONFIG(GRU_HAS_WLAN_RESET)) |
Philip Chen | a061820 | 2017-08-23 18:02:25 -0700 | [diff] [blame] | 334 | assert_wifi_reset(); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 335 | if (!CONFIG(GRU_BASEBOARD_SCARLET)) { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 336 | configure_touchpad(); /* Scarlet: works differently */ |
| 337 | setup_usb(1); /* Scarlet: only one USB port */ |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 338 | } |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 339 | register_gpio_suspend(); |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 340 | register_reset_to_bl31(); |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 341 | register_poweroff_to_bl31(); |
Lin Huang | c9fea5c | 2016-08-30 15:34:42 -0700 | [diff] [blame] | 342 | register_apio_suspend(); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 343 | } |
| 344 | |
Philip Chen | a304b69 | 2017-04-06 10:17:08 -0700 | [diff] [blame] | 345 | static void prepare_backlight_i2c(void) |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 346 | { |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 347 | gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull_up */ |
| 348 | gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull_up */ |
| 349 | |
| 350 | i2c_init(0, 100*KHz); |
| 351 | |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 352 | write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); |
| 353 | write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | void mainboard_power_on_backlight(void) |
| 357 | { |
Lin Huang | 18617bf | 2017-11-20 14:57:22 +0800 | [diff] [blame] | 358 | gpio_output(GPIO_BL_EN, 1); /* BL_EN */ |
| 359 | |
| 360 | /* Configure as output GPIO, to be toggled by payload. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 361 | if (CONFIG(GRU_BASEBOARD_SCARLET)) |
Lin Huang | 18617bf | 2017-11-20 14:57:22 +0800 | [diff] [blame] | 362 | gpio_output(GPIO_BACKLIGHT, 0); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 363 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 364 | if (CONFIG(BOARD_GOOGLE_GRU)) |
Philip Chen | a304b69 | 2017-04-06 10:17:08 -0700 | [diff] [blame] | 365 | prepare_backlight_i2c(); |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 366 | } |
| 367 | |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 368 | static struct panel_init_command innolux_p097pfg_init_cmds[] = { |
| 369 | /* page 0 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 370 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00), |
| 371 | MIPI_INIT_CMD(0xB1, 0xE8, 0x11), |
| 372 | MIPI_INIT_CMD(0xB2, 0x25, 0x02), |
| 373 | MIPI_INIT_CMD(0xB5, 0x08, 0x00), |
| 374 | MIPI_INIT_CMD(0xBC, 0x0F, 0x00), |
| 375 | MIPI_INIT_CMD(0xB8, 0x03, 0x06, 0x00, 0x00), |
| 376 | MIPI_INIT_CMD(0xBD, 0x01, 0x90, 0x14, 0x14), |
| 377 | MIPI_INIT_CMD(0x6F, 0x01), |
| 378 | MIPI_INIT_CMD(0xC0, 0x03), |
| 379 | MIPI_INIT_CMD(0x6F, 0x02), |
| 380 | MIPI_INIT_CMD(0xC1, 0x0D), |
| 381 | MIPI_INIT_CMD(0xD9, 0x01, 0x09, 0x70), |
| 382 | MIPI_INIT_CMD(0xC5, 0x12, 0x21, 0x00), |
| 383 | MIPI_INIT_CMD(0xBB, 0x93, 0x93), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 384 | |
| 385 | /* page 1 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 386 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01), |
| 387 | MIPI_INIT_CMD(0xB3, 0x3C, 0x3C), |
| 388 | MIPI_INIT_CMD(0xB4, 0x0F, 0x0F), |
| 389 | MIPI_INIT_CMD(0xB9, 0x45, 0x45), |
| 390 | MIPI_INIT_CMD(0xBA, 0x14, 0x14), |
| 391 | MIPI_INIT_CMD(0xCA, 0x02), |
| 392 | MIPI_INIT_CMD(0xCE, 0x04), |
| 393 | MIPI_INIT_CMD(0xC3, 0x9B, 0x9B), |
| 394 | MIPI_INIT_CMD(0xD8, 0xC0, 0x03), |
| 395 | MIPI_INIT_CMD(0xBC, 0x82, 0x01), |
| 396 | MIPI_INIT_CMD(0xBD, 0x9E, 0x01), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 397 | |
| 398 | /* page 2 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 399 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02), |
| 400 | MIPI_INIT_CMD(0xB0, 0x82), |
| 401 | MIPI_INIT_CMD(0xD1, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x82, 0x00, 0xA5, |
| 402 | 0x00, 0xC1, 0x00, 0xEA, 0x01, 0x0D, 0x01, 0x40), |
| 403 | MIPI_INIT_CMD(0xD2, 0x01, 0x6A, 0x01, 0xA8, 0x01, 0xDC, 0x02, 0x29, |
| 404 | 0x02, 0x67, 0x02, 0x68, 0x02, 0xA8, 0x02, 0xF0), |
| 405 | MIPI_INIT_CMD(0xD3, 0x03, 0x19, 0x03, 0x49, 0x03, 0x67, 0x03, 0x8C, |
| 406 | 0x03, 0xA6, 0x03, 0xC7, 0x03, 0xDE, 0x03, 0xEC), |
| 407 | MIPI_INIT_CMD(0xD4, 0x03, 0xFF, 0x03, 0xFF), |
| 408 | MIPI_INIT_CMD(0xE0, 0x00, 0x00, 0x00, 0x86, 0x00, 0xC5, 0x00, 0xE5, |
| 409 | 0x00, 0xFF, 0x01, 0x26, 0x01, 0x45, 0x01, 0x75), |
| 410 | MIPI_INIT_CMD(0xE1, 0x01, 0x9C, 0x01, 0xD5, 0x02, 0x05, 0x02, 0x4D, |
| 411 | 0x02, 0x86, 0x02, 0x87, 0x02, 0xC3, 0x03, 0x03), |
| 412 | MIPI_INIT_CMD(0xE2, 0x03, 0x2A, 0x03, 0x56, 0x03, 0x72, 0x03, 0x94, |
| 413 | 0x03, 0xAC, 0x03, 0xCB, 0x03, 0xE0, 0x03, 0xED), |
| 414 | MIPI_INIT_CMD(0xE3, 0x03, 0xFF, 0x03, 0xFF), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 415 | |
| 416 | /* page 3 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 417 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03), |
| 418 | MIPI_INIT_CMD(0xB0, 0x00, 0x00, 0x00, 0x00), |
| 419 | MIPI_INIT_CMD(0xB1, 0x00, 0x00, 0x00, 0x00), |
| 420 | MIPI_INIT_CMD(0xB2, 0x00, 0x00, 0x06, 0x04, 0x01, 0x40, 0x85), |
| 421 | MIPI_INIT_CMD(0xB3, 0x10, 0x07, 0xFC, 0x04, 0x01, 0x40, 0x80), |
| 422 | MIPI_INIT_CMD(0xB6, 0xF0, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, |
| 423 | 0x40, 0x80), |
| 424 | MIPI_INIT_CMD(0xBA, 0xC5, 0x07, 0x00, 0x04, 0x11, 0x25, 0x8C), |
| 425 | MIPI_INIT_CMD(0xBB, 0xC5, 0x07, 0x00, 0x03, 0x11, 0x25, 0x8C), |
| 426 | MIPI_INIT_CMD(0xC0, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x80), |
| 427 | MIPI_INIT_CMD(0xC1, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x80), |
| 428 | MIPI_INIT_CMD(0xC4, 0x00, 0x00), |
| 429 | MIPI_INIT_CMD(0xEF, 0x41), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 430 | |
| 431 | /* page 4 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 432 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04), |
| 433 | MIPI_INIT_CMD(0xEC, 0x4C), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 434 | |
| 435 | /* page 5 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 436 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05), |
| 437 | MIPI_INIT_CMD(0xB0, 0x13, 0x03, 0x03, 0x01), |
| 438 | MIPI_INIT_CMD(0xB1, 0x30, 0x00), |
| 439 | MIPI_INIT_CMD(0xB2, 0x02, 0x02, 0x00), |
| 440 | MIPI_INIT_CMD(0xB3, 0x82, 0x23, 0x82, 0x9D), |
| 441 | MIPI_INIT_CMD(0xB4, 0xC5, 0x75, 0x24, 0x57), |
| 442 | MIPI_INIT_CMD(0xB5, 0x00, 0xD4, 0x72, 0x11, 0x11, 0xAB, 0x0A), |
| 443 | MIPI_INIT_CMD(0xB6, 0x00, 0x00, 0xD5, 0x72, 0x24, 0x56), |
| 444 | MIPI_INIT_CMD(0xB7, 0x5C, 0xDC, 0x5C, 0x5C), |
| 445 | MIPI_INIT_CMD(0xB9, 0x0C, 0x00, 0x00, 0x01, 0x00), |
| 446 | MIPI_INIT_CMD(0xC0, 0x75, 0x11, 0x11, 0x54, 0x05), |
| 447 | MIPI_INIT_CMD(0xC6, 0x00, 0x00, 0x00, 0x00), |
| 448 | MIPI_INIT_CMD(0xD0, 0x00, 0x48, 0x08, 0x00, 0x00), |
| 449 | MIPI_INIT_CMD(0xD1, 0x00, 0x48, 0x09, 0x00, 0x00), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 450 | |
| 451 | /* page 6 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 452 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06), |
| 453 | MIPI_INIT_CMD(0xB0, 0x02, 0x32, 0x32, 0x08, 0x2F), |
| 454 | MIPI_INIT_CMD(0xB1, 0x2E, 0x15, 0x14, 0x13, 0x12), |
| 455 | MIPI_INIT_CMD(0xB2, 0x11, 0x10, 0x00, 0x3D, 0x3D), |
| 456 | MIPI_INIT_CMD(0xB3, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D), |
| 457 | MIPI_INIT_CMD(0xB4, 0x3D, 0x32), |
| 458 | MIPI_INIT_CMD(0xB5, 0x03, 0x32, 0x32, 0x09, 0x2F), |
| 459 | MIPI_INIT_CMD(0xB6, 0x2E, 0x1B, 0x1A, 0x19, 0x18), |
| 460 | MIPI_INIT_CMD(0xB7, 0x17, 0x16, 0x01, 0x3D, 0x3D), |
| 461 | MIPI_INIT_CMD(0xB8, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D), |
| 462 | MIPI_INIT_CMD(0xB9, 0x3D, 0x32), |
| 463 | MIPI_INIT_CMD(0xC0, 0x01, 0x32, 0x32, 0x09, 0x2F), |
| 464 | MIPI_INIT_CMD(0xC1, 0x2E, 0x1A, 0x1B, 0x16, 0x17), |
| 465 | MIPI_INIT_CMD(0xC2, 0x18, 0x19, 0x03, 0x3D, 0x3D), |
| 466 | MIPI_INIT_CMD(0xC3, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D), |
| 467 | MIPI_INIT_CMD(0xC4, 0x3D, 0x32), |
| 468 | MIPI_INIT_CMD(0xC5, 0x00, 0x32, 0x32, 0x08, 0x2F), |
| 469 | MIPI_INIT_CMD(0xC6, 0x2E, 0x14, 0x15, 0x10, 0x11), |
| 470 | MIPI_INIT_CMD(0xC7, 0x12, 0x13, 0x02, 0x3D, 0x3D), |
| 471 | MIPI_INIT_CMD(0xC8, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D), |
| 472 | MIPI_INIT_CMD(0xC9, 0x3D, 0x32), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 473 | |
| 474 | {}, |
| 475 | }; |
| 476 | |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 477 | static struct panel_init_command kd097d04_init_commands[] = { |
| 478 | /* voltage setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 479 | MIPI_INIT_CMD(0xB0, 0x00), |
| 480 | MIPI_INIT_CMD(0xB2, 0x02), |
| 481 | MIPI_INIT_CMD(0xB3, 0x11), |
| 482 | MIPI_INIT_CMD(0xB4, 0x00), |
| 483 | MIPI_INIT_CMD(0xB6, 0x80), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 484 | /* VCOM disable */ |
Brian Norris | cc761e8 | 2018-03-07 13:11:47 -0800 | [diff] [blame] | 485 | MIPI_INIT_CMD(0xB7, 0x02), |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 486 | MIPI_INIT_CMD(0xB8, 0x80), |
| 487 | MIPI_INIT_CMD(0xBA, 0x43), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 488 | /* VCOM setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 489 | MIPI_INIT_CMD(0xBB, 0x53), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 490 | /* VSP setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 491 | MIPI_INIT_CMD(0xBC, 0x0A), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 492 | /* VSN setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 493 | MIPI_INIT_CMD(0xBD, 0x4A), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 494 | /* VGH setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 495 | MIPI_INIT_CMD(0xBE, 0x2F), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 496 | /* VGL setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 497 | MIPI_INIT_CMD(0xBF, 0x1A), |
| 498 | MIPI_INIT_CMD(0xF0, 0x39), |
Brian Norris | cc761e8 | 2018-03-07 13:11:47 -0800 | [diff] [blame] | 499 | MIPI_INIT_CMD(0xF1, 0x22), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 500 | /* Gamma setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 501 | MIPI_INIT_CMD(0xB0, 0x02), |
| 502 | MIPI_INIT_CMD(0xC0, 0x00), |
| 503 | MIPI_INIT_CMD(0xC1, 0x01), |
| 504 | MIPI_INIT_CMD(0xC2, 0x0B), |
| 505 | MIPI_INIT_CMD(0xC3, 0x15), |
| 506 | MIPI_INIT_CMD(0xC4, 0x22), |
| 507 | MIPI_INIT_CMD(0xC5, 0x11), |
| 508 | MIPI_INIT_CMD(0xC6, 0x15), |
| 509 | MIPI_INIT_CMD(0xC7, 0x19), |
| 510 | MIPI_INIT_CMD(0xC8, 0x1A), |
| 511 | MIPI_INIT_CMD(0xC9, 0x16), |
| 512 | MIPI_INIT_CMD(0xCA, 0x18), |
| 513 | MIPI_INIT_CMD(0xCB, 0x13), |
| 514 | MIPI_INIT_CMD(0xCC, 0x18), |
| 515 | MIPI_INIT_CMD(0xCD, 0x13), |
| 516 | MIPI_INIT_CMD(0xCE, 0x1C), |
| 517 | MIPI_INIT_CMD(0xCF, 0x19), |
| 518 | MIPI_INIT_CMD(0xD0, 0x21), |
| 519 | MIPI_INIT_CMD(0xD1, 0x2C), |
| 520 | MIPI_INIT_CMD(0xD2, 0x2F), |
| 521 | MIPI_INIT_CMD(0xD3, 0x30), |
| 522 | MIPI_INIT_CMD(0xD4, 0x19), |
| 523 | MIPI_INIT_CMD(0xD5, 0x1F), |
| 524 | MIPI_INIT_CMD(0xD6, 0x00), |
| 525 | MIPI_INIT_CMD(0xD7, 0x01), |
| 526 | MIPI_INIT_CMD(0xD8, 0x0B), |
| 527 | MIPI_INIT_CMD(0xD9, 0x15), |
| 528 | MIPI_INIT_CMD(0xDA, 0x22), |
| 529 | MIPI_INIT_CMD(0xDB, 0x11), |
| 530 | MIPI_INIT_CMD(0xDC, 0x15), |
| 531 | MIPI_INIT_CMD(0xDD, 0x19), |
| 532 | MIPI_INIT_CMD(0xDE, 0x1A), |
| 533 | MIPI_INIT_CMD(0xDF, 0x16), |
| 534 | MIPI_INIT_CMD(0xE0, 0x18), |
| 535 | MIPI_INIT_CMD(0xE1, 0x13), |
| 536 | MIPI_INIT_CMD(0xE2, 0x18), |
| 537 | MIPI_INIT_CMD(0xE3, 0x13), |
| 538 | MIPI_INIT_CMD(0xE4, 0x1C), |
| 539 | MIPI_INIT_CMD(0xE5, 0x19), |
| 540 | MIPI_INIT_CMD(0xE6, 0x21), |
| 541 | MIPI_INIT_CMD(0xE7, 0x2C), |
| 542 | MIPI_INIT_CMD(0xE8, 0x2F), |
| 543 | MIPI_INIT_CMD(0xE9, 0x30), |
| 544 | MIPI_INIT_CMD(0xEA, 0x19), |
| 545 | MIPI_INIT_CMD(0xEB, 0x1F), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 546 | /* GOA MUX setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 547 | MIPI_INIT_CMD(0xB0, 0x01), |
| 548 | MIPI_INIT_CMD(0xC0, 0x10), |
| 549 | MIPI_INIT_CMD(0xC1, 0x0F), |
| 550 | MIPI_INIT_CMD(0xC2, 0x0E), |
| 551 | MIPI_INIT_CMD(0xC3, 0x0D), |
| 552 | MIPI_INIT_CMD(0xC4, 0x0C), |
| 553 | MIPI_INIT_CMD(0xC5, 0x0B), |
| 554 | MIPI_INIT_CMD(0xC6, 0x0A), |
| 555 | MIPI_INIT_CMD(0xC7, 0x09), |
| 556 | MIPI_INIT_CMD(0xC8, 0x08), |
| 557 | MIPI_INIT_CMD(0xC9, 0x07), |
| 558 | MIPI_INIT_CMD(0xCA, 0x06), |
| 559 | MIPI_INIT_CMD(0xCB, 0x05), |
| 560 | MIPI_INIT_CMD(0xCC, 0x00), |
| 561 | MIPI_INIT_CMD(0xCD, 0x01), |
| 562 | MIPI_INIT_CMD(0xCE, 0x02), |
| 563 | MIPI_INIT_CMD(0xCF, 0x03), |
| 564 | MIPI_INIT_CMD(0xD0, 0x04), |
| 565 | MIPI_INIT_CMD(0xD6, 0x10), |
| 566 | MIPI_INIT_CMD(0xD7, 0x0F), |
| 567 | MIPI_INIT_CMD(0xD8, 0x0E), |
| 568 | MIPI_INIT_CMD(0xD9, 0x0D), |
| 569 | MIPI_INIT_CMD(0xDA, 0x0C), |
| 570 | MIPI_INIT_CMD(0xDB, 0x0B), |
| 571 | MIPI_INIT_CMD(0xDC, 0x0A), |
| 572 | MIPI_INIT_CMD(0xDD, 0x09), |
| 573 | MIPI_INIT_CMD(0xDE, 0x08), |
| 574 | MIPI_INIT_CMD(0xDF, 0x07), |
| 575 | MIPI_INIT_CMD(0xE0, 0x06), |
| 576 | MIPI_INIT_CMD(0xE1, 0x05), |
| 577 | MIPI_INIT_CMD(0xE2, 0x00), |
| 578 | MIPI_INIT_CMD(0xE3, 0x01), |
| 579 | MIPI_INIT_CMD(0xE4, 0x02), |
| 580 | MIPI_INIT_CMD(0xE5, 0x03), |
| 581 | MIPI_INIT_CMD(0xE6, 0x04), |
| 582 | MIPI_INIT_CMD(0xE7, 0x00), |
| 583 | MIPI_INIT_CMD(0xEC, 0xC0), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 584 | /* GOA timing setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 585 | MIPI_INIT_CMD(0xB0, 0x03), |
| 586 | MIPI_INIT_CMD(0xC0, 0x01), |
| 587 | MIPI_INIT_CMD(0xC2, 0x6F), |
| 588 | MIPI_INIT_CMD(0xC3, 0x6F), |
| 589 | MIPI_INIT_CMD(0xC5, 0x36), |
| 590 | MIPI_INIT_CMD(0xC8, 0x08), |
| 591 | MIPI_INIT_CMD(0xC9, 0x04), |
| 592 | MIPI_INIT_CMD(0xCA, 0x41), |
| 593 | MIPI_INIT_CMD(0xCC, 0x43), |
| 594 | MIPI_INIT_CMD(0xCF, 0x60), |
| 595 | MIPI_INIT_CMD(0xD2, 0x04), |
| 596 | MIPI_INIT_CMD(0xD3, 0x04), |
| 597 | MIPI_INIT_CMD(0xD4, 0x03), |
| 598 | MIPI_INIT_CMD(0xD5, 0x02), |
| 599 | MIPI_INIT_CMD(0xD6, 0x01), |
| 600 | MIPI_INIT_CMD(0xD7, 0x00), |
| 601 | MIPI_INIT_CMD(0xDB, 0x01), |
| 602 | MIPI_INIT_CMD(0xDE, 0x36), |
| 603 | MIPI_INIT_CMD(0xE6, 0x6F), |
| 604 | MIPI_INIT_CMD(0xE7, 0x6F), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 605 | /* GOE setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 606 | MIPI_INIT_CMD(0xB0, 0x06), |
| 607 | MIPI_INIT_CMD(0xB8, 0xA5), |
| 608 | MIPI_INIT_CMD(0xC0, 0xA5), |
| 609 | MIPI_INIT_CMD(0xD5, 0x3F), |
| 610 | {}, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 611 | }; |
| 612 | |
| 613 | const struct mipi_panel_data kd097d04_panel = { |
| 614 | .mipi_num = 2, |
| 615 | .format = MIPI_DSI_FMT_RGB888, |
| 616 | .lanes = 8, |
| 617 | .display_on_udelay = 120000, |
| 618 | .video_mode_udelay = 5000, |
| 619 | .init_cmd = kd097d04_init_commands, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 620 | }; |
| 621 | |
| 622 | static const struct edid_mode kd097d04_edid_mode = { |
| 623 | .name = "1536x2048@60Hz", |
Lin Huang | ab21ab9 | 2017-12-06 10:18:10 +0800 | [diff] [blame] | 624 | .pixel_clock = 216000, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 625 | .refresh = 60, |
| 626 | .ha = 1536, |
Lin Huang | ab21ab9 | 2017-12-06 10:18:10 +0800 | [diff] [blame] | 627 | .hbl = 186, |
| 628 | .hso = 81, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 629 | .hspw = 24, |
| 630 | .va = 2048, |
Lin Huang | ab21ab9 | 2017-12-06 10:18:10 +0800 | [diff] [blame] | 631 | .vbl = 42, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 632 | .vso = 17, |
| 633 | .vspw = 2, |
| 634 | }; |
| 635 | |
Lin Huang | 318a03a | 2017-12-08 10:31:46 +0800 | [diff] [blame] | 636 | const struct mipi_panel_data inx097pfg_panel = { |
| 637 | .mipi_num = 2, |
| 638 | .format = MIPI_DSI_FMT_RGB888, |
| 639 | .lanes = 8, |
| 640 | .display_on_udelay = 120000, |
| 641 | .video_mode_udelay = 5000, |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 642 | .init_cmd = innolux_p097pfg_init_cmds, |
Lin Huang | 318a03a | 2017-12-08 10:31:46 +0800 | [diff] [blame] | 643 | }; |
| 644 | |
| 645 | static const struct edid_mode inx097pfg_edid_mode = { |
| 646 | .name = "1536x2048@60Hz", |
| 647 | .pixel_clock = 220000, |
| 648 | .refresh = 60, |
| 649 | .ha = 1536, |
| 650 | .hbl = 224, |
| 651 | .hso = 100, |
| 652 | .hspw = 24, |
| 653 | .va = 2048, |
| 654 | .vbl = 38, |
| 655 | .vso = 18, |
| 656 | .vspw = 2, |
| 657 | }; |
| 658 | |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 659 | const struct mipi_panel_data *mainboard_get_mipi_mode |
| 660 | (struct edid_mode *edid_mode) |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 661 | { |
Lin Huang | 318a03a | 2017-12-08 10:31:46 +0800 | [diff] [blame] | 662 | switch (sku_id()) { |
| 663 | case 0: |
| 664 | case 2: |
| 665 | case 4: |
| 666 | case 6: |
| 667 | memcpy(edid_mode, &inx097pfg_edid_mode, |
| 668 | sizeof(struct edid_mode)); |
| 669 | return &inx097pfg_panel; |
| 670 | case 1: |
| 671 | case 3: |
| 672 | case 5: |
| 673 | case 7: |
| 674 | default: |
| 675 | memcpy(edid_mode, &kd097d04_edid_mode, |
| 676 | sizeof(struct edid_mode)); |
| 677 | return &kd097d04_panel; |
| 678 | } |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 679 | } |
| 680 | |
Elyes HAOUAS | d129d43 | 2018-05-04 20:23:33 +0200 | [diff] [blame] | 681 | static void mainboard_enable(struct device *dev) |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 682 | { |
| 683 | dev->ops->init = &mainboard_init; |
| 684 | } |
| 685 | |
| 686 | struct chip_operations mainboard_ops = { |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 687 | .enable_dev = mainboard_enable, |
| 688 | }; |