huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 17 | #include <assert.h> |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 18 | #include <boardid.h> |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 19 | #include <console/console.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 20 | #include <delay.h> |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 21 | #include <device/device.h> |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 22 | #include <device/i2c_simple.h> |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 23 | #include <ec/google/chromeec/ec.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 24 | #include <gpio.h> |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 25 | #include <soc/bl31_plat_params.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 26 | #include <soc/clock.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 27 | #include <soc/display.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 28 | #include <soc/grf.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 29 | #include <soc/i2c.h> |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 30 | #include <soc/usb.h> |
Simon Glass | bc679bc | 2016-06-19 16:09:21 -0600 | [diff] [blame] | 31 | #include <vendorcode/google/chromeos/chromeos.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 32 | |
Vadim Bendebury | 993dbe1 | 2016-05-22 15:53:37 -0700 | [diff] [blame] | 33 | #include "board.h" |
| 34 | |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 35 | /* |
Caesar Wang | 212a026 | 2017-05-24 18:02:25 +0800 | [diff] [blame] | 36 | * We have to drive the stronger pull-up within 1 second of powering up the |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 37 | * touchpad to prevent its firmware from falling into recovery. Not on |
| 38 | * Scarlet-based boards. |
Caesar Wang | 212a026 | 2017-05-24 18:02:25 +0800 | [diff] [blame] | 39 | */ |
| 40 | static void configure_touchpad(void) |
| 41 | { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 42 | gpio_output(GPIO_TP_RST_L, 1); /* TP's I2C pull-up rail */ |
Caesar Wang | 212a026 | 2017-05-24 18:02:25 +0800 | [diff] [blame] | 43 | } |
| 44 | |
| 45 | /* |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 46 | * Wifi's PDN/RST line is pulled down by its (unpowered) voltage rails, but |
| 47 | * this reset pin is pulled up by default. Let's drive it low as early as we |
Philip Chen | a061820 | 2017-08-23 18:02:25 -0700 | [diff] [blame] | 48 | * can. This only applies to boards with Marvell 8997 WiFi. |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 49 | */ |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 50 | static void assert_wifi_reset(void) |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 51 | { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 52 | gpio_output(GPIO_WLAN_RST_L, 0); /* Assert WLAN_MODULE_RST# */ |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 53 | } |
| 54 | |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 55 | static void configure_emmc(void) |
| 56 | { |
| 57 | /* Host controller does not support programmable clock generator. |
| 58 | * If we don't do this setting, when we use phy to control the |
| 59 | * emmc clock(when clock exceed 50MHz), it will get wrong clock. |
| 60 | * |
| 61 | * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register. |
| 62 | * Please search "_CON11[7:0]" to locate register description. |
| 63 | */ |
| 64 | write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0)); |
| 65 | |
| 66 | rkclk_configure_emmc(); |
| 67 | } |
| 68 | |
Lin Huang | c9fea5c | 2016-08-30 15:34:42 -0700 | [diff] [blame] | 69 | static void register_apio_suspend(void) |
| 70 | { |
| 71 | static struct bl31_apio_param param_apio = { |
| 72 | .h = { |
| 73 | .type = PARAM_SUSPEND_APIO, |
| 74 | }, |
| 75 | .apio = { |
| 76 | .apio1 = 1, |
| 77 | .apio2 = 1, |
| 78 | .apio3 = 1, |
| 79 | .apio4 = 1, |
| 80 | .apio5 = 1, |
| 81 | }, |
| 82 | }; |
| 83 | register_bl31_param(¶m_apio.h); |
| 84 | } |
| 85 | |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 86 | static void register_gpio_suspend(void) |
| 87 | { |
| 88 | /* |
| 89 | * These three GPIO params are used to shut down the 1.5V, 1.8V and |
| 90 | * 3.3V power rails, which need to be shut down ordered by voltage, |
| 91 | * with highest voltage first. |
| 92 | * Since register_bl31() appends to the front of the list, we need to |
| 93 | * register them backwards, with 1.5V coming first. |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 94 | * 1.5V and 1.8V are EC-controlled on Scarlet derivatives, |
| 95 | * so we skip them. |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 96 | */ |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 97 | if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 98 | static struct bl31_gpio_param param_p15_en = { |
| 99 | .h = { .type = PARAM_SUSPEND_GPIO }, |
| 100 | .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, |
| 101 | }; |
| 102 | param_p15_en.gpio.index = GPIO_P15V_EN.raw; |
| 103 | register_bl31_param(¶m_p15_en.h); |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 104 | |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 105 | static struct bl31_gpio_param param_p18_audio_en = { |
| 106 | .h = { .type = PARAM_SUSPEND_GPIO }, |
| 107 | .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, |
| 108 | }; |
| 109 | param_p18_audio_en.gpio.index = GPIO_P18V_AUDIO_PWREN.raw; |
| 110 | register_bl31_param(¶m_p18_audio_en.h); |
| 111 | } |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 112 | |
| 113 | static struct bl31_gpio_param param_p30_en = { |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 114 | .h = { .type = PARAM_SUSPEND_GPIO }, |
| 115 | .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 116 | }; |
Julius Werner | 4ed8b30 | 2017-07-14 14:25:39 -0700 | [diff] [blame] | 117 | param_p30_en.gpio.index = GPIO_P30V_EN.raw; |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 118 | register_bl31_param(¶m_p30_en.h); |
| 119 | } |
| 120 | |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 121 | static void register_reset_to_bl31(void) |
| 122 | { |
| 123 | static struct bl31_gpio_param param_reset = { |
| 124 | .h = { |
| 125 | .type = PARAM_RESET, |
| 126 | }, |
| 127 | .gpio = { |
| 128 | .polarity = 1, |
| 129 | }, |
| 130 | }; |
| 131 | |
| 132 | /* gru/kevin reset pin: gpio0b3 */ |
Julius Werner | 4ed8b30 | 2017-07-14 14:25:39 -0700 | [diff] [blame] | 133 | param_reset.gpio.index = GPIO_RESET.raw, |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 134 | |
| 135 | register_bl31_param(¶m_reset.h); |
| 136 | } |
| 137 | |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 138 | static void register_poweroff_to_bl31(void) |
| 139 | { |
| 140 | static struct bl31_gpio_param param_poweroff = { |
| 141 | .h = { |
| 142 | .type = PARAM_POWEROFF, |
| 143 | }, |
| 144 | .gpio = { |
| 145 | .polarity = 1, |
| 146 | }, |
| 147 | }; |
| 148 | |
| 149 | /* |
| 150 | * gru/kevin power off pin: gpio1a6, |
| 151 | * reuse with tsadc int pin, so iomux need set back to |
| 152 | * gpio in BL31 and depthcharge before you setting this gpio |
| 153 | */ |
Julius Werner | 4ed8b30 | 2017-07-14 14:25:39 -0700 | [diff] [blame] | 154 | param_poweroff.gpio.index = GPIO_POWEROFF.raw, |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 155 | |
| 156 | register_bl31_param(¶m_poweroff.h); |
| 157 | } |
| 158 | |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 159 | static void configure_sdmmc(void) |
| 160 | { |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 161 | gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */ |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 162 | |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 163 | /* set SDMMC_DET_L pin */ |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 164 | if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 165 | /* |
| 166 | * do not have external pull up, so need to |
| 167 | * set this pin internal pull up |
| 168 | */ |
| 169 | gpio_input_pullup(GPIO(1, B, 3)); |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 170 | else |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 171 | gpio_input(GPIO(4, D, 0)); |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 172 | |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 173 | /* |
| 174 | * Keep sd card io domain 3v |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 175 | * In Scarlet derivatives, this GPIO set to high will get 3v, |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 176 | * With other board variants setting this GPIO low results in 3V. |
| 177 | */ |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 178 | if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 179 | gpio_output(GPIO(2, D, 4), 1); |
| 180 | else |
| 181 | gpio_output(GPIO(2, D, 4), 0); |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 182 | |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 183 | gpio_input(GPIO(4, B, 0)); /* SDMMC0_D0 remove pull-up */ |
| 184 | gpio_input(GPIO(4, B, 1)); /* SDMMC0_D1 remove pull-up */ |
| 185 | gpio_input(GPIO(4, B, 2)); /* SDMMC0_D2 remove pull-up */ |
| 186 | gpio_input(GPIO(4, B, 3)); /* SDMMC0_D3 remove pull-up */ |
| 187 | gpio_input(GPIO(4, B, 4)); /* SDMMC0_CLK remove pull-down */ |
| 188 | gpio_input(GPIO(4, B, 5)); /* SDMMC0_CMD remove pull-up */ |
| 189 | |
Vadim Bendebury | ad6ee02 | 2016-05-12 16:54:00 +0800 | [diff] [blame] | 190 | write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0)); |
| 191 | |
| 192 | /* |
| 193 | * Set all outputs' drive strength to 8 mA. Group 4 bank B driver |
| 194 | * strength requires three bits per pin. Value of 2 written in that |
| 195 | * three bit field means '8 mA', as deduced from the kernel code. |
| 196 | * |
| 197 | * Thus the six pins involved in SDMMC interface require 18 bits to |
| 198 | * configure drive strength, but each 32 bit register provides only 16 |
| 199 | * bits for this setting, this covers 5 pins fully and one bit from |
| 200 | * the 6th pin. Two more bits spill over to the next register. This is |
| 201 | * described on page 378 of rk3399 TRM Version 0.3 Part 1. |
| 202 | */ |
| 203 | write32(&rk3399_grf->gpio4b_e01, |
| 204 | RK_CLRSETBITS(0xffff, |
| 205 | (2 << 0) | (2 << 3) | |
| 206 | (2 << 6) | (2 << 9) | (2 << 12))); |
| 207 | write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1)); |
| 208 | |
| 209 | /* And now set the multiplexor to enable SDMMC0. */ |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 210 | write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC); |
| 211 | } |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 212 | |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 213 | static void configure_codec(void) |
| 214 | { |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 215 | gpio_input(GPIO(3, D, 0)); /* I2S0_SCLK remove pull-up */ |
| 216 | gpio_input(GPIO(3, D, 1)); /* I2S0_RX remove pull-up */ |
| 217 | gpio_input(GPIO(3, D, 2)); /* I2S0_TX remove pull-up */ |
| 218 | gpio_input(GPIO(3, D, 3)); /* I2S0_SDI0 remove pull-up */ |
| 219 | gpio_input(GPIO(3, D, 4)); /* I2S0_SDI1 remove pull-up */ |
| 220 | /* GPIO3_D5 (I2S0_SDI2SDO2) not connected */ |
| 221 | gpio_input(GPIO(3, D, 6)); /* I2S0_SDO1 remove pull-up */ |
| 222 | gpio_input(GPIO(3, D, 7)); /* I2S0_SDO0 remove pull-up */ |
| 223 | gpio_input(GPIO(4, A, 0)); /* I2S0_MCLK remove pull-up */ |
| 224 | |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 225 | write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0); |
| 226 | write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK); |
| 227 | |
| 228 | /* AUDIO IO domain 1.8V voltage selection */ |
| 229 | write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1)); |
| 230 | |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 231 | if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) |
Julius Werner | 1ab8c01 | 2017-11-03 15:23:09 -0700 | [diff] [blame] | 232 | gpio_output(GPIO_P18V_AUDIO_PWREN, 1); |
| 233 | gpio_output(GPIO_SPK_PA_EN, 0); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 234 | |
| 235 | rkclk_configure_i2s(12288000); |
| 236 | } |
| 237 | |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 238 | static void configure_display(void) |
| 239 | { |
Ege Mihmanli | beb0468 | 2017-11-20 11:54:02 -0800 | [diff] [blame] | 240 | /* |
| 241 | * Rainier is Scarlet-derived, but uses EDP so use board-specific |
| 242 | * config rather than baseboard. |
| 243 | */ |
| 244 | if (IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 245 | gpio_output(GPIO(4, D, 1), 0); /* DISPLAY_RST_L */ |
| 246 | gpio_output(GPIO(4, D, 3), 1); /* PPVARP_LCD */ |
| 247 | mdelay(10); |
| 248 | gpio_output(GPIO(4, D, 4), 1); /* PPVARN_LCD */ |
| 249 | mdelay(20 + 2); /* add 2ms for bias rise time */ |
| 250 | gpio_output(GPIO(4, D, 1), 1); /* DISPLAY_RST_L */ |
| 251 | mdelay(30); |
| 252 | } else { |
| 253 | /* set pinmux for edp HPD */ |
| 254 | gpio_input_pulldown(GPIO(4, C, 7)); |
| 255 | write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 256 | |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 257 | gpio_output(GPIO(4, D, 3), 1); /* P3.3V_DISP */ |
| 258 | } |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 259 | } |
| 260 | |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 261 | static void usb_power_cycle(int port) |
| 262 | { |
| 263 | if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK)) |
| 264 | printk(BIOS_ERR, "ERROR: Cannot force USB%d PD sink\n", port); |
| 265 | |
| 266 | mdelay(10); /* Make sure USB stick is fully depowered. */ |
| 267 | |
| 268 | if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON)) |
| 269 | printk(BIOS_ERR, "ERROR: Cannot restore USB%d PD mode\n", port); |
| 270 | } |
| 271 | |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 272 | static void setup_usb(int port) |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 273 | { |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 274 | /* Must be PHY0 or PHY1. */ |
| 275 | assert(port == 0 || port == 1); |
| 276 | |
William wu | 605a87c | 2017-01-09 19:02:39 +0800 | [diff] [blame] | 277 | /* |
| 278 | * A few magic PHY tuning values that improve eye diagram amplitude |
| 279 | * and make it extra sure we get reliable communication in firmware |
| 280 | * Set max ODT compensation voltage and current tuning reference. |
| 281 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 282 | write32(&rk3399_grf->usbphy_ctrl[port][3], RK_CLRSETBITS(0xfff, 0x2e3)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 283 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 284 | /* Set max pre-emphasis level on PHY0 and PHY1. */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 285 | write32(&rk3399_grf->usbphy_ctrl[port][12], |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 286 | RK_CLRSETBITS(0xffff, 0xa7)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 287 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 288 | /* |
William wu | ebbdd28 | 2017-01-23 20:54:22 +0800 | [diff] [blame] | 289 | * 1. Disable the pre-emphasize in eop state and chirp |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 290 | * state to avoid mis-trigger the disconnect detection |
| 291 | * and also avoid high-speed handshake fail for PHY0 |
| 292 | * and PHY1 consist of otg-port and host-port. |
William wu | ebbdd28 | 2017-01-23 20:54:22 +0800 | [diff] [blame] | 293 | * |
| 294 | * 2. Configure PHY0 and PHY1 otg-ports squelch detection |
| 295 | * threshold to 125mV (default is 150mV). |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 296 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 297 | write32(&rk3399_grf->usbphy_ctrl[port][0], |
William wu | ebbdd28 | 2017-01-23 20:54:22 +0800 | [diff] [blame] | 298 | RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13)); |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 299 | write32(&rk3399_grf->usbphy_ctrl[port][13], RK_CLRBITS(3 << 0)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 300 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 301 | /* |
| 302 | * ODT auto compensation bypass, and set max driver |
| 303 | * strength only for PHY0 and PHY1 otg-port. |
| 304 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 305 | write32(&rk3399_grf->usbphy_ctrl[port][2], |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 306 | RK_CLRSETBITS(0x7e << 4, 0x60 << 4)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 307 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 308 | /* |
| 309 | * ODT auto refresh bypass, and set the max bias current |
| 310 | * tuning reference only for PHY0 and PHY1 otg-port. |
| 311 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 312 | write32(&rk3399_grf->usbphy_ctrl[port][3], |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 313 | RK_CLRSETBITS(0x21c, 1 << 4)); |
William wu | 605a87c | 2017-01-09 19:02:39 +0800 | [diff] [blame] | 314 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 315 | /* |
| 316 | * ODT auto compensation bypass, and set default driver |
| 317 | * strength only for PHY0 and PHY1 host-port. |
| 318 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 319 | write32(&rk3399_grf->usbphy_ctrl[port][15], RK_SETBITS(1 << 10)); |
William wu | 605a87c | 2017-01-09 19:02:39 +0800 | [diff] [blame] | 320 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 321 | /* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 322 | write32(&rk3399_grf->usbphy_ctrl[port][16], RK_CLRBITS(1 << 9)); |
Julius Werner | 1c8491c | 2016-08-15 17:58:05 -0700 | [diff] [blame] | 323 | |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 324 | if (port == 0) |
| 325 | setup_usb_otg0(); |
| 326 | else |
| 327 | setup_usb_otg1(); |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 328 | |
| 329 | /* |
| 330 | * Need to power-cycle USB ports for use in firmware, since some devices |
| 331 | * can't fall back to USB 2.0 after they saw SuperSpeed terminations. |
| 332 | * This takes about a dozen milliseconds, so only do it in boot modes |
| 333 | * that have firmware UI (which one could select USB boot from). |
| 334 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 335 | if (display_init_required()) |
| 336 | usb_power_cycle(port); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 337 | } |
| 338 | |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 339 | static void mainboard_init(device_t dev) |
| 340 | { |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 341 | configure_sdmmc(); |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 342 | configure_emmc(); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 343 | configure_codec(); |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 344 | if (display_init_required()) |
| 345 | configure_display(); |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 346 | setup_usb(0); |
Philip Chen | a061820 | 2017-08-23 18:02:25 -0700 | [diff] [blame] | 347 | if (IS_ENABLED(CONFIG_GRU_HAS_WLAN_RESET)) |
| 348 | assert_wifi_reset(); |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 349 | if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 350 | configure_touchpad(); /* Scarlet: works differently */ |
| 351 | setup_usb(1); /* Scarlet: only one USB port */ |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 352 | } |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 353 | register_gpio_suspend(); |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 354 | register_reset_to_bl31(); |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 355 | register_poweroff_to_bl31(); |
Lin Huang | c9fea5c | 2016-08-30 15:34:42 -0700 | [diff] [blame] | 356 | register_apio_suspend(); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 357 | } |
| 358 | |
Philip Chen | a304b69 | 2017-04-06 10:17:08 -0700 | [diff] [blame] | 359 | static void prepare_backlight_i2c(void) |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 360 | { |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 361 | gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull_up */ |
| 362 | gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull_up */ |
| 363 | |
| 364 | i2c_init(0, 100*KHz); |
| 365 | |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 366 | write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); |
| 367 | write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 368 | } |
| 369 | |
| 370 | void mainboard_power_on_backlight(void) |
| 371 | { |
Lin Huang | 18617bf | 2017-11-20 14:57:22 +0800 | [diff] [blame^] | 372 | gpio_output(GPIO_BL_EN, 1); /* BL_EN */ |
| 373 | |
| 374 | /* Configure as output GPIO, to be toggled by payload. */ |
| 375 | if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) |
| 376 | gpio_output(GPIO_BACKLIGHT, 0); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 377 | |
Philip Chen | a304b69 | 2017-04-06 10:17:08 -0700 | [diff] [blame] | 378 | if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) |
| 379 | prepare_backlight_i2c(); |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 380 | } |
| 381 | |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 382 | const struct mipi_panel_data *mainboard_get_mipi_mode(struct edid *edid) |
| 383 | { |
| 384 | return NULL; |
| 385 | } |
| 386 | |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 387 | static void mainboard_enable(device_t dev) |
| 388 | { |
| 389 | dev->ops->init = &mainboard_init; |
| 390 | } |
| 391 | |
| 392 | struct chip_operations mainboard_ops = { |
| 393 | .name = CONFIG_MAINBOARD_PART_NUMBER, |
| 394 | .enable_dev = mainboard_enable, |
| 395 | }; |