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huang lina6dbfb52016-03-02 18:38:40 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070017#include <boardid.h>
Lin Huangb497b482016-03-31 18:44:13 +080018#include <delay.h>
huang lina6dbfb52016-03-02 18:38:40 +080019#include <device/device.h>
Lin Huangb497b482016-03-31 18:44:13 +080020#include <device/i2c.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070021#include <gpio.h>
Lin Huang5a4be8a2016-05-17 15:45:53 +080022#include <soc/bl31_plat_params.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070023#include <soc/clock.h>
Lin Huangb497b482016-03-31 18:44:13 +080024#include <soc/display.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070025#include <soc/grf.h>
Lin Huangb497b482016-03-31 18:44:13 +080026#include <soc/i2c.h>
Liangfeng Wu76655cb2016-05-26 16:06:58 +080027#include <soc/usb.h>
Simon Glassbc679bc2016-06-19 16:09:21 -060028#include <vendorcode/google/chromeos/chromeos.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070029
Vadim Bendebury993dbe12016-05-22 15:53:37 -070030#include "board.h"
31
Lin Huang2f7ed8d2016-04-08 18:56:20 +080032static void configure_emmc(void)
33{
34 /* Host controller does not support programmable clock generator.
35 * If we don't do this setting, when we use phy to control the
36 * emmc clock(when clock exceed 50MHz), it will get wrong clock.
37 *
38 * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register.
39 * Please search "_CON11[7:0]" to locate register description.
40 */
41 write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
42
43 rkclk_configure_emmc();
44}
45
Lin Huangc9fea5c2016-08-30 15:34:42 -070046static void register_apio_suspend(void)
47{
48 static struct bl31_apio_param param_apio = {
49 .h = {
50 .type = PARAM_SUSPEND_APIO,
51 },
52 .apio = {
53 .apio1 = 1,
54 .apio2 = 1,
55 .apio3 = 1,
56 .apio4 = 1,
57 .apio5 = 1,
58 },
59 };
60 register_bl31_param(&param_apio.h);
61}
62
Lin Huang7d8ccfb2016-08-22 17:35:40 -070063static void register_gpio_suspend(void)
64{
65 /*
66 * These three GPIO params are used to shut down the 1.5V, 1.8V and
67 * 3.3V power rails, which need to be shut down ordered by voltage,
68 * with highest voltage first.
69 * Since register_bl31() appends to the front of the list, we need to
70 * register them backwards, with 1.5V coming first.
71 */
72 static struct bl31_gpio_param param_p15_en = {
73 .h = {
74 .type = PARAM_SUSPEND_GPIO,
75 },
76 .gpio = {
77 .polarity = BL31_GPIO_LEVEL_LOW,
78 },
79 };
80 param_p15_en.gpio.index = GET_GPIO_NUM(GPIO_P15V_EN);
81 register_bl31_param(&param_p15_en.h);
82
83 static struct bl31_gpio_param param_p18_audio_en = {
84 .h = {
85 .type = PARAM_SUSPEND_GPIO,
86 },
87 .gpio = {
88 .polarity = BL31_GPIO_LEVEL_LOW,
89 },
90 };
91 param_p18_audio_en.gpio.index = GET_GPIO_NUM(GPIO_P18V_AUDIO_PWREN);
92 register_bl31_param(&param_p18_audio_en.h);
93
94 static struct bl31_gpio_param param_p30_en = {
95 .h = {
96 .type = PARAM_SUSPEND_GPIO,
97 },
98 .gpio = {
99 .polarity = BL31_GPIO_LEVEL_LOW,
100 },
101 };
102 param_p30_en.gpio.index = GET_GPIO_NUM(GPIO_P30V_EN);
103 register_bl31_param(&param_p30_en.h);
104}
105
Lin Huang5a4be8a2016-05-17 15:45:53 +0800106static void register_reset_to_bl31(void)
107{
108 static struct bl31_gpio_param param_reset = {
109 .h = {
110 .type = PARAM_RESET,
111 },
112 .gpio = {
113 .polarity = 1,
114 },
115 };
116
117 /* gru/kevin reset pin: gpio0b3 */
118 param_reset.gpio.index = GET_GPIO_NUM(GPIO_RESET),
119
120 register_bl31_param(&param_reset.h);
121}
122
Lin Huang9a5c4fe2016-05-19 11:11:23 +0800123static void register_poweroff_to_bl31(void)
124{
125 static struct bl31_gpio_param param_poweroff = {
126 .h = {
127 .type = PARAM_POWEROFF,
128 },
129 .gpio = {
130 .polarity = 1,
131 },
132 };
133
134 /*
135 * gru/kevin power off pin: gpio1a6,
136 * reuse with tsadc int pin, so iomux need set back to
137 * gpio in BL31 and depthcharge before you setting this gpio
138 */
139 param_poweroff.gpio.index = GET_GPIO_NUM(GPIO_POWEROFF),
140
141 register_bl31_param(&param_poweroff.h);
142}
143
Vadim Bendebury1e80ab32016-03-28 00:44:54 -0700144static void configure_sdmmc(void)
145{
146 gpio_output(GPIO(4, D, 5), 1); /* SDMMC_PWR_EN */
147 gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */
Vadim Bendebury2832c412016-05-11 15:03:44 +0800148
149 /* SDMMC_DET_L is different on Kevin board revision 0. */
150 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && (board_id() == 0))
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -0700151 gpio_input(GPIO(4, D, 2));
Vadim Bendebury2832c412016-05-11 15:03:44 +0800152 else
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -0700153 gpio_input(GPIO(4, D, 0));
Vadim Bendebury2832c412016-05-11 15:03:44 +0800154
Vadim Bendebury1e80ab32016-03-28 00:44:54 -0700155 gpio_output(GPIO(2, D, 4), 0); /* Keep the max voltage */
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -0700156
Julius Werner7feb86b2016-09-02 11:25:56 -0700157 gpio_input(GPIO(4, B, 0)); /* SDMMC0_D0 remove pull-up */
158 gpio_input(GPIO(4, B, 1)); /* SDMMC0_D1 remove pull-up */
159 gpio_input(GPIO(4, B, 2)); /* SDMMC0_D2 remove pull-up */
160 gpio_input(GPIO(4, B, 3)); /* SDMMC0_D3 remove pull-up */
161 gpio_input(GPIO(4, B, 4)); /* SDMMC0_CLK remove pull-down */
162 gpio_input(GPIO(4, B, 5)); /* SDMMC0_CMD remove pull-up */
163
Vadim Bendeburyad6ee022016-05-12 16:54:00 +0800164 write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0));
165
166 /*
167 * Set all outputs' drive strength to 8 mA. Group 4 bank B driver
168 * strength requires three bits per pin. Value of 2 written in that
169 * three bit field means '8 mA', as deduced from the kernel code.
170 *
171 * Thus the six pins involved in SDMMC interface require 18 bits to
172 * configure drive strength, but each 32 bit register provides only 16
173 * bits for this setting, this covers 5 pins fully and one bit from
174 * the 6th pin. Two more bits spill over to the next register. This is
175 * described on page 378 of rk3399 TRM Version 0.3 Part 1.
176 */
177 write32(&rk3399_grf->gpio4b_e01,
178 RK_CLRSETBITS(0xffff,
179 (2 << 0) | (2 << 3) |
180 (2 << 6) | (2 << 9) | (2 << 12)));
181 write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1));
182
183 /* And now set the multiplexor to enable SDMMC0. */
Vadim Bendebury1e80ab32016-03-28 00:44:54 -0700184 write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC);
185}
huang lina6dbfb52016-03-02 18:38:40 +0800186
Xing Zheng96fbc312016-05-19 11:39:20 +0800187static void configure_codec(void)
188{
Julius Werner7feb86b2016-09-02 11:25:56 -0700189 gpio_input(GPIO(3, D, 0)); /* I2S0_SCLK remove pull-up */
190 gpio_input(GPIO(3, D, 1)); /* I2S0_RX remove pull-up */
191 gpio_input(GPIO(3, D, 2)); /* I2S0_TX remove pull-up */
192 gpio_input(GPIO(3, D, 3)); /* I2S0_SDI0 remove pull-up */
193 gpio_input(GPIO(3, D, 4)); /* I2S0_SDI1 remove pull-up */
194 /* GPIO3_D5 (I2S0_SDI2SDO2) not connected */
195 gpio_input(GPIO(3, D, 6)); /* I2S0_SDO1 remove pull-up */
196 gpio_input(GPIO(3, D, 7)); /* I2S0_SDO0 remove pull-up */
197 gpio_input(GPIO(4, A, 0)); /* I2S0_MCLK remove pull-up */
198
Xing Zheng96fbc312016-05-19 11:39:20 +0800199 write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0);
200 write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK);
201
202 /* AUDIO IO domain 1.8V voltage selection */
203 write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1));
204
205 /* CPU1_P1.8V_AUDIO_PWREN for P1.8_AUDIO */
206 gpio_output(GPIO(0, A, 2), 1);
207
208 /* set CPU1_SPK_PA_EN output */
209 gpio_output(GPIO(1, A, 2), 0);
210
211 rkclk_configure_i2s(12288000);
212}
213
Lin Huangb497b482016-03-31 18:44:13 +0800214static void configure_display(void)
215{
216 /* set pinmux for edp HPD*/
217 gpio_input_pulldown(GPIO(4, C, 7));
218 write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
219
220 gpio_output(GPIO(4, D, 3), 1); /* CPU3_EDP_VDDEN for P3.3V_DISP */
221}
222
Liangfeng Wu76655cb2016-05-26 16:06:58 +0800223static void setup_usb(void)
224{
Julius Werner1c8491c2016-08-15 17:58:05 -0700225 /* A few magic PHY tuning values that improve eye diagram amplitude
226 * and make it extra sure we get reliable communication in firmware. */
227 /* Set max ODT compensation voltage and current tuning reference. */
228 write32(&rk3399_grf->usbphy0_ctrl[3], 0x0fff02e3);
229 write32(&rk3399_grf->usbphy1_ctrl[3], 0x0fff02e3);
230 /* Set max pre-emphasis level, only on Kevin PHY0. */
231 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
232 write32(&rk3399_grf->usbphy0_ctrl[12], 0xffff00a7);
233
Julius Werner785ff1b2016-08-03 19:18:39 -0700234 setup_usb_otg0();
235 setup_usb_otg1();
Liangfeng Wu76655cb2016-05-26 16:06:58 +0800236}
237
huang lina6dbfb52016-03-02 18:38:40 +0800238static void mainboard_init(device_t dev)
239{
Vadim Bendebury1e80ab32016-03-28 00:44:54 -0700240 configure_sdmmc();
Lin Huang2f7ed8d2016-04-08 18:56:20 +0800241 configure_emmc();
Xing Zheng96fbc312016-05-19 11:39:20 +0800242 configure_codec();
Lin Huangb497b482016-03-31 18:44:13 +0800243 configure_display();
Liangfeng Wu76655cb2016-05-26 16:06:58 +0800244 setup_usb();
Lin Huang5a4be8a2016-05-17 15:45:53 +0800245 register_reset_to_bl31();
Lin Huang9a5c4fe2016-05-19 11:11:23 +0800246 register_poweroff_to_bl31();
Lin Huang7d8ccfb2016-08-22 17:35:40 -0700247 register_gpio_suspend();
Lin Huangc9fea5c2016-08-30 15:34:42 -0700248 register_apio_suspend();
Lin Huangb497b482016-03-31 18:44:13 +0800249}
250
251static void enable_backlight_booster(void)
252{
253 const struct {
254 uint8_t reg;
255 uint8_t value;
256 } i2c_writes[] = {
257 {1, 0x84},
258 {1, 0x85},
259 {0, 0x26}
260 };
261 int i;
262 const int booster_i2c_port = 0;
263 uint8_t i2c_buf[2];
264 struct i2c_seg i2c_command = { .read = 0, .chip = 0x2c,
265 .buf = i2c_buf, .len = sizeof(i2c_buf)
266 };
267
268 /*
269 * This function is called on Gru right after BL_EN is asserted. It
270 * takes time for the switcher chip to come online, let's wait a bit
271 * to let the voltage settle, so that the chip can be accessed.
272 */
273 udelay(1000);
274
Julius Werner7feb86b2016-09-02 11:25:56 -0700275 gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull_up */
276 gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull_up */
277
278 i2c_init(0, 100*KHz);
279
Lin Huangb497b482016-03-31 18:44:13 +0800280 write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA);
281 write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL);
Lin Huangb497b482016-03-31 18:44:13 +0800282
283 for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) {
284 i2c_buf[0] = i2c_writes[i].reg;
285 i2c_buf[1] = i2c_writes[i].value;
286 i2c_transfer(booster_i2c_port, &i2c_command, 1);
287 }
288}
289
290void mainboard_power_on_backlight(void)
291{
292 gpio_output(GPIO(1, C, 1), 1); /* BL_EN */
293
Julius Werner5e6771b2016-07-29 16:15:04 -0700294 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() == 0)
Lin Huangb497b482016-03-31 18:44:13 +0800295 enable_backlight_booster();
huang lina6dbfb52016-03-02 18:38:40 +0800296}
297
298static void mainboard_enable(device_t dev)
299{
300 dev->ops->init = &mainboard_init;
301}
302
303struct chip_operations mainboard_ops = {
304 .name = CONFIG_MAINBOARD_PART_NUMBER,
305 .enable_dev = mainboard_enable,
306};