huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 17 | #include <boardid.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 18 | #include <delay.h> |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 19 | #include <device/device.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 20 | #include <device/i2c.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 21 | #include <gpio.h> |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame^] | 22 | #include <soc/bl31_plat_params.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 23 | #include <soc/clock.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 24 | #include <soc/display.h> |
Shunqian Zheng | 462e141 | 2016-05-02 10:27:30 +0800 | [diff] [blame] | 25 | #include <soc/emmc.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 26 | #include <soc/grf.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 27 | #include <soc/i2c.h> |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 28 | #include <soc/usb.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 29 | |
Vadim Bendebury | 993dbe1 | 2016-05-22 15:53:37 -0700 | [diff] [blame] | 30 | #include "board.h" |
| 31 | |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 32 | static void configure_emmc(void) |
| 33 | { |
| 34 | /* Host controller does not support programmable clock generator. |
| 35 | * If we don't do this setting, when we use phy to control the |
| 36 | * emmc clock(when clock exceed 50MHz), it will get wrong clock. |
| 37 | * |
| 38 | * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register. |
| 39 | * Please search "_CON11[7:0]" to locate register description. |
| 40 | */ |
| 41 | write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0)); |
| 42 | |
| 43 | rkclk_configure_emmc(); |
Shunqian Zheng | 462e141 | 2016-05-02 10:27:30 +0800 | [diff] [blame] | 44 | |
| 45 | enable_emmc_clk(); |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 46 | } |
| 47 | |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame^] | 48 | static void register_reset_to_bl31(void) |
| 49 | { |
| 50 | static struct bl31_gpio_param param_reset = { |
| 51 | .h = { |
| 52 | .type = PARAM_RESET, |
| 53 | }, |
| 54 | .gpio = { |
| 55 | .polarity = 1, |
| 56 | }, |
| 57 | }; |
| 58 | |
| 59 | /* gru/kevin reset pin: gpio0b3 */ |
| 60 | param_reset.gpio.index = GET_GPIO_NUM(GPIO_RESET), |
| 61 | |
| 62 | register_bl31_param(¶m_reset.h); |
| 63 | } |
| 64 | |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 65 | static void configure_sdmmc(void) |
| 66 | { |
| 67 | gpio_output(GPIO(4, D, 5), 1); /* SDMMC_PWR_EN */ |
| 68 | gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */ |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 69 | |
| 70 | /* SDMMC_DET_L is different on Kevin board revision 0. */ |
| 71 | if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && (board_id() == 0)) |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 72 | gpio_input(GPIO(4, D, 2)); |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 73 | else |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 74 | gpio_input(GPIO(4, D, 0)); |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 75 | |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 76 | gpio_output(GPIO(2, D, 4), 0); /* Keep the max voltage */ |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 77 | |
Vadim Bendebury | ad6ee02 | 2016-05-12 16:54:00 +0800 | [diff] [blame] | 78 | /* |
| 79 | * The SD card on this board is connected to port SDMMC0, which is |
| 80 | * multiplexed with GPIO4B pins 0..5. |
| 81 | * |
| 82 | * Disable all pullups on these pins. For pullup configuration |
| 83 | * register layout stacks banks 2 through 4 together, hence [2] means |
| 84 | * group 4, [1] means bank B. This register is described on page 342 |
| 85 | * of section 1 of the TRM. |
| 86 | * |
| 87 | * Each GPIO pin's pull config takes two bits, writing zero to the |
| 88 | * field disables pull ups/downs, as described on page 342 of rk3399 |
| 89 | * TRM Version 0.3 Part 1. |
| 90 | */ |
| 91 | write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0)); |
| 92 | |
| 93 | /* |
| 94 | * Set all outputs' drive strength to 8 mA. Group 4 bank B driver |
| 95 | * strength requires three bits per pin. Value of 2 written in that |
| 96 | * three bit field means '8 mA', as deduced from the kernel code. |
| 97 | * |
| 98 | * Thus the six pins involved in SDMMC interface require 18 bits to |
| 99 | * configure drive strength, but each 32 bit register provides only 16 |
| 100 | * bits for this setting, this covers 5 pins fully and one bit from |
| 101 | * the 6th pin. Two more bits spill over to the next register. This is |
| 102 | * described on page 378 of rk3399 TRM Version 0.3 Part 1. |
| 103 | */ |
| 104 | write32(&rk3399_grf->gpio4b_e01, |
| 105 | RK_CLRSETBITS(0xffff, |
| 106 | (2 << 0) | (2 << 3) | |
| 107 | (2 << 6) | (2 << 9) | (2 << 12))); |
| 108 | write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1)); |
| 109 | |
| 110 | /* And now set the multiplexor to enable SDMMC0. */ |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 111 | write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC); |
| 112 | } |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 113 | |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 114 | static void configure_codec(void) |
| 115 | { |
| 116 | write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0); |
| 117 | write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK); |
| 118 | |
| 119 | /* AUDIO IO domain 1.8V voltage selection */ |
| 120 | write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1)); |
| 121 | |
| 122 | /* CPU1_P1.8V_AUDIO_PWREN for P1.8_AUDIO */ |
| 123 | gpio_output(GPIO(0, A, 2), 1); |
| 124 | |
| 125 | /* set CPU1_SPK_PA_EN output */ |
| 126 | gpio_output(GPIO(1, A, 2), 0); |
| 127 | |
| 128 | rkclk_configure_i2s(12288000); |
| 129 | } |
| 130 | |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 131 | static void configure_display(void) |
| 132 | { |
| 133 | /* set pinmux for edp HPD*/ |
| 134 | gpio_input_pulldown(GPIO(4, C, 7)); |
| 135 | write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG); |
| 136 | |
| 137 | gpio_output(GPIO(4, D, 3), 1); /* CPU3_EDP_VDDEN for P3.3V_DISP */ |
| 138 | } |
| 139 | |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 140 | static void setup_usb(void) |
| 141 | { |
| 142 | setup_usb_drd0_dwc3(); |
| 143 | setup_usb_drd1_dwc3(); |
| 144 | } |
| 145 | |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 146 | static void mainboard_init(device_t dev) |
| 147 | { |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 148 | configure_sdmmc(); |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 149 | configure_emmc(); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 150 | configure_codec(); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 151 | configure_display(); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 152 | setup_usb(); |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame^] | 153 | register_reset_to_bl31(); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | static void enable_backlight_booster(void) |
| 157 | { |
| 158 | const struct { |
| 159 | uint8_t reg; |
| 160 | uint8_t value; |
| 161 | } i2c_writes[] = { |
| 162 | {1, 0x84}, |
| 163 | {1, 0x85}, |
| 164 | {0, 0x26} |
| 165 | }; |
| 166 | int i; |
| 167 | const int booster_i2c_port = 0; |
| 168 | uint8_t i2c_buf[2]; |
| 169 | struct i2c_seg i2c_command = { .read = 0, .chip = 0x2c, |
| 170 | .buf = i2c_buf, .len = sizeof(i2c_buf) |
| 171 | }; |
| 172 | |
| 173 | /* |
| 174 | * This function is called on Gru right after BL_EN is asserted. It |
| 175 | * takes time for the switcher chip to come online, let's wait a bit |
| 176 | * to let the voltage settle, so that the chip can be accessed. |
| 177 | */ |
| 178 | udelay(1000); |
| 179 | |
| 180 | /* Select pinmux for i2c0, which is the display backlight booster. */ |
| 181 | write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); |
| 182 | write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); |
| 183 | i2c_init(0, 100*KHz); |
| 184 | |
| 185 | for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) { |
| 186 | i2c_buf[0] = i2c_writes[i].reg; |
| 187 | i2c_buf[1] = i2c_writes[i].value; |
| 188 | i2c_transfer(booster_i2c_port, &i2c_command, 1); |
| 189 | } |
| 190 | } |
| 191 | |
| 192 | void mainboard_power_on_backlight(void) |
| 193 | { |
| 194 | gpio_output(GPIO(1, C, 1), 1); /* BL_EN */ |
| 195 | |
| 196 | if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) |
| 197 | enable_backlight_booster(); |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | static void mainboard_enable(device_t dev) |
| 201 | { |
| 202 | dev->ops->init = &mainboard_init; |
| 203 | } |
| 204 | |
| 205 | struct chip_operations mainboard_ops = { |
| 206 | .name = CONFIG_MAINBOARD_PART_NUMBER, |
| 207 | .enable_dev = mainboard_enable, |
| 208 | }; |