huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2016 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 17 | #include <assert.h> |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 18 | #include <boardid.h> |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 19 | #include <console/console.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 20 | #include <delay.h> |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 21 | #include <device/device.h> |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 22 | #include <device/i2c_simple.h> |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 23 | #include <ec/google/chromeec/ec.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 24 | #include <gpio.h> |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 25 | #include <soc/bl31_plat_params.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 26 | #include <soc/clock.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 27 | #include <soc/display.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 28 | #include <soc/grf.h> |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 29 | #include <soc/mipi.h> |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 30 | #include <soc/i2c.h> |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 31 | #include <soc/usb.h> |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 32 | #include <string.h> |
Simon Glass | bc679bc | 2016-06-19 16:09:21 -0600 | [diff] [blame] | 33 | #include <vendorcode/google/chromeos/chromeos.h> |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 34 | |
Vadim Bendebury | 993dbe1 | 2016-05-22 15:53:37 -0700 | [diff] [blame] | 35 | #include "board.h" |
| 36 | |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 37 | /* |
Caesar Wang | 212a026 | 2017-05-24 18:02:25 +0800 | [diff] [blame] | 38 | * We have to drive the stronger pull-up within 1 second of powering up the |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 39 | * touchpad to prevent its firmware from falling into recovery. Not on |
| 40 | * Scarlet-based boards. |
Caesar Wang | 212a026 | 2017-05-24 18:02:25 +0800 | [diff] [blame] | 41 | */ |
| 42 | static void configure_touchpad(void) |
| 43 | { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 44 | gpio_output(GPIO_TP_RST_L, 1); /* TP's I2C pull-up rail */ |
Caesar Wang | 212a026 | 2017-05-24 18:02:25 +0800 | [diff] [blame] | 45 | } |
| 46 | |
| 47 | /* |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 48 | * Wifi's PDN/RST line is pulled down by its (unpowered) voltage rails, but |
| 49 | * this reset pin is pulled up by default. Let's drive it low as early as we |
Philip Chen | a061820 | 2017-08-23 18:02:25 -0700 | [diff] [blame] | 50 | * can. This only applies to boards with Marvell 8997 WiFi. |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 51 | */ |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 52 | static void assert_wifi_reset(void) |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 53 | { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 54 | gpio_output(GPIO_WLAN_RST_L, 0); /* Assert WLAN_MODULE_RST# */ |
Brian Norris | e06a1b8 | 2016-09-21 18:16:54 -0700 | [diff] [blame] | 55 | } |
| 56 | |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 57 | static void configure_emmc(void) |
| 58 | { |
| 59 | /* Host controller does not support programmable clock generator. |
| 60 | * If we don't do this setting, when we use phy to control the |
| 61 | * emmc clock(when clock exceed 50MHz), it will get wrong clock. |
| 62 | * |
| 63 | * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register. |
| 64 | * Please search "_CON11[7:0]" to locate register description. |
| 65 | */ |
| 66 | write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0)); |
| 67 | |
| 68 | rkclk_configure_emmc(); |
| 69 | } |
| 70 | |
Lin Huang | c9fea5c | 2016-08-30 15:34:42 -0700 | [diff] [blame] | 71 | static void register_apio_suspend(void) |
| 72 | { |
| 73 | static struct bl31_apio_param param_apio = { |
| 74 | .h = { |
| 75 | .type = PARAM_SUSPEND_APIO, |
| 76 | }, |
| 77 | .apio = { |
| 78 | .apio1 = 1, |
| 79 | .apio2 = 1, |
| 80 | .apio3 = 1, |
| 81 | .apio4 = 1, |
| 82 | .apio5 = 1, |
| 83 | }, |
| 84 | }; |
| 85 | register_bl31_param(¶m_apio.h); |
| 86 | } |
| 87 | |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 88 | static void register_gpio_suspend(void) |
| 89 | { |
| 90 | /* |
| 91 | * These three GPIO params are used to shut down the 1.5V, 1.8V and |
| 92 | * 3.3V power rails, which need to be shut down ordered by voltage, |
| 93 | * with highest voltage first. |
| 94 | * Since register_bl31() appends to the front of the list, we need to |
| 95 | * register them backwards, with 1.5V coming first. |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 96 | * 1.5V and 1.8V are EC-controlled on Scarlet derivatives, |
| 97 | * so we skip them. |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 98 | */ |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 99 | if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 100 | static struct bl31_gpio_param param_p15_en = { |
| 101 | .h = { .type = PARAM_SUSPEND_GPIO }, |
| 102 | .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, |
| 103 | }; |
| 104 | param_p15_en.gpio.index = GPIO_P15V_EN.raw; |
| 105 | register_bl31_param(¶m_p15_en.h); |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 106 | |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 107 | static struct bl31_gpio_param param_p18_audio_en = { |
| 108 | .h = { .type = PARAM_SUSPEND_GPIO }, |
| 109 | .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, |
| 110 | }; |
| 111 | param_p18_audio_en.gpio.index = GPIO_P18V_AUDIO_PWREN.raw; |
| 112 | register_bl31_param(¶m_p18_audio_en.h); |
| 113 | } |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 114 | |
| 115 | static struct bl31_gpio_param param_p30_en = { |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 116 | .h = { .type = PARAM_SUSPEND_GPIO }, |
| 117 | .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 118 | }; |
Julius Werner | 4ed8b30 | 2017-07-14 14:25:39 -0700 | [diff] [blame] | 119 | param_p30_en.gpio.index = GPIO_P30V_EN.raw; |
Lin Huang | 7d8ccfb | 2016-08-22 17:35:40 -0700 | [diff] [blame] | 120 | register_bl31_param(¶m_p30_en.h); |
| 121 | } |
| 122 | |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 123 | static void register_reset_to_bl31(void) |
| 124 | { |
| 125 | static struct bl31_gpio_param param_reset = { |
| 126 | .h = { |
| 127 | .type = PARAM_RESET, |
| 128 | }, |
| 129 | .gpio = { |
| 130 | .polarity = 1, |
| 131 | }, |
| 132 | }; |
| 133 | |
| 134 | /* gru/kevin reset pin: gpio0b3 */ |
Julius Werner | 4ed8b30 | 2017-07-14 14:25:39 -0700 | [diff] [blame] | 135 | param_reset.gpio.index = GPIO_RESET.raw, |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 136 | |
| 137 | register_bl31_param(¶m_reset.h); |
| 138 | } |
| 139 | |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 140 | static void register_poweroff_to_bl31(void) |
| 141 | { |
| 142 | static struct bl31_gpio_param param_poweroff = { |
| 143 | .h = { |
| 144 | .type = PARAM_POWEROFF, |
| 145 | }, |
| 146 | .gpio = { |
| 147 | .polarity = 1, |
| 148 | }, |
| 149 | }; |
| 150 | |
| 151 | /* |
| 152 | * gru/kevin power off pin: gpio1a6, |
| 153 | * reuse with tsadc int pin, so iomux need set back to |
| 154 | * gpio in BL31 and depthcharge before you setting this gpio |
| 155 | */ |
Julius Werner | 4ed8b30 | 2017-07-14 14:25:39 -0700 | [diff] [blame] | 156 | param_poweroff.gpio.index = GPIO_POWEROFF.raw, |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 157 | |
| 158 | register_bl31_param(¶m_poweroff.h); |
| 159 | } |
| 160 | |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 161 | static void configure_sdmmc(void) |
| 162 | { |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 163 | gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */ |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 164 | |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 165 | /* set SDMMC_DET_L pin */ |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 166 | if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 167 | /* |
| 168 | * do not have external pull up, so need to |
| 169 | * set this pin internal pull up |
| 170 | */ |
| 171 | gpio_input_pullup(GPIO(1, B, 3)); |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 172 | else |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 173 | gpio_input(GPIO(4, D, 0)); |
Vadim Bendebury | 2832c41 | 2016-05-11 15:03:44 +0800 | [diff] [blame] | 174 | |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 175 | /* |
| 176 | * Keep sd card io domain 3v |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 177 | * In Scarlet derivatives, this GPIO set to high will get 3v, |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 178 | * With other board variants setting this GPIO low results in 3V. |
| 179 | */ |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 180 | if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) |
Lin Huang | a2c5b2f | 2017-07-25 09:50:10 +0800 | [diff] [blame] | 181 | gpio_output(GPIO(2, D, 4), 1); |
| 182 | else |
| 183 | gpio_output(GPIO(2, D, 4), 0); |
Vadim Bendebury | 8e8a00c | 2016-04-22 12:25:07 -0700 | [diff] [blame] | 184 | |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 185 | gpio_input(GPIO(4, B, 0)); /* SDMMC0_D0 remove pull-up */ |
| 186 | gpio_input(GPIO(4, B, 1)); /* SDMMC0_D1 remove pull-up */ |
| 187 | gpio_input(GPIO(4, B, 2)); /* SDMMC0_D2 remove pull-up */ |
| 188 | gpio_input(GPIO(4, B, 3)); /* SDMMC0_D3 remove pull-up */ |
| 189 | gpio_input(GPIO(4, B, 4)); /* SDMMC0_CLK remove pull-down */ |
| 190 | gpio_input(GPIO(4, B, 5)); /* SDMMC0_CMD remove pull-up */ |
| 191 | |
Vadim Bendebury | ad6ee02 | 2016-05-12 16:54:00 +0800 | [diff] [blame] | 192 | write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0)); |
| 193 | |
| 194 | /* |
| 195 | * Set all outputs' drive strength to 8 mA. Group 4 bank B driver |
| 196 | * strength requires three bits per pin. Value of 2 written in that |
| 197 | * three bit field means '8 mA', as deduced from the kernel code. |
| 198 | * |
| 199 | * Thus the six pins involved in SDMMC interface require 18 bits to |
| 200 | * configure drive strength, but each 32 bit register provides only 16 |
| 201 | * bits for this setting, this covers 5 pins fully and one bit from |
| 202 | * the 6th pin. Two more bits spill over to the next register. This is |
| 203 | * described on page 378 of rk3399 TRM Version 0.3 Part 1. |
| 204 | */ |
| 205 | write32(&rk3399_grf->gpio4b_e01, |
| 206 | RK_CLRSETBITS(0xffff, |
| 207 | (2 << 0) | (2 << 3) | |
| 208 | (2 << 6) | (2 << 9) | (2 << 12))); |
| 209 | write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1)); |
| 210 | |
| 211 | /* And now set the multiplexor to enable SDMMC0. */ |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 212 | write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC); |
| 213 | } |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 214 | |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 215 | static void configure_codec(void) |
| 216 | { |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 217 | gpio_input(GPIO(3, D, 0)); /* I2S0_SCLK remove pull-up */ |
| 218 | gpio_input(GPIO(3, D, 1)); /* I2S0_RX remove pull-up */ |
| 219 | gpio_input(GPIO(3, D, 2)); /* I2S0_TX remove pull-up */ |
| 220 | gpio_input(GPIO(3, D, 3)); /* I2S0_SDI0 remove pull-up */ |
Julius Werner | 5598db2 | 2017-12-08 16:42:59 -0800 | [diff] [blame] | 221 | /* GPIOs 3_D4 - 3_D6 not used for I2S and are SKU ID pins on Scarlet. */ |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 222 | gpio_input(GPIO(3, D, 7)); /* I2S0_SDO0 remove pull-up */ |
| 223 | gpio_input(GPIO(4, A, 0)); /* I2S0_MCLK remove pull-up */ |
| 224 | |
Julius Werner | 5598db2 | 2017-12-08 16:42:59 -0800 | [diff] [blame] | 225 | write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0_SD0); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 226 | write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK); |
| 227 | |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 228 | if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) |
Julius Werner | 1ab8c01 | 2017-11-03 15:23:09 -0700 | [diff] [blame] | 229 | gpio_output(GPIO_P18V_AUDIO_PWREN, 1); |
| 230 | gpio_output(GPIO_SPK_PA_EN, 0); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 231 | |
| 232 | rkclk_configure_i2s(12288000); |
| 233 | } |
| 234 | |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 235 | static void configure_display(void) |
| 236 | { |
Ege Mihmanli | beb0468 | 2017-11-20 11:54:02 -0800 | [diff] [blame] | 237 | /* |
| 238 | * Rainier is Scarlet-derived, but uses EDP so use board-specific |
| 239 | * config rather than baseboard. |
| 240 | */ |
| 241 | if (IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 242 | gpio_output(GPIO(4, D, 1), 0); /* DISPLAY_RST_L */ |
| 243 | gpio_output(GPIO(4, D, 3), 1); /* PPVARP_LCD */ |
| 244 | mdelay(10); |
| 245 | gpio_output(GPIO(4, D, 4), 1); /* PPVARN_LCD */ |
| 246 | mdelay(20 + 2); /* add 2ms for bias rise time */ |
| 247 | gpio_output(GPIO(4, D, 1), 1); /* DISPLAY_RST_L */ |
| 248 | mdelay(30); |
| 249 | } else { |
| 250 | /* set pinmux for edp HPD */ |
| 251 | gpio_input_pulldown(GPIO(4, C, 7)); |
| 252 | write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 253 | |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 254 | gpio_output(GPIO(4, D, 3), 1); /* P3.3V_DISP */ |
| 255 | } |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 256 | } |
| 257 | |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 258 | static void usb_power_cycle(int port) |
| 259 | { |
| 260 | if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK)) |
| 261 | printk(BIOS_ERR, "ERROR: Cannot force USB%d PD sink\n", port); |
| 262 | |
| 263 | mdelay(10); /* Make sure USB stick is fully depowered. */ |
| 264 | |
| 265 | if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON)) |
| 266 | printk(BIOS_ERR, "ERROR: Cannot restore USB%d PD mode\n", port); |
| 267 | } |
| 268 | |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 269 | static void setup_usb(int port) |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 270 | { |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 271 | /* Must be PHY0 or PHY1. */ |
| 272 | assert(port == 0 || port == 1); |
| 273 | |
William wu | 605a87c | 2017-01-09 19:02:39 +0800 | [diff] [blame] | 274 | /* |
| 275 | * A few magic PHY tuning values that improve eye diagram amplitude |
| 276 | * and make it extra sure we get reliable communication in firmware |
| 277 | * Set max ODT compensation voltage and current tuning reference. |
| 278 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 279 | write32(&rk3399_grf->usbphy_ctrl[port][3], RK_CLRSETBITS(0xfff, 0x2e3)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 280 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 281 | /* Set max pre-emphasis level on PHY0 and PHY1. */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 282 | write32(&rk3399_grf->usbphy_ctrl[port][12], |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 283 | RK_CLRSETBITS(0xffff, 0xa7)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 284 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 285 | /* |
William wu | ebbdd28 | 2017-01-23 20:54:22 +0800 | [diff] [blame] | 286 | * 1. Disable the pre-emphasize in eop state and chirp |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 287 | * state to avoid mis-trigger the disconnect detection |
| 288 | * and also avoid high-speed handshake fail for PHY0 |
| 289 | * and PHY1 consist of otg-port and host-port. |
William wu | ebbdd28 | 2017-01-23 20:54:22 +0800 | [diff] [blame] | 290 | * |
| 291 | * 2. Configure PHY0 and PHY1 otg-ports squelch detection |
| 292 | * threshold to 125mV (default is 150mV). |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 293 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 294 | write32(&rk3399_grf->usbphy_ctrl[port][0], |
William wu | ebbdd28 | 2017-01-23 20:54:22 +0800 | [diff] [blame] | 295 | RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13)); |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 296 | write32(&rk3399_grf->usbphy_ctrl[port][13], RK_CLRBITS(3 << 0)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 297 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 298 | /* |
| 299 | * ODT auto compensation bypass, and set max driver |
| 300 | * strength only for PHY0 and PHY1 otg-port. |
| 301 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 302 | write32(&rk3399_grf->usbphy_ctrl[port][2], |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 303 | RK_CLRSETBITS(0x7e << 4, 0x60 << 4)); |
William wu | 9f470b1 | 2016-11-10 19:34:45 +0800 | [diff] [blame] | 304 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 305 | /* |
| 306 | * ODT auto refresh bypass, and set the max bias current |
| 307 | * tuning reference only for PHY0 and PHY1 otg-port. |
| 308 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 309 | write32(&rk3399_grf->usbphy_ctrl[port][3], |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 310 | RK_CLRSETBITS(0x21c, 1 << 4)); |
William wu | 605a87c | 2017-01-09 19:02:39 +0800 | [diff] [blame] | 311 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 312 | /* |
| 313 | * ODT auto compensation bypass, and set default driver |
| 314 | * strength only for PHY0 and PHY1 host-port. |
| 315 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 316 | write32(&rk3399_grf->usbphy_ctrl[port][15], RK_SETBITS(1 << 10)); |
William wu | 605a87c | 2017-01-09 19:02:39 +0800 | [diff] [blame] | 317 | |
Caesar Wang | 9e58800 | 2017-02-10 11:16:13 +0800 | [diff] [blame] | 318 | /* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 319 | write32(&rk3399_grf->usbphy_ctrl[port][16], RK_CLRBITS(1 << 9)); |
Julius Werner | 1c8491c | 2016-08-15 17:58:05 -0700 | [diff] [blame] | 320 | |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 321 | if (port == 0) |
| 322 | setup_usb_otg0(); |
| 323 | else |
| 324 | setup_usb_otg1(); |
Julius Werner | c49782c | 2016-11-21 20:14:18 -0800 | [diff] [blame] | 325 | |
| 326 | /* |
| 327 | * Need to power-cycle USB ports for use in firmware, since some devices |
| 328 | * can't fall back to USB 2.0 after they saw SuperSpeed terminations. |
| 329 | * This takes about a dozen milliseconds, so only do it in boot modes |
| 330 | * that have firmware UI (which one could select USB boot from). |
| 331 | */ |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 332 | if (display_init_required()) |
| 333 | usb_power_cycle(port); |
Liangfeng Wu | 76655cb | 2016-05-26 16:06:58 +0800 | [diff] [blame] | 334 | } |
| 335 | |
Elyes HAOUAS | d129d43 | 2018-05-04 20:23:33 +0200 | [diff] [blame^] | 336 | static void mainboard_init(struct device *dev) |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 337 | { |
Vadim Bendebury | 1e80ab3 | 2016-03-28 00:44:54 -0700 | [diff] [blame] | 338 | configure_sdmmc(); |
Lin Huang | 2f7ed8d | 2016-04-08 18:56:20 +0800 | [diff] [blame] | 339 | configure_emmc(); |
Xing Zheng | 96fbc31 | 2016-05-19 11:39:20 +0800 | [diff] [blame] | 340 | configure_codec(); |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 341 | if (display_init_required()) |
| 342 | configure_display(); |
philipchen | 21b0852 | 2017-04-27 18:25:11 -0700 | [diff] [blame] | 343 | setup_usb(0); |
Philip Chen | a061820 | 2017-08-23 18:02:25 -0700 | [diff] [blame] | 344 | if (IS_ENABLED(CONFIG_GRU_HAS_WLAN_RESET)) |
| 345 | assert_wifi_reset(); |
Ege Mihmanli | 75b1543 | 2017-11-15 17:19:58 -0800 | [diff] [blame] | 346 | if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 347 | configure_touchpad(); /* Scarlet: works differently */ |
| 348 | setup_usb(1); /* Scarlet: only one USB port */ |
Julius Werner | 6486e78 | 2017-07-14 14:30:29 -0700 | [diff] [blame] | 349 | } |
Julius Werner | 2be6404 | 2017-09-01 14:27:46 -0700 | [diff] [blame] | 350 | register_gpio_suspend(); |
Lin Huang | 5a4be8a | 2016-05-17 15:45:53 +0800 | [diff] [blame] | 351 | register_reset_to_bl31(); |
Lin Huang | 9a5c4fe | 2016-05-19 11:11:23 +0800 | [diff] [blame] | 352 | register_poweroff_to_bl31(); |
Lin Huang | c9fea5c | 2016-08-30 15:34:42 -0700 | [diff] [blame] | 353 | register_apio_suspend(); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 354 | } |
| 355 | |
Philip Chen | a304b69 | 2017-04-06 10:17:08 -0700 | [diff] [blame] | 356 | static void prepare_backlight_i2c(void) |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 357 | { |
Julius Werner | 7feb86b | 2016-09-02 11:25:56 -0700 | [diff] [blame] | 358 | gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull_up */ |
| 359 | gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull_up */ |
| 360 | |
| 361 | i2c_init(0, 100*KHz); |
| 362 | |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 363 | write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); |
| 364 | write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 365 | } |
| 366 | |
| 367 | void mainboard_power_on_backlight(void) |
| 368 | { |
Lin Huang | 18617bf | 2017-11-20 14:57:22 +0800 | [diff] [blame] | 369 | gpio_output(GPIO_BL_EN, 1); /* BL_EN */ |
| 370 | |
| 371 | /* Configure as output GPIO, to be toggled by payload. */ |
| 372 | if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) |
| 373 | gpio_output(GPIO_BACKLIGHT, 0); |
Lin Huang | b497b48 | 2016-03-31 18:44:13 +0800 | [diff] [blame] | 374 | |
Philip Chen | a304b69 | 2017-04-06 10:17:08 -0700 | [diff] [blame] | 375 | if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) |
| 376 | prepare_backlight_i2c(); |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 377 | } |
| 378 | |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 379 | static struct panel_init_command innolux_p097pfg_init_cmds[] = { |
| 380 | /* page 0 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 381 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00), |
| 382 | MIPI_INIT_CMD(0xB1, 0xE8, 0x11), |
| 383 | MIPI_INIT_CMD(0xB2, 0x25, 0x02), |
| 384 | MIPI_INIT_CMD(0xB5, 0x08, 0x00), |
| 385 | MIPI_INIT_CMD(0xBC, 0x0F, 0x00), |
| 386 | MIPI_INIT_CMD(0xB8, 0x03, 0x06, 0x00, 0x00), |
| 387 | MIPI_INIT_CMD(0xBD, 0x01, 0x90, 0x14, 0x14), |
| 388 | MIPI_INIT_CMD(0x6F, 0x01), |
| 389 | MIPI_INIT_CMD(0xC0, 0x03), |
| 390 | MIPI_INIT_CMD(0x6F, 0x02), |
| 391 | MIPI_INIT_CMD(0xC1, 0x0D), |
| 392 | MIPI_INIT_CMD(0xD9, 0x01, 0x09, 0x70), |
| 393 | MIPI_INIT_CMD(0xC5, 0x12, 0x21, 0x00), |
| 394 | MIPI_INIT_CMD(0xBB, 0x93, 0x93), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 395 | |
| 396 | /* page 1 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 397 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01), |
| 398 | MIPI_INIT_CMD(0xB3, 0x3C, 0x3C), |
| 399 | MIPI_INIT_CMD(0xB4, 0x0F, 0x0F), |
| 400 | MIPI_INIT_CMD(0xB9, 0x45, 0x45), |
| 401 | MIPI_INIT_CMD(0xBA, 0x14, 0x14), |
| 402 | MIPI_INIT_CMD(0xCA, 0x02), |
| 403 | MIPI_INIT_CMD(0xCE, 0x04), |
| 404 | MIPI_INIT_CMD(0xC3, 0x9B, 0x9B), |
| 405 | MIPI_INIT_CMD(0xD8, 0xC0, 0x03), |
| 406 | MIPI_INIT_CMD(0xBC, 0x82, 0x01), |
| 407 | MIPI_INIT_CMD(0xBD, 0x9E, 0x01), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 408 | |
| 409 | /* page 2 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 410 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02), |
| 411 | MIPI_INIT_CMD(0xB0, 0x82), |
| 412 | MIPI_INIT_CMD(0xD1, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x82, 0x00, 0xA5, |
| 413 | 0x00, 0xC1, 0x00, 0xEA, 0x01, 0x0D, 0x01, 0x40), |
| 414 | MIPI_INIT_CMD(0xD2, 0x01, 0x6A, 0x01, 0xA8, 0x01, 0xDC, 0x02, 0x29, |
| 415 | 0x02, 0x67, 0x02, 0x68, 0x02, 0xA8, 0x02, 0xF0), |
| 416 | MIPI_INIT_CMD(0xD3, 0x03, 0x19, 0x03, 0x49, 0x03, 0x67, 0x03, 0x8C, |
| 417 | 0x03, 0xA6, 0x03, 0xC7, 0x03, 0xDE, 0x03, 0xEC), |
| 418 | MIPI_INIT_CMD(0xD4, 0x03, 0xFF, 0x03, 0xFF), |
| 419 | MIPI_INIT_CMD(0xE0, 0x00, 0x00, 0x00, 0x86, 0x00, 0xC5, 0x00, 0xE5, |
| 420 | 0x00, 0xFF, 0x01, 0x26, 0x01, 0x45, 0x01, 0x75), |
| 421 | MIPI_INIT_CMD(0xE1, 0x01, 0x9C, 0x01, 0xD5, 0x02, 0x05, 0x02, 0x4D, |
| 422 | 0x02, 0x86, 0x02, 0x87, 0x02, 0xC3, 0x03, 0x03), |
| 423 | MIPI_INIT_CMD(0xE2, 0x03, 0x2A, 0x03, 0x56, 0x03, 0x72, 0x03, 0x94, |
| 424 | 0x03, 0xAC, 0x03, 0xCB, 0x03, 0xE0, 0x03, 0xED), |
| 425 | MIPI_INIT_CMD(0xE3, 0x03, 0xFF, 0x03, 0xFF), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 426 | |
| 427 | /* page 3 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 428 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03), |
| 429 | MIPI_INIT_CMD(0xB0, 0x00, 0x00, 0x00, 0x00), |
| 430 | MIPI_INIT_CMD(0xB1, 0x00, 0x00, 0x00, 0x00), |
| 431 | MIPI_INIT_CMD(0xB2, 0x00, 0x00, 0x06, 0x04, 0x01, 0x40, 0x85), |
| 432 | MIPI_INIT_CMD(0xB3, 0x10, 0x07, 0xFC, 0x04, 0x01, 0x40, 0x80), |
| 433 | MIPI_INIT_CMD(0xB6, 0xF0, 0x08, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, |
| 434 | 0x40, 0x80), |
| 435 | MIPI_INIT_CMD(0xBA, 0xC5, 0x07, 0x00, 0x04, 0x11, 0x25, 0x8C), |
| 436 | MIPI_INIT_CMD(0xBB, 0xC5, 0x07, 0x00, 0x03, 0x11, 0x25, 0x8C), |
| 437 | MIPI_INIT_CMD(0xC0, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x80), |
| 438 | MIPI_INIT_CMD(0xC1, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x80, 0x80), |
| 439 | MIPI_INIT_CMD(0xC4, 0x00, 0x00), |
| 440 | MIPI_INIT_CMD(0xEF, 0x41), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 441 | |
| 442 | /* page 4 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 443 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04), |
| 444 | MIPI_INIT_CMD(0xEC, 0x4C), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 445 | |
| 446 | /* page 5 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 447 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05), |
| 448 | MIPI_INIT_CMD(0xB0, 0x13, 0x03, 0x03, 0x01), |
| 449 | MIPI_INIT_CMD(0xB1, 0x30, 0x00), |
| 450 | MIPI_INIT_CMD(0xB2, 0x02, 0x02, 0x00), |
| 451 | MIPI_INIT_CMD(0xB3, 0x82, 0x23, 0x82, 0x9D), |
| 452 | MIPI_INIT_CMD(0xB4, 0xC5, 0x75, 0x24, 0x57), |
| 453 | MIPI_INIT_CMD(0xB5, 0x00, 0xD4, 0x72, 0x11, 0x11, 0xAB, 0x0A), |
| 454 | MIPI_INIT_CMD(0xB6, 0x00, 0x00, 0xD5, 0x72, 0x24, 0x56), |
| 455 | MIPI_INIT_CMD(0xB7, 0x5C, 0xDC, 0x5C, 0x5C), |
| 456 | MIPI_INIT_CMD(0xB9, 0x0C, 0x00, 0x00, 0x01, 0x00), |
| 457 | MIPI_INIT_CMD(0xC0, 0x75, 0x11, 0x11, 0x54, 0x05), |
| 458 | MIPI_INIT_CMD(0xC6, 0x00, 0x00, 0x00, 0x00), |
| 459 | MIPI_INIT_CMD(0xD0, 0x00, 0x48, 0x08, 0x00, 0x00), |
| 460 | MIPI_INIT_CMD(0xD1, 0x00, 0x48, 0x09, 0x00, 0x00), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 461 | |
| 462 | /* page 6 */ |
Lin Huang | 1cce10e | 2018-02-02 10:07:52 +0800 | [diff] [blame] | 463 | MIPI_INIT_CMD(0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06), |
| 464 | MIPI_INIT_CMD(0xB0, 0x02, 0x32, 0x32, 0x08, 0x2F), |
| 465 | MIPI_INIT_CMD(0xB1, 0x2E, 0x15, 0x14, 0x13, 0x12), |
| 466 | MIPI_INIT_CMD(0xB2, 0x11, 0x10, 0x00, 0x3D, 0x3D), |
| 467 | MIPI_INIT_CMD(0xB3, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D), |
| 468 | MIPI_INIT_CMD(0xB4, 0x3D, 0x32), |
| 469 | MIPI_INIT_CMD(0xB5, 0x03, 0x32, 0x32, 0x09, 0x2F), |
| 470 | MIPI_INIT_CMD(0xB6, 0x2E, 0x1B, 0x1A, 0x19, 0x18), |
| 471 | MIPI_INIT_CMD(0xB7, 0x17, 0x16, 0x01, 0x3D, 0x3D), |
| 472 | MIPI_INIT_CMD(0xB8, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D), |
| 473 | MIPI_INIT_CMD(0xB9, 0x3D, 0x32), |
| 474 | MIPI_INIT_CMD(0xC0, 0x01, 0x32, 0x32, 0x09, 0x2F), |
| 475 | MIPI_INIT_CMD(0xC1, 0x2E, 0x1A, 0x1B, 0x16, 0x17), |
| 476 | MIPI_INIT_CMD(0xC2, 0x18, 0x19, 0x03, 0x3D, 0x3D), |
| 477 | MIPI_INIT_CMD(0xC3, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D), |
| 478 | MIPI_INIT_CMD(0xC4, 0x3D, 0x32), |
| 479 | MIPI_INIT_CMD(0xC5, 0x00, 0x32, 0x32, 0x08, 0x2F), |
| 480 | MIPI_INIT_CMD(0xC6, 0x2E, 0x14, 0x15, 0x10, 0x11), |
| 481 | MIPI_INIT_CMD(0xC7, 0x12, 0x13, 0x02, 0x3D, 0x3D), |
| 482 | MIPI_INIT_CMD(0xC8, 0x3D, 0x3D, 0x3D, 0x3D, 0x3D), |
| 483 | MIPI_INIT_CMD(0xC9, 0x3D, 0x32), |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 484 | |
| 485 | {}, |
| 486 | }; |
| 487 | |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 488 | static struct panel_init_command kd097d04_init_commands[] = { |
| 489 | /* voltage setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 490 | MIPI_INIT_CMD(0xB0, 0x00), |
| 491 | MIPI_INIT_CMD(0xB2, 0x02), |
| 492 | MIPI_INIT_CMD(0xB3, 0x11), |
| 493 | MIPI_INIT_CMD(0xB4, 0x00), |
| 494 | MIPI_INIT_CMD(0xB6, 0x80), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 495 | /* VCOM disable */ |
Brian Norris | cc761e8 | 2018-03-07 13:11:47 -0800 | [diff] [blame] | 496 | MIPI_INIT_CMD(0xB7, 0x02), |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 497 | MIPI_INIT_CMD(0xB8, 0x80), |
| 498 | MIPI_INIT_CMD(0xBA, 0x43), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 499 | /* VCOM setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 500 | MIPI_INIT_CMD(0xBB, 0x53), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 501 | /* VSP setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 502 | MIPI_INIT_CMD(0xBC, 0x0A), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 503 | /* VSN setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 504 | MIPI_INIT_CMD(0xBD, 0x4A), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 505 | /* VGH setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 506 | MIPI_INIT_CMD(0xBE, 0x2F), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 507 | /* VGL setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 508 | MIPI_INIT_CMD(0xBF, 0x1A), |
| 509 | MIPI_INIT_CMD(0xF0, 0x39), |
Brian Norris | cc761e8 | 2018-03-07 13:11:47 -0800 | [diff] [blame] | 510 | MIPI_INIT_CMD(0xF1, 0x22), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 511 | /* Gamma setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 512 | MIPI_INIT_CMD(0xB0, 0x02), |
| 513 | MIPI_INIT_CMD(0xC0, 0x00), |
| 514 | MIPI_INIT_CMD(0xC1, 0x01), |
| 515 | MIPI_INIT_CMD(0xC2, 0x0B), |
| 516 | MIPI_INIT_CMD(0xC3, 0x15), |
| 517 | MIPI_INIT_CMD(0xC4, 0x22), |
| 518 | MIPI_INIT_CMD(0xC5, 0x11), |
| 519 | MIPI_INIT_CMD(0xC6, 0x15), |
| 520 | MIPI_INIT_CMD(0xC7, 0x19), |
| 521 | MIPI_INIT_CMD(0xC8, 0x1A), |
| 522 | MIPI_INIT_CMD(0xC9, 0x16), |
| 523 | MIPI_INIT_CMD(0xCA, 0x18), |
| 524 | MIPI_INIT_CMD(0xCB, 0x13), |
| 525 | MIPI_INIT_CMD(0xCC, 0x18), |
| 526 | MIPI_INIT_CMD(0xCD, 0x13), |
| 527 | MIPI_INIT_CMD(0xCE, 0x1C), |
| 528 | MIPI_INIT_CMD(0xCF, 0x19), |
| 529 | MIPI_INIT_CMD(0xD0, 0x21), |
| 530 | MIPI_INIT_CMD(0xD1, 0x2C), |
| 531 | MIPI_INIT_CMD(0xD2, 0x2F), |
| 532 | MIPI_INIT_CMD(0xD3, 0x30), |
| 533 | MIPI_INIT_CMD(0xD4, 0x19), |
| 534 | MIPI_INIT_CMD(0xD5, 0x1F), |
| 535 | MIPI_INIT_CMD(0xD6, 0x00), |
| 536 | MIPI_INIT_CMD(0xD7, 0x01), |
| 537 | MIPI_INIT_CMD(0xD8, 0x0B), |
| 538 | MIPI_INIT_CMD(0xD9, 0x15), |
| 539 | MIPI_INIT_CMD(0xDA, 0x22), |
| 540 | MIPI_INIT_CMD(0xDB, 0x11), |
| 541 | MIPI_INIT_CMD(0xDC, 0x15), |
| 542 | MIPI_INIT_CMD(0xDD, 0x19), |
| 543 | MIPI_INIT_CMD(0xDE, 0x1A), |
| 544 | MIPI_INIT_CMD(0xDF, 0x16), |
| 545 | MIPI_INIT_CMD(0xE0, 0x18), |
| 546 | MIPI_INIT_CMD(0xE1, 0x13), |
| 547 | MIPI_INIT_CMD(0xE2, 0x18), |
| 548 | MIPI_INIT_CMD(0xE3, 0x13), |
| 549 | MIPI_INIT_CMD(0xE4, 0x1C), |
| 550 | MIPI_INIT_CMD(0xE5, 0x19), |
| 551 | MIPI_INIT_CMD(0xE6, 0x21), |
| 552 | MIPI_INIT_CMD(0xE7, 0x2C), |
| 553 | MIPI_INIT_CMD(0xE8, 0x2F), |
| 554 | MIPI_INIT_CMD(0xE9, 0x30), |
| 555 | MIPI_INIT_CMD(0xEA, 0x19), |
| 556 | MIPI_INIT_CMD(0xEB, 0x1F), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 557 | /* GOA MUX setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 558 | MIPI_INIT_CMD(0xB0, 0x01), |
| 559 | MIPI_INIT_CMD(0xC0, 0x10), |
| 560 | MIPI_INIT_CMD(0xC1, 0x0F), |
| 561 | MIPI_INIT_CMD(0xC2, 0x0E), |
| 562 | MIPI_INIT_CMD(0xC3, 0x0D), |
| 563 | MIPI_INIT_CMD(0xC4, 0x0C), |
| 564 | MIPI_INIT_CMD(0xC5, 0x0B), |
| 565 | MIPI_INIT_CMD(0xC6, 0x0A), |
| 566 | MIPI_INIT_CMD(0xC7, 0x09), |
| 567 | MIPI_INIT_CMD(0xC8, 0x08), |
| 568 | MIPI_INIT_CMD(0xC9, 0x07), |
| 569 | MIPI_INIT_CMD(0xCA, 0x06), |
| 570 | MIPI_INIT_CMD(0xCB, 0x05), |
| 571 | MIPI_INIT_CMD(0xCC, 0x00), |
| 572 | MIPI_INIT_CMD(0xCD, 0x01), |
| 573 | MIPI_INIT_CMD(0xCE, 0x02), |
| 574 | MIPI_INIT_CMD(0xCF, 0x03), |
| 575 | MIPI_INIT_CMD(0xD0, 0x04), |
| 576 | MIPI_INIT_CMD(0xD6, 0x10), |
| 577 | MIPI_INIT_CMD(0xD7, 0x0F), |
| 578 | MIPI_INIT_CMD(0xD8, 0x0E), |
| 579 | MIPI_INIT_CMD(0xD9, 0x0D), |
| 580 | MIPI_INIT_CMD(0xDA, 0x0C), |
| 581 | MIPI_INIT_CMD(0xDB, 0x0B), |
| 582 | MIPI_INIT_CMD(0xDC, 0x0A), |
| 583 | MIPI_INIT_CMD(0xDD, 0x09), |
| 584 | MIPI_INIT_CMD(0xDE, 0x08), |
| 585 | MIPI_INIT_CMD(0xDF, 0x07), |
| 586 | MIPI_INIT_CMD(0xE0, 0x06), |
| 587 | MIPI_INIT_CMD(0xE1, 0x05), |
| 588 | MIPI_INIT_CMD(0xE2, 0x00), |
| 589 | MIPI_INIT_CMD(0xE3, 0x01), |
| 590 | MIPI_INIT_CMD(0xE4, 0x02), |
| 591 | MIPI_INIT_CMD(0xE5, 0x03), |
| 592 | MIPI_INIT_CMD(0xE6, 0x04), |
| 593 | MIPI_INIT_CMD(0xE7, 0x00), |
| 594 | MIPI_INIT_CMD(0xEC, 0xC0), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 595 | /* GOA timing setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 596 | MIPI_INIT_CMD(0xB0, 0x03), |
| 597 | MIPI_INIT_CMD(0xC0, 0x01), |
| 598 | MIPI_INIT_CMD(0xC2, 0x6F), |
| 599 | MIPI_INIT_CMD(0xC3, 0x6F), |
| 600 | MIPI_INIT_CMD(0xC5, 0x36), |
| 601 | MIPI_INIT_CMD(0xC8, 0x08), |
| 602 | MIPI_INIT_CMD(0xC9, 0x04), |
| 603 | MIPI_INIT_CMD(0xCA, 0x41), |
| 604 | MIPI_INIT_CMD(0xCC, 0x43), |
| 605 | MIPI_INIT_CMD(0xCF, 0x60), |
| 606 | MIPI_INIT_CMD(0xD2, 0x04), |
| 607 | MIPI_INIT_CMD(0xD3, 0x04), |
| 608 | MIPI_INIT_CMD(0xD4, 0x03), |
| 609 | MIPI_INIT_CMD(0xD5, 0x02), |
| 610 | MIPI_INIT_CMD(0xD6, 0x01), |
| 611 | MIPI_INIT_CMD(0xD7, 0x00), |
| 612 | MIPI_INIT_CMD(0xDB, 0x01), |
| 613 | MIPI_INIT_CMD(0xDE, 0x36), |
| 614 | MIPI_INIT_CMD(0xE6, 0x6F), |
| 615 | MIPI_INIT_CMD(0xE7, 0x6F), |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 616 | /* GOE setting */ |
Lin Huang | 0499ce9 | 2018-01-17 14:24:14 +0800 | [diff] [blame] | 617 | MIPI_INIT_CMD(0xB0, 0x06), |
| 618 | MIPI_INIT_CMD(0xB8, 0xA5), |
| 619 | MIPI_INIT_CMD(0xC0, 0xA5), |
| 620 | MIPI_INIT_CMD(0xD5, 0x3F), |
| 621 | {}, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 622 | }; |
| 623 | |
| 624 | const struct mipi_panel_data kd097d04_panel = { |
| 625 | .mipi_num = 2, |
| 626 | .format = MIPI_DSI_FMT_RGB888, |
| 627 | .lanes = 8, |
| 628 | .display_on_udelay = 120000, |
| 629 | .video_mode_udelay = 5000, |
| 630 | .init_cmd = kd097d04_init_commands, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 631 | }; |
| 632 | |
| 633 | static const struct edid_mode kd097d04_edid_mode = { |
| 634 | .name = "1536x2048@60Hz", |
Lin Huang | ab21ab9 | 2017-12-06 10:18:10 +0800 | [diff] [blame] | 635 | .pixel_clock = 216000, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 636 | .refresh = 60, |
| 637 | .ha = 1536, |
Lin Huang | ab21ab9 | 2017-12-06 10:18:10 +0800 | [diff] [blame] | 638 | .hbl = 186, |
| 639 | .hso = 81, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 640 | .hspw = 24, |
| 641 | .va = 2048, |
Lin Huang | ab21ab9 | 2017-12-06 10:18:10 +0800 | [diff] [blame] | 642 | .vbl = 42, |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 643 | .vso = 17, |
| 644 | .vspw = 2, |
| 645 | }; |
| 646 | |
Lin Huang | 318a03a | 2017-12-08 10:31:46 +0800 | [diff] [blame] | 647 | const struct mipi_panel_data inx097pfg_panel = { |
| 648 | .mipi_num = 2, |
| 649 | .format = MIPI_DSI_FMT_RGB888, |
| 650 | .lanes = 8, |
| 651 | .display_on_udelay = 120000, |
| 652 | .video_mode_udelay = 5000, |
Lin Huang | 3c0d7cf | 2018-01-18 11:24:28 +0800 | [diff] [blame] | 653 | .init_cmd = innolux_p097pfg_init_cmds, |
Lin Huang | 318a03a | 2017-12-08 10:31:46 +0800 | [diff] [blame] | 654 | }; |
| 655 | |
| 656 | static const struct edid_mode inx097pfg_edid_mode = { |
| 657 | .name = "1536x2048@60Hz", |
| 658 | .pixel_clock = 220000, |
| 659 | .refresh = 60, |
| 660 | .ha = 1536, |
| 661 | .hbl = 224, |
| 662 | .hso = 100, |
| 663 | .hspw = 24, |
| 664 | .va = 2048, |
| 665 | .vbl = 38, |
| 666 | .vso = 18, |
| 667 | .vspw = 2, |
| 668 | }; |
| 669 | |
Lin Huang | add7666 | 2017-11-23 08:50:03 +0800 | [diff] [blame] | 670 | const struct mipi_panel_data *mainboard_get_mipi_mode |
| 671 | (struct edid_mode *edid_mode) |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 672 | { |
Lin Huang | 318a03a | 2017-12-08 10:31:46 +0800 | [diff] [blame] | 673 | switch (sku_id()) { |
| 674 | case 0: |
| 675 | case 2: |
| 676 | case 4: |
| 677 | case 6: |
| 678 | memcpy(edid_mode, &inx097pfg_edid_mode, |
| 679 | sizeof(struct edid_mode)); |
| 680 | return &inx097pfg_panel; |
| 681 | case 1: |
| 682 | case 3: |
| 683 | case 5: |
| 684 | case 7: |
| 685 | default: |
| 686 | memcpy(edid_mode, &kd097d04_edid_mode, |
| 687 | sizeof(struct edid_mode)); |
| 688 | return &kd097d04_panel; |
| 689 | } |
Lin Huang | 25fb09b | 2017-11-22 09:40:50 +0800 | [diff] [blame] | 690 | } |
| 691 | |
Elyes HAOUAS | d129d43 | 2018-05-04 20:23:33 +0200 | [diff] [blame^] | 692 | static void mainboard_enable(struct device *dev) |
huang lin | a6dbfb5 | 2016-03-02 18:38:40 +0800 | [diff] [blame] | 693 | { |
| 694 | dev->ops->init = &mainboard_init; |
| 695 | } |
| 696 | |
| 697 | struct chip_operations mainboard_ops = { |
| 698 | .name = CONFIG_MAINBOARD_PART_NUMBER, |
| 699 | .enable_dev = mainboard_enable, |
| 700 | }; |