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huang lina6dbfb52016-03-02 18:38:40 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070017#include <boardid.h>
Lin Huangb497b482016-03-31 18:44:13 +080018#include <delay.h>
huang lina6dbfb52016-03-02 18:38:40 +080019#include <device/device.h>
Lin Huangb497b482016-03-31 18:44:13 +080020#include <device/i2c.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070021#include <gpio.h>
22#include <soc/clock.h>
Lin Huangb497b482016-03-31 18:44:13 +080023#include <soc/display.h>
Shunqian Zheng462e1412016-05-02 10:27:30 +080024#include <soc/emmc.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070025#include <soc/grf.h>
Lin Huangb497b482016-03-31 18:44:13 +080026#include <soc/i2c.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070027
Vadim Bendebury993dbe12016-05-22 15:53:37 -070028#include "board.h"
29
Lin Huang2f7ed8d2016-04-08 18:56:20 +080030static void configure_emmc(void)
31{
32 /* Host controller does not support programmable clock generator.
33 * If we don't do this setting, when we use phy to control the
34 * emmc clock(when clock exceed 50MHz), it will get wrong clock.
35 *
36 * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register.
37 * Please search "_CON11[7:0]" to locate register description.
38 */
39 write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
40
41 rkclk_configure_emmc();
Shunqian Zheng462e1412016-05-02 10:27:30 +080042
43 enable_emmc_clk();
Lin Huang2f7ed8d2016-04-08 18:56:20 +080044}
45
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070046static void configure_sdmmc(void)
47{
48 gpio_output(GPIO(4, D, 5), 1); /* SDMMC_PWR_EN */
49 gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */
Vadim Bendebury2832c412016-05-11 15:03:44 +080050
51 /* SDMMC_DET_L is different on Kevin board revision 0. */
52 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && (board_id() == 0))
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070053 gpio_input(GPIO(4, D, 2));
Vadim Bendebury2832c412016-05-11 15:03:44 +080054 else
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070055 gpio_input(GPIO(4, D, 0));
Vadim Bendebury2832c412016-05-11 15:03:44 +080056
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070057 gpio_output(GPIO(2, D, 4), 0); /* Keep the max voltage */
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070058
Vadim Bendeburyad6ee022016-05-12 16:54:00 +080059 /*
60 * The SD card on this board is connected to port SDMMC0, which is
61 * multiplexed with GPIO4B pins 0..5.
62 *
63 * Disable all pullups on these pins. For pullup configuration
64 * register layout stacks banks 2 through 4 together, hence [2] means
65 * group 4, [1] means bank B. This register is described on page 342
66 * of section 1 of the TRM.
67 *
68 * Each GPIO pin's pull config takes two bits, writing zero to the
69 * field disables pull ups/downs, as described on page 342 of rk3399
70 * TRM Version 0.3 Part 1.
71 */
72 write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0));
73
74 /*
75 * Set all outputs' drive strength to 8 mA. Group 4 bank B driver
76 * strength requires three bits per pin. Value of 2 written in that
77 * three bit field means '8 mA', as deduced from the kernel code.
78 *
79 * Thus the six pins involved in SDMMC interface require 18 bits to
80 * configure drive strength, but each 32 bit register provides only 16
81 * bits for this setting, this covers 5 pins fully and one bit from
82 * the 6th pin. Two more bits spill over to the next register. This is
83 * described on page 378 of rk3399 TRM Version 0.3 Part 1.
84 */
85 write32(&rk3399_grf->gpio4b_e01,
86 RK_CLRSETBITS(0xffff,
87 (2 << 0) | (2 << 3) |
88 (2 << 6) | (2 << 9) | (2 << 12)));
89 write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1));
90
91 /* And now set the multiplexor to enable SDMMC0. */
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070092 write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC);
93}
huang lina6dbfb52016-03-02 18:38:40 +080094
Xing Zheng96fbc312016-05-19 11:39:20 +080095static void configure_codec(void)
96{
97 write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0);
98 write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK);
99
100 /* AUDIO IO domain 1.8V voltage selection */
101 write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1));
102
103 /* CPU1_P1.8V_AUDIO_PWREN for P1.8_AUDIO */
104 gpio_output(GPIO(0, A, 2), 1);
105
106 /* set CPU1_SPK_PA_EN output */
107 gpio_output(GPIO(1, A, 2), 0);
108
109 rkclk_configure_i2s(12288000);
110}
111
Lin Huangb497b482016-03-31 18:44:13 +0800112static void configure_display(void)
113{
114 /* set pinmux for edp HPD*/
115 gpio_input_pulldown(GPIO(4, C, 7));
116 write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
117
118 gpio_output(GPIO(4, D, 3), 1); /* CPU3_EDP_VDDEN for P3.3V_DISP */
119}
120
huang lina6dbfb52016-03-02 18:38:40 +0800121static void mainboard_init(device_t dev)
122{
Vadim Bendebury1e80ab32016-03-28 00:44:54 -0700123 configure_sdmmc();
Lin Huang2f7ed8d2016-04-08 18:56:20 +0800124 configure_emmc();
Xing Zheng96fbc312016-05-19 11:39:20 +0800125 configure_codec();
Lin Huangb497b482016-03-31 18:44:13 +0800126 configure_display();
127}
128
129static void enable_backlight_booster(void)
130{
131 const struct {
132 uint8_t reg;
133 uint8_t value;
134 } i2c_writes[] = {
135 {1, 0x84},
136 {1, 0x85},
137 {0, 0x26}
138 };
139 int i;
140 const int booster_i2c_port = 0;
141 uint8_t i2c_buf[2];
142 struct i2c_seg i2c_command = { .read = 0, .chip = 0x2c,
143 .buf = i2c_buf, .len = sizeof(i2c_buf)
144 };
145
146 /*
147 * This function is called on Gru right after BL_EN is asserted. It
148 * takes time for the switcher chip to come online, let's wait a bit
149 * to let the voltage settle, so that the chip can be accessed.
150 */
151 udelay(1000);
152
153 /* Select pinmux for i2c0, which is the display backlight booster. */
154 write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA);
155 write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL);
156 i2c_init(0, 100*KHz);
157
158 for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) {
159 i2c_buf[0] = i2c_writes[i].reg;
160 i2c_buf[1] = i2c_writes[i].value;
161 i2c_transfer(booster_i2c_port, &i2c_command, 1);
162 }
163}
164
165void mainboard_power_on_backlight(void)
166{
167 gpio_output(GPIO(1, C, 1), 1); /* BL_EN */
168
169 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
170 enable_backlight_booster();
huang lina6dbfb52016-03-02 18:38:40 +0800171}
172
173static void mainboard_enable(device_t dev)
174{
175 dev->ops->init = &mainboard_init;
176}
177
178struct chip_operations mainboard_ops = {
179 .name = CONFIG_MAINBOARD_PART_NUMBER,
180 .enable_dev = mainboard_enable,
181};