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huang lina6dbfb52016-03-02 18:38:40 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070017#include <boardid.h>
Lin Huangb497b482016-03-31 18:44:13 +080018#include <delay.h>
huang lina6dbfb52016-03-02 18:38:40 +080019#include <device/device.h>
Lin Huangb497b482016-03-31 18:44:13 +080020#include <device/i2c.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070021#include <gpio.h>
Lin Huang5a4be8a2016-05-17 15:45:53 +080022#include <soc/bl31_plat_params.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070023#include <soc/clock.h>
Lin Huangb497b482016-03-31 18:44:13 +080024#include <soc/display.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070025#include <soc/grf.h>
Lin Huangb497b482016-03-31 18:44:13 +080026#include <soc/i2c.h>
Liangfeng Wu76655cb2016-05-26 16:06:58 +080027#include <soc/usb.h>
Simon Glassbc679bc2016-06-19 16:09:21 -060028#include <vendorcode/google/chromeos/chromeos.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070029
Vadim Bendebury993dbe12016-05-22 15:53:37 -070030#include "board.h"
31
Lin Huang2f7ed8d2016-04-08 18:56:20 +080032static void configure_emmc(void)
33{
34 /* Host controller does not support programmable clock generator.
35 * If we don't do this setting, when we use phy to control the
36 * emmc clock(when clock exceed 50MHz), it will get wrong clock.
37 *
38 * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register.
39 * Please search "_CON11[7:0]" to locate register description.
40 */
41 write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
42
43 rkclk_configure_emmc();
44}
45
Lin Huang5a4be8a2016-05-17 15:45:53 +080046static void register_reset_to_bl31(void)
47{
48 static struct bl31_gpio_param param_reset = {
49 .h = {
50 .type = PARAM_RESET,
51 },
52 .gpio = {
53 .polarity = 1,
54 },
55 };
56
57 /* gru/kevin reset pin: gpio0b3 */
58 param_reset.gpio.index = GET_GPIO_NUM(GPIO_RESET),
59
60 register_bl31_param(&param_reset.h);
61}
62
Lin Huang9a5c4fe2016-05-19 11:11:23 +080063static void register_poweroff_to_bl31(void)
64{
65 static struct bl31_gpio_param param_poweroff = {
66 .h = {
67 .type = PARAM_POWEROFF,
68 },
69 .gpio = {
70 .polarity = 1,
71 },
72 };
73
74 /*
75 * gru/kevin power off pin: gpio1a6,
76 * reuse with tsadc int pin, so iomux need set back to
77 * gpio in BL31 and depthcharge before you setting this gpio
78 */
79 param_poweroff.gpio.index = GET_GPIO_NUM(GPIO_POWEROFF),
80
81 register_bl31_param(&param_poweroff.h);
82}
83
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070084static void configure_sdmmc(void)
85{
86 gpio_output(GPIO(4, D, 5), 1); /* SDMMC_PWR_EN */
87 gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */
Vadim Bendebury2832c412016-05-11 15:03:44 +080088
89 /* SDMMC_DET_L is different on Kevin board revision 0. */
90 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && (board_id() == 0))
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070091 gpio_input(GPIO(4, D, 2));
Vadim Bendebury2832c412016-05-11 15:03:44 +080092 else
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070093 gpio_input(GPIO(4, D, 0));
Vadim Bendebury2832c412016-05-11 15:03:44 +080094
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070095 gpio_output(GPIO(2, D, 4), 0); /* Keep the max voltage */
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070096
Vadim Bendeburyad6ee022016-05-12 16:54:00 +080097 /*
98 * The SD card on this board is connected to port SDMMC0, which is
99 * multiplexed with GPIO4B pins 0..5.
100 *
101 * Disable all pullups on these pins. For pullup configuration
102 * register layout stacks banks 2 through 4 together, hence [2] means
103 * group 4, [1] means bank B. This register is described on page 342
104 * of section 1 of the TRM.
105 *
106 * Each GPIO pin's pull config takes two bits, writing zero to the
107 * field disables pull ups/downs, as described on page 342 of rk3399
108 * TRM Version 0.3 Part 1.
109 */
110 write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0));
111
112 /*
113 * Set all outputs' drive strength to 8 mA. Group 4 bank B driver
114 * strength requires three bits per pin. Value of 2 written in that
115 * three bit field means '8 mA', as deduced from the kernel code.
116 *
117 * Thus the six pins involved in SDMMC interface require 18 bits to
118 * configure drive strength, but each 32 bit register provides only 16
119 * bits for this setting, this covers 5 pins fully and one bit from
120 * the 6th pin. Two more bits spill over to the next register. This is
121 * described on page 378 of rk3399 TRM Version 0.3 Part 1.
122 */
123 write32(&rk3399_grf->gpio4b_e01,
124 RK_CLRSETBITS(0xffff,
125 (2 << 0) | (2 << 3) |
126 (2 << 6) | (2 << 9) | (2 << 12)));
127 write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1));
128
129 /* And now set the multiplexor to enable SDMMC0. */
Vadim Bendebury1e80ab32016-03-28 00:44:54 -0700130 write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC);
131}
huang lina6dbfb52016-03-02 18:38:40 +0800132
Xing Zheng96fbc312016-05-19 11:39:20 +0800133static void configure_codec(void)
134{
135 write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0);
136 write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK);
137
138 /* AUDIO IO domain 1.8V voltage selection */
139 write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1));
140
141 /* CPU1_P1.8V_AUDIO_PWREN for P1.8_AUDIO */
142 gpio_output(GPIO(0, A, 2), 1);
143
144 /* set CPU1_SPK_PA_EN output */
145 gpio_output(GPIO(1, A, 2), 0);
146
147 rkclk_configure_i2s(12288000);
148}
149
Lin Huangb497b482016-03-31 18:44:13 +0800150static void configure_display(void)
151{
152 /* set pinmux for edp HPD*/
153 gpio_input_pulldown(GPIO(4, C, 7));
154 write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
155
156 gpio_output(GPIO(4, D, 3), 1); /* CPU3_EDP_VDDEN for P3.3V_DISP */
157}
158
Liangfeng Wu76655cb2016-05-26 16:06:58 +0800159static void setup_usb(void)
160{
Julius Werner1c8491c2016-08-15 17:58:05 -0700161 /* A few magic PHY tuning values that improve eye diagram amplitude
162 * and make it extra sure we get reliable communication in firmware. */
163 /* Set max ODT compensation voltage and current tuning reference. */
164 write32(&rk3399_grf->usbphy0_ctrl[3], 0x0fff02e3);
165 write32(&rk3399_grf->usbphy1_ctrl[3], 0x0fff02e3);
166 /* Set max pre-emphasis level, only on Kevin PHY0. */
167 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
168 write32(&rk3399_grf->usbphy0_ctrl[12], 0xffff00a7);
169
Julius Werner785ff1b2016-08-03 19:18:39 -0700170 setup_usb_otg0();
171 setup_usb_otg1();
Liangfeng Wu76655cb2016-05-26 16:06:58 +0800172}
173
huang lina6dbfb52016-03-02 18:38:40 +0800174static void mainboard_init(device_t dev)
175{
Vadim Bendebury1e80ab32016-03-28 00:44:54 -0700176 configure_sdmmc();
Lin Huang2f7ed8d2016-04-08 18:56:20 +0800177 configure_emmc();
Xing Zheng96fbc312016-05-19 11:39:20 +0800178 configure_codec();
Lin Huangb497b482016-03-31 18:44:13 +0800179 configure_display();
Liangfeng Wu76655cb2016-05-26 16:06:58 +0800180 setup_usb();
Lin Huang5a4be8a2016-05-17 15:45:53 +0800181 register_reset_to_bl31();
Lin Huang9a5c4fe2016-05-19 11:11:23 +0800182 register_poweroff_to_bl31();
Lin Huangb497b482016-03-31 18:44:13 +0800183}
184
185static void enable_backlight_booster(void)
186{
187 const struct {
188 uint8_t reg;
189 uint8_t value;
190 } i2c_writes[] = {
191 {1, 0x84},
192 {1, 0x85},
193 {0, 0x26}
194 };
195 int i;
196 const int booster_i2c_port = 0;
197 uint8_t i2c_buf[2];
198 struct i2c_seg i2c_command = { .read = 0, .chip = 0x2c,
199 .buf = i2c_buf, .len = sizeof(i2c_buf)
200 };
201
202 /*
203 * This function is called on Gru right after BL_EN is asserted. It
204 * takes time for the switcher chip to come online, let's wait a bit
205 * to let the voltage settle, so that the chip can be accessed.
206 */
207 udelay(1000);
208
209 /* Select pinmux for i2c0, which is the display backlight booster. */
210 write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA);
211 write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL);
212 i2c_init(0, 100*KHz);
213
214 for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) {
215 i2c_buf[0] = i2c_writes[i].reg;
216 i2c_buf[1] = i2c_writes[i].value;
217 i2c_transfer(booster_i2c_port, &i2c_command, 1);
218 }
219}
220
221void mainboard_power_on_backlight(void)
222{
223 gpio_output(GPIO(1, C, 1), 1); /* BL_EN */
224
Julius Werner5e6771b2016-07-29 16:15:04 -0700225 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() == 0)
Lin Huangb497b482016-03-31 18:44:13 +0800226 enable_backlight_booster();
huang lina6dbfb52016-03-02 18:38:40 +0800227}
228
229static void mainboard_enable(device_t dev)
230{
231 dev->ops->init = &mainboard_init;
232}
233
234struct chip_operations mainboard_ops = {
235 .name = CONFIG_MAINBOARD_PART_NUMBER,
236 .enable_dev = mainboard_enable,
237};