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huang lina6dbfb52016-03-02 18:38:40 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070017#include <boardid.h>
Lin Huangb497b482016-03-31 18:44:13 +080018#include <delay.h>
huang lina6dbfb52016-03-02 18:38:40 +080019#include <device/device.h>
Lin Huangb497b482016-03-31 18:44:13 +080020#include <device/i2c.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070021#include <gpio.h>
22#include <soc/clock.h>
Lin Huangb497b482016-03-31 18:44:13 +080023#include <soc/display.h>
Shunqian Zheng462e1412016-05-02 10:27:30 +080024#include <soc/emmc.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070025#include <soc/grf.h>
Lin Huangb497b482016-03-31 18:44:13 +080026#include <soc/i2c.h>
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070027
Lin Huang2f7ed8d2016-04-08 18:56:20 +080028static void configure_emmc(void)
29{
30 /* Host controller does not support programmable clock generator.
31 * If we don't do this setting, when we use phy to control the
32 * emmc clock(when clock exceed 50MHz), it will get wrong clock.
33 *
34 * Refer to TRM V0.3 Part 1 Chapter 15 PAGE 782 for this register.
35 * Please search "_CON11[7:0]" to locate register description.
36 */
37 write32(&rk3399_grf->emmccore_con[11], RK_CLRSETBITS(0xff, 0));
38
39 rkclk_configure_emmc();
Shunqian Zheng462e1412016-05-02 10:27:30 +080040
41 enable_emmc_clk();
Lin Huang2f7ed8d2016-04-08 18:56:20 +080042}
43
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070044static void configure_sdmmc(void)
45{
46 gpio_output(GPIO(4, D, 5), 1); /* SDMMC_PWR_EN */
47 gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */
Vadim Bendebury2832c412016-05-11 15:03:44 +080048
49 /* SDMMC_DET_L is different on Kevin board revision 0. */
50 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && (board_id() == 0))
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070051 gpio_input(GPIO(4, D, 2));
Vadim Bendebury2832c412016-05-11 15:03:44 +080052 else
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070053 gpio_input(GPIO(4, D, 0));
Vadim Bendebury2832c412016-05-11 15:03:44 +080054
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070055 gpio_output(GPIO(2, D, 4), 0); /* Keep the max voltage */
Vadim Bendebury8e8a00c2016-04-22 12:25:07 -070056
Vadim Bendeburyad6ee022016-05-12 16:54:00 +080057 /*
58 * The SD card on this board is connected to port SDMMC0, which is
59 * multiplexed with GPIO4B pins 0..5.
60 *
61 * Disable all pullups on these pins. For pullup configuration
62 * register layout stacks banks 2 through 4 together, hence [2] means
63 * group 4, [1] means bank B. This register is described on page 342
64 * of section 1 of the TRM.
65 *
66 * Each GPIO pin's pull config takes two bits, writing zero to the
67 * field disables pull ups/downs, as described on page 342 of rk3399
68 * TRM Version 0.3 Part 1.
69 */
70 write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0));
71
72 /*
73 * Set all outputs' drive strength to 8 mA. Group 4 bank B driver
74 * strength requires three bits per pin. Value of 2 written in that
75 * three bit field means '8 mA', as deduced from the kernel code.
76 *
77 * Thus the six pins involved in SDMMC interface require 18 bits to
78 * configure drive strength, but each 32 bit register provides only 16
79 * bits for this setting, this covers 5 pins fully and one bit from
80 * the 6th pin. Two more bits spill over to the next register. This is
81 * described on page 378 of rk3399 TRM Version 0.3 Part 1.
82 */
83 write32(&rk3399_grf->gpio4b_e01,
84 RK_CLRSETBITS(0xffff,
85 (2 << 0) | (2 << 3) |
86 (2 << 6) | (2 << 9) | (2 << 12)));
87 write32(&rk3399_grf->gpio4b_e2, RK_CLRSETBITS(3, 1));
88
89 /* And now set the multiplexor to enable SDMMC0. */
Vadim Bendebury1e80ab32016-03-28 00:44:54 -070090 write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC);
91}
huang lina6dbfb52016-03-02 18:38:40 +080092
Lin Huangb497b482016-03-31 18:44:13 +080093static void configure_display(void)
94{
95 /* set pinmux for edp HPD*/
96 gpio_input_pulldown(GPIO(4, C, 7));
97 write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
98
99 gpio_output(GPIO(4, D, 3), 1); /* CPU3_EDP_VDDEN for P3.3V_DISP */
100}
101
huang lina6dbfb52016-03-02 18:38:40 +0800102static void mainboard_init(device_t dev)
103{
Vadim Bendebury1e80ab32016-03-28 00:44:54 -0700104 configure_sdmmc();
Lin Huang2f7ed8d2016-04-08 18:56:20 +0800105 configure_emmc();
Lin Huangb497b482016-03-31 18:44:13 +0800106 configure_display();
107}
108
109static void enable_backlight_booster(void)
110{
111 const struct {
112 uint8_t reg;
113 uint8_t value;
114 } i2c_writes[] = {
115 {1, 0x84},
116 {1, 0x85},
117 {0, 0x26}
118 };
119 int i;
120 const int booster_i2c_port = 0;
121 uint8_t i2c_buf[2];
122 struct i2c_seg i2c_command = { .read = 0, .chip = 0x2c,
123 .buf = i2c_buf, .len = sizeof(i2c_buf)
124 };
125
126 /*
127 * This function is called on Gru right after BL_EN is asserted. It
128 * takes time for the switcher chip to come online, let's wait a bit
129 * to let the voltage settle, so that the chip can be accessed.
130 */
131 udelay(1000);
132
133 /* Select pinmux for i2c0, which is the display backlight booster. */
134 write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA);
135 write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL);
136 i2c_init(0, 100*KHz);
137
138 for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) {
139 i2c_buf[0] = i2c_writes[i].reg;
140 i2c_buf[1] = i2c_writes[i].value;
141 i2c_transfer(booster_i2c_port, &i2c_command, 1);
142 }
143}
144
145void mainboard_power_on_backlight(void)
146{
147 gpio_output(GPIO(1, C, 1), 1); /* BL_EN */
148
149 if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
150 enable_backlight_booster();
huang lina6dbfb52016-03-02 18:38:40 +0800151}
152
153static void mainboard_enable(device_t dev)
154{
155 dev->ops->init = &mainboard_init;
156}
157
158struct chip_operations mainboard_ops = {
159 .name = CONFIG_MAINBOARD_PART_NUMBER,
160 .enable_dev = mainboard_enable,
161};