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Angel Pons182dbde2020-04-02 23:49:05 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Aaron Durbin76c37002012-10-30 09:03:43 -05002
3#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
4#define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
5
Furquan Shaikh76cedd22020-05-02 10:24:23 -07006#include <acpi/acpi.h>
Aaron Durbinda5f5092016-07-13 23:23:16 -05007
Aaron Durbinb0f81512016-07-25 21:31:41 -05008#define CROS_GPIO_DEVICE_NAME "LynxPoint"
9
Aaron Durbin76c37002012-10-30 09:03:43 -050010/*
11 * Lynx Point PCH PCI Devices:
12 *
13 * Bus 0:Device 31:Function 0 LPC Controller1
14 * Bus 0:Device 31:Function 2 SATA Controller #1
15 * Bus 0:Device 31:Function 3 SMBus Controller
16 * Bus 0:Device 31:Function 5 SATA Controller #22
17 * Bus 0:Device 31:Function 6 Thermal Subsystem
18 * Bus 0:Device 29:Function 03 USB EHCI Controller #1
19 * Bus 0:Device 26:Function 03 USB EHCI Controller #2
20 * Bus 0:Device 28:Function 0 PCI Express* Port 1
21 * Bus 0:Device 28:Function 1 PCI Express Port 2
22 * Bus 0:Device 28:Function 2 PCI Express Port 3
23 * Bus 0:Device 28:Function 3 PCI Express Port 4
24 * Bus 0:Device 28:Function 4 PCI Express Port 5
25 * Bus 0:Device 28:Function 5 PCI Express Port 6
26 * Bus 0:Device 28:Function 6 PCI Express Port 7
27 * Bus 0:Device 28:Function 7 PCI Express Port 8
Duncan Laurie5cc51c02013-03-07 14:06:43 -080028 * Bus 0:Device 27:Function 0 Intel High Definition Audio Controller
Aaron Durbin76c37002012-10-30 09:03:43 -050029 * Bus 0:Device 25:Function 0 Gigabit Ethernet Controller
Duncan Laurie5cc51c02013-03-07 14:06:43 -080030 * Bus 0:Device 22:Function 0 Intel Management Engine Interface #1
Aaron Durbin76c37002012-10-30 09:03:43 -050031 * Bus 0:Device 22:Function 1 Intel Management Engine Interface #2
32 * Bus 0:Device 22:Function 2 IDE-R
33 * Bus 0:Device 22:Function 3 KT
34 * Bus 0:Device 20:Function 0 xHCI Controller
35*/
36
Aaron Durbin76c37002012-10-30 09:03:43 -050037/* PCH stepping values for LPC device */
Duncan Laurie4bc107b2013-06-24 13:14:44 -070038#define LPT_H_STEP_B0 0x02
39#define LPT_H_STEP_C0 0x03
40#define LPT_H_STEP_C1 0x04
41#define LPT_H_STEP_C2 0x05
42#define LPT_LP_STEP_B0 0x02
43#define LPT_LP_STEP_B1 0x03
44#define LPT_LP_STEP_B2 0x04
Aaron Durbin76c37002012-10-30 09:03:43 -050045
Aaron Durbin76c37002012-10-30 09:03:43 -050046#define SMBUS_SLAVE_ADDR 0x24
Aaron Durbin76c37002012-10-30 09:03:43 -050047
Julius Wernercd49cce2019-03-05 16:53:33 -080048#if CONFIG(INTEL_LYNXPOINT_LP)
Duncan Laurie7922b462013-03-08 16:34:33 -080049#define DEFAULT_PMBASE 0x1000
50#define DEFAULT_GPIOBASE 0x1400
Duncan Laurie045f1532012-12-17 11:29:10 -080051#define DEFAULT_GPIOSIZE 0x400
52#else
Duncan Laurie7922b462013-03-08 16:34:33 -080053#define DEFAULT_PMBASE 0x500
Duncan Laurie045f1532012-12-17 11:29:10 -080054#define DEFAULT_GPIOBASE 0x480
55#define DEFAULT_GPIOSIZE 0x80
56#endif
57
Peter Lemenkov7b428112018-10-23 11:12:46 +020058#include <southbridge/intel/common/rcba.h>
Aaron Durbin76c37002012-10-30 09:03:43 -050059
60#ifndef __ACPI__
Aaron Durbin76c37002012-10-30 09:03:43 -050061
Angel Ponsf5ec52a2021-03-17 11:24:59 +010062#if CONFIG(INTEL_LYNXPOINT_LP)
63#define MAX_USB2_PORTS 10
64#define MAX_USB3_PORTS 4
65#else
66#define MAX_USB2_PORTS 14
67#define MAX_USB3_PORTS 6
68#endif
69
70/* There are 8 OC pins */
71#define USB_OC_PIN_SKIP 8
72
73enum usb2_port_location {
74 USB_PORT_SKIP = 0,
75 USB_PORT_BACK_PANEL,
76 USB_PORT_FRONT_PANEL,
77 USB_PORT_DOCK,
78 USB_PORT_MINI_PCIE,
79 USB_PORT_FLEX,
80 USB_PORT_INTERNAL,
81};
82
83/*
84 * USB port length is in MRC format: binary-coded decimal length in tenths of an inch.
85 * 4.2 inches -> 0x0042
86 * 12.7 inches -> 0x0127
87 */
88struct usb2_port_config {
89 uint16_t length;
90 bool enable;
91 unsigned short oc_pin;
92 enum usb2_port_location location;
93};
94
95struct usb3_port_config {
96 bool enable;
97 unsigned int oc_pin;
98};
99
100/* Mainboard-specific USB configuration */
101extern const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS];
102extern const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS];
103
Angel Ponsd9f1b042020-09-02 20:19:15 +0200104static inline int pch_is_lp(void)
105{
106 return CONFIG(INTEL_LYNXPOINT_LP);
107}
108
Angel Pons31739932020-07-03 23:14:40 +0200109/* PCH platform types, safe for MRC consumption */
110enum pch_platform_type {
111 PCH_TYPE_MOBILE = 0,
112 PCH_TYPE_DESKTOP = 1, /* or server */
113 PCH_TYPE_ULT = 5,
114};
115
Elyes HAOUAS38f1d132018-09-17 08:44:18 +0200116void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
117void usb_ehci_disable(pci_devfn_t dev);
118void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
Duncan Laurie911cedf2013-07-30 16:05:55 -0700119void usb_xhci_route_all(void);
Aaron Durbin239c2e82012-12-19 11:31:17 -0600120
Angel Pons31739932020-07-03 23:14:40 +0200121enum pch_platform_type get_pch_platform_type(void);
Duncan Laurie5cc51c02013-03-07 14:06:43 -0800122int pch_silicon_revision(void);
Tristan Corrickd3f01b22018-12-06 22:46:58 +1300123int pch_silicon_id(void);
Duncan Laurie1ad55642013-03-07 14:08:04 -0800124u16 get_pmbase(void);
125u16 get_gpiobase(void);
Duncan Laurie55cdf552013-03-08 16:01:44 -0800126
127/* Power Management register handling in pmutil.c */
128/* PM1_CNT */
129void enable_pm1_control(u32 mask);
130void disable_pm1_control(u32 mask);
131/* PM1 */
132u16 clear_pm1_status(void);
Aaron Durbind6d6db32013-03-27 21:13:02 -0500133void enable_pm1(u16 events);
Duncan Laurie55cdf552013-03-08 16:01:44 -0800134u32 clear_smi_status(void);
135/* SMI */
136void enable_smi(u32 mask);
137void disable_smi(u32 mask);
138/* ALT_GP_SMI */
139u32 clear_alt_smi_status(void);
140void enable_alt_smi(u32 mask);
141/* TCO */
142u32 clear_tco_status(void);
143void enable_tco_sci(void);
144/* GPE0 */
145u32 clear_gpe_status(void);
146void clear_gpe_enable(void);
147void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4);
148void disable_all_gpe(void);
149void enable_gpe(u32 mask);
150void disable_gpe(u32 mask);
151
Elyes HAOUAS38f1d132018-09-17 08:44:18 +0200152void pch_enable(struct device *dev);
153void pch_disable_devfn(struct device *dev);
Duncan Laurie8584b222013-02-15 13:52:28 -0800154void pch_log_state(void);
Duncan Lauried7cb8d02013-05-15 15:03:57 -0700155void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
Duncan Laurie8584b222013-02-15 13:52:28 -0800156
Kyösti Mälkki12b121c2019-08-18 16:33:39 +0300157void enable_usb_bar(void);
Angel Pons30931f52021-03-12 13:06:45 +0100158void early_pch_init(void);
Stefan Reinauer779e1782013-10-07 16:29:54 -0700159void pch_enable_lpc(void);
Tristan Corrick655ef612018-10-31 02:26:19 +1300160void mainboard_config_superio(void);
Angel Pons6e1c4712020-07-03 13:05:10 +0200161void mainboard_config_rcba(void);
Aaron Durbin76c37002012-10-30 09:03:43 -0500162
163#define MAINBOARD_POWER_OFF 0
164#define MAINBOARD_POWER_ON 1
165#define MAINBOARD_POWER_KEEP 2
166
Aaron Durbin76c37002012-10-30 09:03:43 -0500167/* PCI Configuration Space (D30:F0): PCI2PCI */
168#define PSTS 0x06
169#define SMLT 0x1b
170#define SECSTS 0x1e
171#define INTR 0x3c
Aaron Durbin76c37002012-10-30 09:03:43 -0500172
Duncan Laurie98c40622013-05-21 16:37:40 -0700173/* Power Management Control and Status */
174#define PCH_PCS 0x84
175#define PCH_PCS_PS_D3HOT 3
176
Angel Pons30392ae2020-07-12 01:06:23 +0200177/* SerialIO */
178#define PCH_DEVFN_SDMA PCI_DEVFN(0x15, 0)
179#define PCH_DEVFN_I2C0 PCI_DEVFN(0x15, 1)
180#define PCH_DEVFN_I2C1 PCI_DEVFN(0x15, 2)
181#define PCH_DEVFN_SPI0 PCI_DEVFN(0x15, 3)
182#define PCH_DEVFN_SPI1 PCI_DEVFN(0x15, 4)
183#define PCH_DEVFN_UART0 PCI_DEVFN(0x15, 5)
184#define PCH_DEVFN_UART1 PCI_DEVFN(0x15, 6)
185
186#define PCH_DEVFN_SDIO PCI_DEVFN(0x17, 0)
187
Aaron Durbin76c37002012-10-30 09:03:43 -0500188#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
189#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
Duncan Laurie2d9d39a2013-05-29 15:27:55 -0700190#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0)
Aaron Durbin76c37002012-10-30 09:03:43 -0500191#define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
192#define PCH_PCIE_DEV_SLOT 28
193
194/* PCI Configuration Space (D31:F0): LPC */
195#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
196#define SERIRQ_CNTL 0x64
197
198#define GEN_PMCON_1 0xa0
Angel Pons35605d62021-04-24 11:54:01 +0200199#define SMI_LOCK (1 << 4)
Aaron Durbin76c37002012-10-30 09:03:43 -0500200#define GEN_PMCON_2 0xa2
Angel Pons35605d62021-04-24 11:54:01 +0200201#define SYSTEM_RESET_STS (1 << 4)
202#define THERMTRIP_STS (1 << 3)
203#define SYSPWR_FLR (1 << 1)
204#define PWROK_FLR (1 << 0)
Aaron Durbin76c37002012-10-30 09:03:43 -0500205#define GEN_PMCON_3 0xa4
Angel Pons35605d62021-04-24 11:54:01 +0200206#define SUS_PWR_FLR (1 << 14)
207#define GEN_RST_STS (1 << 9)
208#define RTC_BATTERY_DEAD (1 << 2)
209#define PWR_FLR (1 << 1)
210#define SLEEP_AFTER_POWER_FAIL (1 << 0)
Aaron Durbinb9ea8b32012-11-02 09:10:30 -0500211#define PMIR 0xac
Angel Pons8963f7d2020-10-24 12:20:28 +0200212#define PMIR_CF9LOCK (1 << 31)
Aaron Durbinb9ea8b32012-11-02 09:10:30 -0500213#define PMIR_CF9GR (1 << 20)
Aaron Durbin76c37002012-10-30 09:03:43 -0500214
215/* GEN_PMCON_3 bits */
216#define RTC_BATTERY_DEAD (1 << 2)
217#define RTC_POWER_FAILED (1 << 1)
218#define SLEEP_AFTER_POWER_FAIL (1 << 0)
219
220#define PMBASE 0x40
221#define ACPI_CNTL 0x44
Paul Menzel373a20c2013-05-03 12:17:02 +0200222#define ACPI_EN (1 << 7)
Aaron Durbin76c37002012-10-30 09:03:43 -0500223#define BIOS_CNTL 0xDC
224#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
225#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
226#define GPIO_ROUT 0xb8
227
228#define PIRQA_ROUT 0x60
229#define PIRQB_ROUT 0x61
230#define PIRQC_ROUT 0x62
231#define PIRQD_ROUT 0x63
232#define PIRQE_ROUT 0x68
233#define PIRQF_ROUT 0x69
234#define PIRQG_ROUT 0x6A
235#define PIRQH_ROUT 0x6B
236
237#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
238#define LPC_EN 0x82 /* LPC IF Enables Register */
239#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
240#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
241#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
242#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
243#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
244#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
245#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
246#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
247#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
248#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
Matt DeVilliera51e3792018-03-04 01:44:15 -0600249#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */
Angel Pons1afe4692021-02-10 13:41:04 +0100250#define LPC_HnBDF(n) (0x70 + (n) * 2) /* HPET n bus/dev/fn */
Aaron Durbin76c37002012-10-30 09:03:43 -0500251#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
252#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
253#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
254#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
Aaron Durbin6f561af2012-12-19 14:38:01 -0600255#define LGMR 0x98 /* LPC Generic Memory Range */
Aaron Durbin76c37002012-10-30 09:03:43 -0500256
Angel Pons0b3512b2020-08-10 13:02:20 +0200257/* PCI Configuration Space (D31:F2): SATA */
Aaron Durbin76c37002012-10-30 09:03:43 -0500258#define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
259#define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
Angel Pons93859e32020-11-02 12:08:50 +0100260
Aaron Durbin76c37002012-10-30 09:03:43 -0500261#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
262#define IDE_DECODE_ENABLE (1 << 15)
Aaron Durbin76c37002012-10-30 09:03:43 -0500263#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
264
Aaron Durbin76c37002012-10-30 09:03:43 -0500265#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
266#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
267#define SATA_SP 0xd0 /* Scratchpad */
268
269/* SATA IOBP Registers */
270#define SATA_IOBP_SP0G3IR 0xea000151
271#define SATA_IOBP_SP1G3IR 0xea000051
Angel Pons244a4252020-11-05 10:42:20 +0100272#define SATA_IOBP_SP0DTLE_DATA 0xea002750
273#define SATA_IOBP_SP0DTLE_EDGE 0xea002754
274#define SATA_IOBP_SP1DTLE_DATA 0xea002550
275#define SATA_IOBP_SP1DTLE_EDGE 0xea002554
Shawn Nematbakhsh28752272013-08-13 10:45:21 -0700276
277#define SATA_DTLE_MASK 0xF
278#define SATA_DTLE_DATA_SHIFT 24
279#define SATA_DTLE_EDGE_SHIFT 16
Aaron Durbin76c37002012-10-30 09:03:43 -0500280
Duncan Laurie1f529082013-07-30 15:53:45 -0700281/* EHCI PCI Registers */
282#define EHCI_PWR_CTL_STS 0x54
283#define PWR_CTL_SET_MASK 0x3
284#define PWR_CTL_SET_D0 0x0
285#define PWR_CTL_SET_D3 0x3
286#define PWR_CTL_ENABLE_PME (1 << 8)
Duncan Laurie0bf1dea2013-08-13 13:32:28 -0700287#define PWR_CTL_STATUS_PME (1 << 15)
Duncan Laurie1f529082013-07-30 15:53:45 -0700288
289/* EHCI Memory Registers */
290#define EHCI_USB_CMD 0x20
291#define EHCI_USB_CMD_RUN (1 << 0)
292#define EHCI_USB_CMD_PSE (1 << 4)
293#define EHCI_USB_CMD_ASE (1 << 5)
Angel Pons1afe4692021-02-10 13:41:04 +0100294#define EHCI_PORTSC(port) (0x64 + (port) * 4)
Duncan Laurie1f529082013-07-30 15:53:45 -0700295#define EHCI_PORTSC_ENABLED (1 << 2)
296#define EHCI_PORTSC_SUSPEND (1 << 7)
297
298/* XHCI PCI Registers */
299#define XHCI_PWR_CTL_STS 0x74
300#define XHCI_USB2PR 0xd0
301#define XHCI_USB2PRM 0xd4
302#define XHCI_USB2PR_HCSEL 0x7fff
303#define XHCI_USB3PR 0xd8
304#define XHCI_USB3PR_SSEN 0x3f
305#define XHCI_USB3PRM 0xdc
306#define XHCI_USB3FUS 0xe0
307#define XHCI_USB3FUS_SS_MASK 3
308#define XHCI_USB3FUS_SS_SHIFT 3
309#define XHCI_USB3PDO 0xe8
310
311/* XHCI Memory Registers */
Angel Pons1afe4692021-02-10 13:41:04 +0100312#define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + ((port) * 0x10))
Duncan Laurie1f529082013-07-30 15:53:45 -0700313#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
314#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
315#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
316#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
317#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200318#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
319#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
Angel Pons8963f7d2020-10-24 12:20:28 +0200320#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
Duncan Laurie1f529082013-07-30 15:53:45 -0700321#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
322#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
323#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
324#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
325#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
Duncan Laurie2d9d39a2013-05-29 15:27:55 -0700326
Duncan Laurie71346c02013-01-10 13:20:40 -0800327/* Serial IO IOBP Registers */
328#define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */
329#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5)
330#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4)
331#define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */
332#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13)
333#define SIO_IOBP_GPIODF 0xcb000154
334#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4)
335#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3)
336#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2)
337#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1)
338#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0)
339#define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */
340#define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */
341#define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */
342#define SIO_IOBP_PORTCTRL5 0xcb000258 /* SPI0 D21:F3 */
343#define SIO_IOBP_PORTCTRL6 0xcb000260 /* SPI1 D21:F4 */
344#define SIO_IOBP_PORTCTRL7 0xcb000268 /* UART0 D21:F5 */
345#define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */
Duncan Laurieb39ba2e2013-03-22 11:21:14 -0700346#define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8))
Duncan Laurie71346c02013-01-10 13:20:40 -0800347/* PORTCTRL 2-8 have the same layout */
348#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21)
349#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20)
350#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18)
351#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2)
Duncan Laurieb39ba2e2013-03-22 11:21:14 -0700352#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1)
Duncan Laurie71346c02013-01-10 13:20:40 -0800353#define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */
354#define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */
355#define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */
356#define SIO_IOBP_FUNCDIS3 0xce00aac7 /* SPI0 D21:F3 */
357#define SIO_IOBP_FUNCDIS4 0xce00ab07 /* SPI1 D21:F4 */
358#define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */
359#define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */
360#define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */
361#define SIO_IOBP_FUNCDIS_DIS (1 << 8)
362
Duncan Laurieb39ba2e2013-03-22 11:21:14 -0700363/* Serial IO Devices */
364#define SIO_ID_SDMA 0 /* D21:F0 */
365#define SIO_ID_I2C0 1 /* D21:F1 */
366#define SIO_ID_I2C1 2 /* D21:F2 */
367#define SIO_ID_SPI0 3 /* D21:F3 */
368#define SIO_ID_SPI1 4 /* D21:F4 */
369#define SIO_ID_UART0 5 /* D21:F5 */
370#define SIO_ID_UART1 6 /* D21:F6 */
371#define SIO_ID_SDIO 7 /* D23:F0 */
372
Duncan Laurie98c40622013-05-21 16:37:40 -0700373#define SIO_REG_PPR_CLOCK 0x800
374#define SIO_REG_PPR_CLOCK_EN (1 << 0)
Duncan Laurieb39ba2e2013-03-22 11:21:14 -0700375#define SIO_REG_PPR_RST 0x804
376#define SIO_REG_PPR_RST_ASSERT 0x3
377#define SIO_REG_PPR_GEN 0x808
378#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2)
379#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3)
Angel Pons1afe4692021-02-10 13:41:04 +0100380#define SIO_REG_PPR_GEN_VOLTAGE(x) (((x) & 1) << 3)
Duncan Laurieb39ba2e2013-03-22 11:21:14 -0700381#define SIO_REG_AUTO_LTR 0x814
382
383#define SIO_REG_SDIO_PPR_GEN 0x1008
384#define SIO_REG_SDIO_PPR_SW_LTR 0x1010
385#define SIO_REG_SDIO_PPR_CMD12 0x3c
386#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30)
387
388#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */
389#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */
390#define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */
391#define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */
392
Aaron Durbin76c37002012-10-30 09:03:43 -0500393/* PCI Configuration Space (D31:F3): SMBus */
394#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
395#define SMB_BASE 0x20
396#define HOSTC 0x40
Aaron Durbin76c37002012-10-30 09:03:43 -0500397
398/* HOSTC bits */
399#define I2C_EN (1 << 2)
400#define SMB_SMI_EN (1 << 1)
401#define HST_EN (1 << 0)
402
Aaron Durbin76c37002012-10-30 09:03:43 -0500403/* Southbridge IO BARs */
404
405#define GPIOBASE 0x48
406
407#define PMBASE 0x40
408
Aaron Durbinc0254e62013-06-20 01:20:30 -0500409#define RPC 0x0400 /* 32bit */
Aaron Durbin76c37002012-10-30 09:03:43 -0500410#define RPFN 0x0404 /* 32bit */
411
412/* Root Port configuratinon space hide */
Angel Pons8963f7d2020-10-24 12:20:28 +0200413#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
Aaron Durbin76c37002012-10-30 09:03:43 -0500414/* Get the function number assigned to a Root Port */
415#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
416/* Set the function number for a Root Port */
417#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
418/* Root Port function number mask */
419#define RPFN_FNMASK(port) (7 << ((port) * 4))
420
421#define TRSR 0x1e00 /* 8bit */
422#define TRCR 0x1e10 /* 64bit */
423#define TWDR 0x1e18 /* 64bit */
424
425#define IOTR0 0x1e80 /* 64bit */
426#define IOTR1 0x1e88 /* 64bit */
427#define IOTR2 0x1e90 /* 64bit */
428#define IOTR3 0x1e98 /* 64bit */
429
430#define TCTL 0x3000 /* 8bit */
431
432#define NOINT 0
433#define INTA 1
434#define INTB 2
435#define INTC 3
436#define INTD 4
437
438#define DIR_IDR 12 /* Interrupt D Pin Offset */
439#define DIR_ICR 8 /* Interrupt C Pin Offset */
440#define DIR_IBR 4 /* Interrupt B Pin Offset */
441#define DIR_IAR 0 /* Interrupt A Pin Offset */
442
443#define PIRQA 0
444#define PIRQB 1
445#define PIRQC 2
446#define PIRQD 3
447#define PIRQE 4
448#define PIRQF 5
449#define PIRQG 6
450#define PIRQH 7
451
452/* IO Buffer Programming */
453#define IOBPIRI 0x2330
454#define IOBPD 0x2334
455#define IOBPS 0x2338
Duncan Laurie7302d1e2013-01-10 13:19:23 -0800456#define IOBPS_READY 0x0001
457#define IOBPS_TX_MASK 0x0006
458#define IOBPS_MASK 0xff00
459#define IOBPS_READ 0x0600
460#define IOBPS_WRITE 0x0700
461#define IOBPU 0x233a
462#define IOBPU_MAGIC 0xf000
Angel Ponsdfb29fd2021-04-19 15:58:21 +0200463#define IOBP_PCICFG_READ 0x0400
464#define IOBP_PCICFG_WRITE 0x0500
Aaron Durbin76c37002012-10-30 09:03:43 -0500465
466#define D31IP 0x3100 /* 32bit */
467#define D31IP_TTIP 24 /* Thermal Throttle Pin */
468#define D31IP_SIP2 20 /* SATA Pin 2 */
469#define D31IP_SMIP 12 /* SMBUS Pin */
470#define D31IP_SIP 8 /* SATA Pin */
471#define D30IP 0x3104 /* 32bit */
472#define D30IP_PIP 0 /* PCI Bridge Pin */
473#define D29IP 0x3108 /* 32bit */
474#define D29IP_E1P 0 /* EHCI #1 Pin */
475#define D28IP 0x310c /* 32bit */
476#define D28IP_P8IP 28 /* PCI Express Port 8 */
477#define D28IP_P7IP 24 /* PCI Express Port 7 */
478#define D28IP_P6IP 20 /* PCI Express Port 6 */
479#define D28IP_P5IP 16 /* PCI Express Port 5 */
480#define D28IP_P4IP 12 /* PCI Express Port 4 */
481#define D28IP_P3IP 8 /* PCI Express Port 3 */
482#define D28IP_P2IP 4 /* PCI Express Port 2 */
483#define D28IP_P1IP 0 /* PCI Express Port 1 */
484#define D27IP 0x3110 /* 32bit */
485#define D27IP_ZIP 0 /* HD Audio Pin */
486#define D26IP 0x3114 /* 32bit */
487#define D26IP_E2P 0 /* EHCI #2 Pin */
488#define D25IP 0x3118 /* 32bit */
489#define D25IP_LIP 0 /* GbE LAN Pin */
490#define D22IP 0x3124 /* 32bit */
491#define D22IP_KTIP 12 /* KT Pin */
492#define D22IP_IDERIP 8 /* IDE-R Pin */
493#define D22IP_MEI2IP 4 /* MEI #2 Pin */
494#define D22IP_MEI1IP 0 /* MEI #1 Pin */
Duncan Laurie26e7dd72012-12-19 09:12:31 -0800495#define D20IP 0x3128 /* 32bit */
496#define D20IP_XHCI 0 /* XHCI Pin */
Aaron Durbin76c37002012-10-30 09:03:43 -0500497#define D31IR 0x3140 /* 16bit */
498#define D30IR 0x3142 /* 16bit */
499#define D29IR 0x3144 /* 16bit */
500#define D28IR 0x3146 /* 16bit */
501#define D27IR 0x3148 /* 16bit */
502#define D26IR 0x314c /* 16bit */
503#define D25IR 0x3150 /* 16bit */
Duncan Laurie26e7dd72012-12-19 09:12:31 -0800504#define D23IR 0x3158 /* 16bit */
Aaron Durbin76c37002012-10-30 09:03:43 -0500505#define D22IR 0x315c /* 16bit */
Duncan Laurie26e7dd72012-12-19 09:12:31 -0800506#define D20IR 0x3160 /* 16bit */
507#define D21IR 0x3164 /* 16bit */
508#define D19IR 0x3168 /* 16bit */
Duncan Laurieb39ba2e2013-03-22 11:21:14 -0700509#define ACPIIRQEN 0x31e0 /* 32bit */
Aaron Durbin76c37002012-10-30 09:03:43 -0500510#define OIC 0x31fe /* 16bit */
Duncan Lauriee1e87e02013-04-26 10:35:19 -0700511#define PMSYNC_CONFIG 0x33c4 /* 32bit */
512#define PMSYNC_CONFIG2 0x33cc /* 32bit */
Aaron Durbin76c37002012-10-30 09:03:43 -0500513#define SOFT_RESET_CTRL 0x38f4
514#define SOFT_RESET_DATA 0x38f8
515
Aaron Durbin239c2e82012-12-19 11:31:17 -0600516#define DIR_ROUTE(a,b,c,d) \
517 (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
518 ((b) << DIR_IBR) | ((a) << DIR_IAR))
Aaron Durbin76c37002012-10-30 09:03:43 -0500519
520#define RC 0x3400 /* 32bit */
521#define HPTC 0x3404 /* 32bit */
522#define GCS 0x3410 /* 32bit */
523#define BUC 0x3414 /* 32bit */
524#define PCH_DISABLE_GBE (1 << 5)
525#define FD 0x3418 /* 32bit */
526#define DISPBDF 0x3424 /* 16bit */
527#define FD2 0x3428 /* 32bit */
528#define CG 0x341c /* 32bit */
529
530/* Function Disable 1 RCBA 0x3418 */
Duncan Laurie26e7dd72012-12-19 09:12:31 -0800531#define PCH_DISABLE_ALWAYS (1 << 0)
532#define PCH_DISABLE_ADSPD (1 << 1)
Aaron Durbin76c37002012-10-30 09:03:43 -0500533#define PCH_DISABLE_SATA1 (1 << 2)
534#define PCH_DISABLE_SMBUS (1 << 3)
535#define PCH_DISABLE_HD_AUDIO (1 << 4)
536#define PCH_DISABLE_EHCI2 (1 << 13)
537#define PCH_DISABLE_LPC (1 << 14)
538#define PCH_DISABLE_EHCI1 (1 << 15)
Angel Pons1afe4692021-02-10 13:41:04 +0100539#define PCH_DISABLE_PCIE(x) (1 << (16 + (x)))
Aaron Durbin76c37002012-10-30 09:03:43 -0500540#define PCH_DISABLE_THERMAL (1 << 24)
541#define PCH_DISABLE_SATA2 (1 << 25)
Duncan Laurie26e7dd72012-12-19 09:12:31 -0800542#define PCH_DISABLE_XHCI (1 << 27)
Aaron Durbin76c37002012-10-30 09:03:43 -0500543
544/* Function Disable 2 RCBA 0x3428 */
545#define PCH_DISABLE_KT (1 << 4)
546#define PCH_DISABLE_IDER (1 << 3)
547#define PCH_DISABLE_MEI2 (1 << 2)
548#define PCH_DISABLE_MEI1 (1 << 1)
549#define PCH_ENABLE_DBDF (1 << 0)
550
Matt DeVilliera51e3792018-03-04 01:44:15 -0600551#define PCH_IOAPIC_PCI_BUS 250
552#define PCH_IOAPIC_PCI_SLOT 31
553#define PCH_HPET_PCI_BUS 250
554#define PCH_HPET_PCI_SLOT 15
555
Aaron Durbin76c37002012-10-30 09:03:43 -0500556/* ICH7 PMBASE */
557#define PM1_STS 0x00
558#define WAK_STS (1 << 15)
559#define PCIEXPWAK_STS (1 << 14)
560#define PRBTNOR_STS (1 << 11)
561#define RTC_STS (1 << 10)
562#define PWRBTN_STS (1 << 8)
563#define GBL_STS (1 << 5)
564#define BM_STS (1 << 4)
565#define TMROF_STS (1 << 0)
566#define PM1_EN 0x02
567#define PCIEXPWAK_DIS (1 << 14)
568#define RTC_EN (1 << 10)
569#define PWRBTN_EN (1 << 8)
570#define GBL_EN (1 << 5)
571#define TMROF_EN (1 << 0)
572#define PM1_CNT 0x04
Aaron Durbin76c37002012-10-30 09:03:43 -0500573#define GBL_RLS (1 << 2)
574#define BM_RLD (1 << 1)
575#define SCI_EN (1 << 0)
576#define PM1_TMR 0x08
577#define PROC_CNT 0x10
578#define LV2 0x14
579#define LV3 0x15
580#define LV4 0x16
581#define PM2_CNT 0x50 // mobile only
582#define GPE0_STS 0x20
583#define PME_B0_STS (1 << 13)
584#define PME_STS (1 << 11)
585#define BATLOW_STS (1 << 10)
586#define PCI_EXP_STS (1 << 9)
587#define RI_STS (1 << 8)
588#define SMB_WAK_STS (1 << 7)
589#define TCOSCI_STS (1 << 6)
590#define SWGPE_STS (1 << 2)
591#define HOT_PLUG_STS (1 << 1)
Duncan Laurie55cdf552013-03-08 16:01:44 -0800592#define GPE0_STS_2 0x24
Aaron Durbin76c37002012-10-30 09:03:43 -0500593#define GPE0_EN 0x28
594#define PME_B0_EN (1 << 13)
595#define PME_EN (1 << 11)
596#define TCOSCI_EN (1 << 6)
Duncan Laurie55cdf552013-03-08 16:01:44 -0800597#define GPE0_EN_2 0x2c
Aaron Durbin76c37002012-10-30 09:03:43 -0500598#define SMI_EN 0x30
599#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
600#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
601#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
602#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
603#define MCSMI_EN (1 << 11) // Trap microcontroller range access
604#define BIOS_RLS (1 << 7) // asserts SCI on bit set
605#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
606#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
607#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
608#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
609#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
610#define EOS (1 << 1) // End of SMI (deassert SMI#)
611#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
612#define SMI_STS 0x34
613#define ALT_GP_SMI_EN 0x38
614#define ALT_GP_SMI_STS 0x3a
615#define GPE_CNTL 0x42
616#define DEVACT_STS 0x44
617#define SS_CNT 0x50
618#define C3_RES 0x54
619#define TCO1_STS 0x64
620#define DMISCI_STS (1 << 9)
621#define TCO2_STS 0x66
Angel Pons35605d62021-04-24 11:54:01 +0200622#define SECOND_TO_STS (1 << 1)
Duncan Laurie55cdf552013-03-08 16:01:44 -0800623#define ALT_GP_SMI_EN2 0x5c
624#define ALT_GP_SMI_STS2 0x5e
625
626/* Lynxpoint LP */
627#define LP_GPE0_STS_1 0x80 /* GPIO 0-31 */
628#define LP_GPE0_STS_2 0x84 /* GPIO 32-63 */
629#define LP_GPE0_STS_3 0x88 /* GPIO 64-94 */
630#define LP_GPE0_STS_4 0x8c /* Standard GPE */
631#define LP_GPE0_EN_1 0x90
632#define LP_GPE0_EN_2 0x94
633#define LP_GPE0_EN_3 0x98
634#define LP_GPE0_EN_4 0x9c
Aaron Durbin76c37002012-10-30 09:03:43 -0500635
636/*
637 * SPI Opcode Menu setup for SPIBAR lockdown
638 * should support most common flash chips.
639 */
640
641#define SPIBAR_OFFSET 0x3800
Angel Pons1afe4692021-02-10 13:41:04 +0100642#define SPIBAR8(x) RCBA8((x) + SPIBAR_OFFSET)
643#define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET)
644#define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET)
Aaron Durbin76c37002012-10-30 09:03:43 -0500645
646/* Reigsters within the SPIBAR */
647#define SSFC 0x91
648#define FDOC 0xb0
649#define FDOD 0xb4
650
Aaron Durbin76c37002012-10-30 09:03:43 -0500651#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */
652#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
653#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
654#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
655#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
656#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */
Angel Pons1afe4692021-02-10 13:41:04 +0100657#define SPIBAR_HSFC_BYTE_COUNT(c) ((((c) - 1) & 0x3f) << 8)
Aaron Durbin76c37002012-10-30 09:03:43 -0500658#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
659#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
660#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
661#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
662#define SPIBAR_FADDR 0x3808 /* SPI flash address */
Angel Pons1afe4692021-02-10 13:41:04 +0100663#define SPIBAR_FDATA(n) (0x3810 + (4 * (n))) /* SPI flash data */
Aaron Durbin76c37002012-10-30 09:03:43 -0500664
665#endif /* __ACPI__ */
Shawn Nematbakhshccb12fb2013-07-03 17:55:38 -0700666#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */