Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H |
| 4 | #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H |
| 5 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 7 | |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 8 | #define CROS_GPIO_DEVICE_NAME "LynxPoint" |
| 9 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 10 | /* |
| 11 | * Lynx Point PCH PCI Devices: |
| 12 | * |
| 13 | * Bus 0:Device 31:Function 0 LPC Controller1 |
| 14 | * Bus 0:Device 31:Function 2 SATA Controller #1 |
| 15 | * Bus 0:Device 31:Function 3 SMBus Controller |
| 16 | * Bus 0:Device 31:Function 5 SATA Controller #22 |
| 17 | * Bus 0:Device 31:Function 6 Thermal Subsystem |
| 18 | * Bus 0:Device 29:Function 03 USB EHCI Controller #1 |
| 19 | * Bus 0:Device 26:Function 03 USB EHCI Controller #2 |
| 20 | * Bus 0:Device 28:Function 0 PCI Express* Port 1 |
| 21 | * Bus 0:Device 28:Function 1 PCI Express Port 2 |
| 22 | * Bus 0:Device 28:Function 2 PCI Express Port 3 |
| 23 | * Bus 0:Device 28:Function 3 PCI Express Port 4 |
| 24 | * Bus 0:Device 28:Function 4 PCI Express Port 5 |
| 25 | * Bus 0:Device 28:Function 5 PCI Express Port 6 |
| 26 | * Bus 0:Device 28:Function 6 PCI Express Port 7 |
| 27 | * Bus 0:Device 28:Function 7 PCI Express Port 8 |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 28 | * Bus 0:Device 27:Function 0 Intel High Definition Audio Controller |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 29 | * Bus 0:Device 25:Function 0 Gigabit Ethernet Controller |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 30 | * Bus 0:Device 22:Function 0 Intel Management Engine Interface #1 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 31 | * Bus 0:Device 22:Function 1 Intel Management Engine Interface #2 |
| 32 | * Bus 0:Device 22:Function 2 IDE-R |
| 33 | * Bus 0:Device 22:Function 3 KT |
| 34 | * Bus 0:Device 20:Function 0 xHCI Controller |
| 35 | */ |
| 36 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | /* PCH stepping values for LPC device */ |
Duncan Laurie | 4bc107b | 2013-06-24 13:14:44 -0700 | [diff] [blame] | 38 | #define LPT_H_STEP_B0 0x02 |
| 39 | #define LPT_H_STEP_C0 0x03 |
| 40 | #define LPT_H_STEP_C1 0x04 |
| 41 | #define LPT_H_STEP_C2 0x05 |
| 42 | #define LPT_LP_STEP_B0 0x02 |
| 43 | #define LPT_LP_STEP_B1 0x03 |
| 44 | #define LPT_LP_STEP_B2 0x04 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | |
| 46 | /* |
| 47 | * It does not matter where we put the SMBus I/O base, as long as we |
| 48 | * keep it consistent and don't interfere with other devices. Stage2 |
| 49 | * will relocate this anyways. |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame] | 50 | * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 51 | * again. But handling static BARs is a generic problem that should be |
| 52 | * solved in the device allocator. |
| 53 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 54 | #define SMBUS_SLAVE_ADDR 0x24 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 56 | #if CONFIG(INTEL_LYNXPOINT_LP) |
Duncan Laurie | 7922b46 | 2013-03-08 16:34:33 -0800 | [diff] [blame] | 57 | #define DEFAULT_PMBASE 0x1000 |
| 58 | #define DEFAULT_GPIOBASE 0x1400 |
Duncan Laurie | 045f153 | 2012-12-17 11:29:10 -0800 | [diff] [blame] | 59 | #define DEFAULT_GPIOSIZE 0x400 |
| 60 | #else |
Duncan Laurie | 7922b46 | 2013-03-08 16:34:33 -0800 | [diff] [blame] | 61 | #define DEFAULT_PMBASE 0x500 |
Duncan Laurie | 045f153 | 2012-12-17 11:29:10 -0800 | [diff] [blame] | 62 | #define DEFAULT_GPIOBASE 0x480 |
| 63 | #define DEFAULT_GPIOSIZE 0x80 |
| 64 | #endif |
| 65 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 66 | #define HPET_ADDR 0xfed00000 |
Peter Lemenkov | 7b42811 | 2018-10-23 11:12:46 +0200 | [diff] [blame] | 67 | |
| 68 | #include <southbridge/intel/common/rcba.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 69 | |
| 70 | #ifndef __ACPI__ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 71 | |
Angel Pons | d9f1b04 | 2020-09-02 20:19:15 +0200 | [diff] [blame] | 72 | static inline int pch_is_lp(void) |
| 73 | { |
| 74 | return CONFIG(INTEL_LYNXPOINT_LP); |
| 75 | } |
| 76 | |
Angel Pons | 3173993 | 2020-07-03 23:14:40 +0200 | [diff] [blame] | 77 | /* PCH platform types, safe for MRC consumption */ |
| 78 | enum pch_platform_type { |
| 79 | PCH_TYPE_MOBILE = 0, |
| 80 | PCH_TYPE_DESKTOP = 1, /* or server */ |
| 81 | PCH_TYPE_ULT = 5, |
| 82 | }; |
| 83 | |
Elyes HAOUAS | 38f1d13 | 2018-09-17 08:44:18 +0200 | [diff] [blame] | 84 | void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); |
| 85 | void usb_ehci_disable(pci_devfn_t dev); |
| 86 | void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 87 | void usb_xhci_route_all(void); |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 88 | |
Angel Pons | 3173993 | 2020-07-03 23:14:40 +0200 | [diff] [blame] | 89 | enum pch_platform_type get_pch_platform_type(void); |
Duncan Laurie | 5cc51c0 | 2013-03-07 14:06:43 -0800 | [diff] [blame] | 90 | int pch_silicon_revision(void); |
Tristan Corrick | d3f01b2 | 2018-12-06 22:46:58 +1300 | [diff] [blame] | 91 | int pch_silicon_id(void); |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 92 | u16 get_pmbase(void); |
| 93 | u16 get_gpiobase(void); |
Duncan Laurie | 55cdf55 | 2013-03-08 16:01:44 -0800 | [diff] [blame] | 94 | |
| 95 | /* Power Management register handling in pmutil.c */ |
| 96 | /* PM1_CNT */ |
| 97 | void enable_pm1_control(u32 mask); |
| 98 | void disable_pm1_control(u32 mask); |
| 99 | /* PM1 */ |
| 100 | u16 clear_pm1_status(void); |
Aaron Durbin | d6d6db3 | 2013-03-27 21:13:02 -0500 | [diff] [blame] | 101 | void enable_pm1(u16 events); |
Duncan Laurie | 55cdf55 | 2013-03-08 16:01:44 -0800 | [diff] [blame] | 102 | u32 clear_smi_status(void); |
| 103 | /* SMI */ |
| 104 | void enable_smi(u32 mask); |
| 105 | void disable_smi(u32 mask); |
| 106 | /* ALT_GP_SMI */ |
| 107 | u32 clear_alt_smi_status(void); |
| 108 | void enable_alt_smi(u32 mask); |
| 109 | /* TCO */ |
| 110 | u32 clear_tco_status(void); |
| 111 | void enable_tco_sci(void); |
| 112 | /* GPE0 */ |
| 113 | u32 clear_gpe_status(void); |
| 114 | void clear_gpe_enable(void); |
| 115 | void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4); |
| 116 | void disable_all_gpe(void); |
| 117 | void enable_gpe(u32 mask); |
| 118 | void disable_gpe(u32 mask); |
| 119 | |
Elyes HAOUAS | 38f1d13 | 2018-09-17 08:44:18 +0200 | [diff] [blame] | 120 | void pch_enable(struct device *dev); |
| 121 | void pch_disable_devfn(struct device *dev); |
Duncan Laurie | 8584b22 | 2013-02-15 13:52:28 -0800 | [diff] [blame] | 122 | void pch_log_state(void); |
Duncan Laurie | d7cb8d0 | 2013-05-15 15:03:57 -0700 | [diff] [blame] | 123 | void acpi_create_serialio_ssdt(acpi_header_t *ssdt); |
Duncan Laurie | 8584b22 | 2013-02-15 13:52:28 -0800 | [diff] [blame] | 124 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 125 | void enable_usb_bar(void); |
Angel Pons | 03f0e43 | 2020-07-03 13:51:15 +0200 | [diff] [blame] | 126 | int early_pch_init(void); |
Stefan Reinauer | 779e178 | 2013-10-07 16:29:54 -0700 | [diff] [blame] | 127 | void pch_enable_lpc(void); |
Tristan Corrick | 655ef61 | 2018-10-31 02:26:19 +1300 | [diff] [blame] | 128 | void mainboard_config_superio(void); |
Angel Pons | 6e1c471 | 2020-07-03 13:05:10 +0200 | [diff] [blame] | 129 | void mainboard_config_rcba(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 130 | |
| 131 | #define MAINBOARD_POWER_OFF 0 |
| 132 | #define MAINBOARD_POWER_ON 1 |
| 133 | #define MAINBOARD_POWER_KEEP 2 |
| 134 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | /* PCI Configuration Space (D30:F0): PCI2PCI */ |
| 136 | #define PSTS 0x06 |
| 137 | #define SMLT 0x1b |
| 138 | #define SECSTS 0x1e |
| 139 | #define INTR 0x3c |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 140 | |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 141 | /* Power Management Control and Status */ |
| 142 | #define PCH_PCS 0x84 |
| 143 | #define PCH_PCS_PS_D3HOT 3 |
| 144 | |
Angel Pons | 30392ae | 2020-07-12 01:06:23 +0200 | [diff] [blame] | 145 | /* SerialIO */ |
| 146 | #define PCH_DEVFN_SDMA PCI_DEVFN(0x15, 0) |
| 147 | #define PCH_DEVFN_I2C0 PCI_DEVFN(0x15, 1) |
| 148 | #define PCH_DEVFN_I2C1 PCI_DEVFN(0x15, 2) |
| 149 | #define PCH_DEVFN_SPI0 PCI_DEVFN(0x15, 3) |
| 150 | #define PCH_DEVFN_SPI1 PCI_DEVFN(0x15, 4) |
| 151 | #define PCH_DEVFN_UART0 PCI_DEVFN(0x15, 5) |
| 152 | #define PCH_DEVFN_UART1 PCI_DEVFN(0x15, 6) |
| 153 | |
| 154 | #define PCH_DEVFN_SDIO PCI_DEVFN(0x17, 0) |
| 155 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 156 | #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) |
| 157 | #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 158 | #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 159 | #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) |
| 160 | #define PCH_PCIE_DEV_SLOT 28 |
| 161 | |
| 162 | /* PCI Configuration Space (D31:F0): LPC */ |
| 163 | #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) |
| 164 | #define SERIRQ_CNTL 0x64 |
| 165 | |
| 166 | #define GEN_PMCON_1 0xa0 |
| 167 | #define GEN_PMCON_2 0xa2 |
| 168 | #define GEN_PMCON_3 0xa4 |
Aaron Durbin | b9ea8b3 | 2012-11-02 09:10:30 -0500 | [diff] [blame] | 169 | #define PMIR 0xac |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 170 | #define PMIR_CF9LOCK (1 << 31) |
Aaron Durbin | b9ea8b3 | 2012-11-02 09:10:30 -0500 | [diff] [blame] | 171 | #define PMIR_CF9GR (1 << 20) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 172 | |
| 173 | /* GEN_PMCON_3 bits */ |
| 174 | #define RTC_BATTERY_DEAD (1 << 2) |
| 175 | #define RTC_POWER_FAILED (1 << 1) |
| 176 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 177 | |
| 178 | #define PMBASE 0x40 |
| 179 | #define ACPI_CNTL 0x44 |
Paul Menzel | 373a20c | 2013-05-03 12:17:02 +0200 | [diff] [blame] | 180 | #define ACPI_EN (1 << 7) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 181 | #define BIOS_CNTL 0xDC |
| 182 | #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ |
| 183 | #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ |
| 184 | #define GPIO_ROUT 0xb8 |
| 185 | |
| 186 | #define PIRQA_ROUT 0x60 |
| 187 | #define PIRQB_ROUT 0x61 |
| 188 | #define PIRQC_ROUT 0x62 |
| 189 | #define PIRQD_ROUT 0x63 |
| 190 | #define PIRQE_ROUT 0x68 |
| 191 | #define PIRQF_ROUT 0x69 |
| 192 | #define PIRQG_ROUT 0x6A |
| 193 | #define PIRQH_ROUT 0x6B |
| 194 | |
| 195 | #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ |
| 196 | #define LPC_EN 0x82 /* LPC IF Enables Register */ |
| 197 | #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| 198 | #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| 199 | #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| 200 | #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| 201 | #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| 202 | #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| 203 | #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| 204 | #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| 205 | #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| 206 | #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 207 | #define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ |
| 208 | #define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 209 | #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ |
| 210 | #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ |
| 211 | #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ |
| 212 | #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ |
Aaron Durbin | 6f561af | 2012-12-19 14:38:01 -0600 | [diff] [blame] | 213 | #define LGMR 0x98 /* LPC Generic Memory Range */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 214 | |
Angel Pons | 0b3512b | 2020-08-10 13:02:20 +0200 | [diff] [blame] | 215 | /* PCI Configuration Space (D31:F2): SATA */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 216 | #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) |
| 217 | #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) |
Angel Pons | 93859e3 | 2020-11-02 12:08:50 +0100 | [diff] [blame^] | 218 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 219 | #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
| 220 | #define IDE_DECODE_ENABLE (1 << 15) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 221 | #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
| 222 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 223 | #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ |
| 224 | #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ |
| 225 | #define SATA_SP 0xd0 /* Scratchpad */ |
| 226 | |
| 227 | /* SATA IOBP Registers */ |
| 228 | #define SATA_IOBP_SP0G3IR 0xea000151 |
| 229 | #define SATA_IOBP_SP1G3IR 0xea000051 |
Angel Pons | 244a425 | 2020-11-05 10:42:20 +0100 | [diff] [blame] | 230 | #define SATA_IOBP_SP0DTLE_DATA 0xea002750 |
| 231 | #define SATA_IOBP_SP0DTLE_EDGE 0xea002754 |
| 232 | #define SATA_IOBP_SP1DTLE_DATA 0xea002550 |
| 233 | #define SATA_IOBP_SP1DTLE_EDGE 0xea002554 |
Shawn Nematbakhsh | 2875227 | 2013-08-13 10:45:21 -0700 | [diff] [blame] | 234 | |
| 235 | #define SATA_DTLE_MASK 0xF |
| 236 | #define SATA_DTLE_DATA_SHIFT 24 |
| 237 | #define SATA_DTLE_EDGE_SHIFT 16 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 238 | |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 239 | /* EHCI PCI Registers */ |
| 240 | #define EHCI_PWR_CTL_STS 0x54 |
| 241 | #define PWR_CTL_SET_MASK 0x3 |
| 242 | #define PWR_CTL_SET_D0 0x0 |
| 243 | #define PWR_CTL_SET_D3 0x3 |
| 244 | #define PWR_CTL_ENABLE_PME (1 << 8) |
Duncan Laurie | 0bf1dea | 2013-08-13 13:32:28 -0700 | [diff] [blame] | 245 | #define PWR_CTL_STATUS_PME (1 << 15) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 246 | |
| 247 | /* EHCI Memory Registers */ |
| 248 | #define EHCI_USB_CMD 0x20 |
| 249 | #define EHCI_USB_CMD_RUN (1 << 0) |
| 250 | #define EHCI_USB_CMD_PSE (1 << 4) |
| 251 | #define EHCI_USB_CMD_ASE (1 << 5) |
| 252 | #define EHCI_PORTSC(port) (0x64 + (port * 4)) |
| 253 | #define EHCI_PORTSC_ENABLED (1 << 2) |
| 254 | #define EHCI_PORTSC_SUSPEND (1 << 7) |
| 255 | |
| 256 | /* XHCI PCI Registers */ |
| 257 | #define XHCI_PWR_CTL_STS 0x74 |
| 258 | #define XHCI_USB2PR 0xd0 |
| 259 | #define XHCI_USB2PRM 0xd4 |
| 260 | #define XHCI_USB2PR_HCSEL 0x7fff |
| 261 | #define XHCI_USB3PR 0xd8 |
| 262 | #define XHCI_USB3PR_SSEN 0x3f |
| 263 | #define XHCI_USB3PRM 0xdc |
| 264 | #define XHCI_USB3FUS 0xe0 |
| 265 | #define XHCI_USB3FUS_SS_MASK 3 |
| 266 | #define XHCI_USB3FUS_SS_SHIFT 3 |
| 267 | #define XHCI_USB3PDO 0xe8 |
| 268 | |
| 269 | /* XHCI Memory Registers */ |
| 270 | #define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + (port * 0x10)) |
| 271 | #define XHCI_USB3_PORTSC_CHST (0x7f << 17) |
| 272 | #define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ |
| 273 | #define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ |
| 274 | #define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ |
| 275 | #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 276 | #define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ |
| 277 | #define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 278 | #define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 279 | #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ |
| 280 | #define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ |
| 281 | #define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ |
| 282 | #define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ |
| 283 | #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 284 | |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 285 | /* Serial IO IOBP Registers */ |
| 286 | #define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */ |
| 287 | #define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5) |
| 288 | #define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4) |
| 289 | #define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */ |
| 290 | #define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13) |
| 291 | #define SIO_IOBP_GPIODF 0xcb000154 |
| 292 | #define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4) |
| 293 | #define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3) |
| 294 | #define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2) |
| 295 | #define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1) |
| 296 | #define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0) |
| 297 | #define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */ |
| 298 | #define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */ |
| 299 | #define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */ |
| 300 | #define SIO_IOBP_PORTCTRL5 0xcb000258 /* SPI0 D21:F3 */ |
| 301 | #define SIO_IOBP_PORTCTRL6 0xcb000260 /* SPI1 D21:F4 */ |
| 302 | #define SIO_IOBP_PORTCTRL7 0xcb000268 /* UART0 D21:F5 */ |
| 303 | #define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */ |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 304 | #define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8)) |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 305 | /* PORTCTRL 2-8 have the same layout */ |
| 306 | #define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21) |
| 307 | #define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20) |
| 308 | #define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18) |
| 309 | #define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2) |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 310 | #define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1) |
Duncan Laurie | 71346c0 | 2013-01-10 13:20:40 -0800 | [diff] [blame] | 311 | #define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */ |
| 312 | #define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */ |
| 313 | #define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */ |
| 314 | #define SIO_IOBP_FUNCDIS3 0xce00aac7 /* SPI0 D21:F3 */ |
| 315 | #define SIO_IOBP_FUNCDIS4 0xce00ab07 /* SPI1 D21:F4 */ |
| 316 | #define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */ |
| 317 | #define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */ |
| 318 | #define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */ |
| 319 | #define SIO_IOBP_FUNCDIS_DIS (1 << 8) |
| 320 | |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 321 | /* Serial IO Devices */ |
| 322 | #define SIO_ID_SDMA 0 /* D21:F0 */ |
| 323 | #define SIO_ID_I2C0 1 /* D21:F1 */ |
| 324 | #define SIO_ID_I2C1 2 /* D21:F2 */ |
| 325 | #define SIO_ID_SPI0 3 /* D21:F3 */ |
| 326 | #define SIO_ID_SPI1 4 /* D21:F4 */ |
| 327 | #define SIO_ID_UART0 5 /* D21:F5 */ |
| 328 | #define SIO_ID_UART1 6 /* D21:F6 */ |
| 329 | #define SIO_ID_SDIO 7 /* D23:F0 */ |
| 330 | |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 331 | #define SIO_REG_PPR_CLOCK 0x800 |
| 332 | #define SIO_REG_PPR_CLOCK_EN (1 << 0) |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 333 | #define SIO_REG_PPR_RST 0x804 |
| 334 | #define SIO_REG_PPR_RST_ASSERT 0x3 |
| 335 | #define SIO_REG_PPR_GEN 0x808 |
| 336 | #define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2) |
| 337 | #define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3) |
| 338 | #define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3) |
| 339 | #define SIO_REG_AUTO_LTR 0x814 |
| 340 | |
| 341 | #define SIO_REG_SDIO_PPR_GEN 0x1008 |
| 342 | #define SIO_REG_SDIO_PPR_SW_LTR 0x1010 |
| 343 | #define SIO_REG_SDIO_PPR_CMD12 0x3c |
| 344 | #define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30) |
| 345 | |
| 346 | #define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */ |
| 347 | #define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */ |
| 348 | #define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */ |
| 349 | #define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */ |
| 350 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 351 | /* PCI Configuration Space (D31:F3): SMBus */ |
| 352 | #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) |
| 353 | #define SMB_BASE 0x20 |
| 354 | #define HOSTC 0x40 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 355 | |
| 356 | /* HOSTC bits */ |
| 357 | #define I2C_EN (1 << 2) |
| 358 | #define SMB_SMI_EN (1 << 1) |
| 359 | #define HST_EN (1 << 0) |
| 360 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 361 | /* Southbridge IO BARs */ |
| 362 | |
| 363 | #define GPIOBASE 0x48 |
| 364 | |
| 365 | #define PMBASE 0x40 |
| 366 | |
Aaron Durbin | c0254e6 | 2013-06-20 01:20:30 -0500 | [diff] [blame] | 367 | #define RPC 0x0400 /* 32bit */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 368 | #define RPFN 0x0404 /* 32bit */ |
| 369 | |
| 370 | /* Root Port configuratinon space hide */ |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 371 | #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 372 | /* Get the function number assigned to a Root Port */ |
| 373 | #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) |
| 374 | /* Set the function number for a Root Port */ |
| 375 | #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) |
| 376 | /* Root Port function number mask */ |
| 377 | #define RPFN_FNMASK(port) (7 << ((port) * 4)) |
| 378 | |
| 379 | #define TRSR 0x1e00 /* 8bit */ |
| 380 | #define TRCR 0x1e10 /* 64bit */ |
| 381 | #define TWDR 0x1e18 /* 64bit */ |
| 382 | |
| 383 | #define IOTR0 0x1e80 /* 64bit */ |
| 384 | #define IOTR1 0x1e88 /* 64bit */ |
| 385 | #define IOTR2 0x1e90 /* 64bit */ |
| 386 | #define IOTR3 0x1e98 /* 64bit */ |
| 387 | |
| 388 | #define TCTL 0x3000 /* 8bit */ |
| 389 | |
| 390 | #define NOINT 0 |
| 391 | #define INTA 1 |
| 392 | #define INTB 2 |
| 393 | #define INTC 3 |
| 394 | #define INTD 4 |
| 395 | |
| 396 | #define DIR_IDR 12 /* Interrupt D Pin Offset */ |
| 397 | #define DIR_ICR 8 /* Interrupt C Pin Offset */ |
| 398 | #define DIR_IBR 4 /* Interrupt B Pin Offset */ |
| 399 | #define DIR_IAR 0 /* Interrupt A Pin Offset */ |
| 400 | |
| 401 | #define PIRQA 0 |
| 402 | #define PIRQB 1 |
| 403 | #define PIRQC 2 |
| 404 | #define PIRQD 3 |
| 405 | #define PIRQE 4 |
| 406 | #define PIRQF 5 |
| 407 | #define PIRQG 6 |
| 408 | #define PIRQH 7 |
| 409 | |
| 410 | /* IO Buffer Programming */ |
| 411 | #define IOBPIRI 0x2330 |
| 412 | #define IOBPD 0x2334 |
| 413 | #define IOBPS 0x2338 |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 414 | #define IOBPS_READY 0x0001 |
| 415 | #define IOBPS_TX_MASK 0x0006 |
| 416 | #define IOBPS_MASK 0xff00 |
| 417 | #define IOBPS_READ 0x0600 |
| 418 | #define IOBPS_WRITE 0x0700 |
| 419 | #define IOBPU 0x233a |
| 420 | #define IOBPU_MAGIC 0xf000 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 421 | |
| 422 | #define D31IP 0x3100 /* 32bit */ |
| 423 | #define D31IP_TTIP 24 /* Thermal Throttle Pin */ |
| 424 | #define D31IP_SIP2 20 /* SATA Pin 2 */ |
| 425 | #define D31IP_SMIP 12 /* SMBUS Pin */ |
| 426 | #define D31IP_SIP 8 /* SATA Pin */ |
| 427 | #define D30IP 0x3104 /* 32bit */ |
| 428 | #define D30IP_PIP 0 /* PCI Bridge Pin */ |
| 429 | #define D29IP 0x3108 /* 32bit */ |
| 430 | #define D29IP_E1P 0 /* EHCI #1 Pin */ |
| 431 | #define D28IP 0x310c /* 32bit */ |
| 432 | #define D28IP_P8IP 28 /* PCI Express Port 8 */ |
| 433 | #define D28IP_P7IP 24 /* PCI Express Port 7 */ |
| 434 | #define D28IP_P6IP 20 /* PCI Express Port 6 */ |
| 435 | #define D28IP_P5IP 16 /* PCI Express Port 5 */ |
| 436 | #define D28IP_P4IP 12 /* PCI Express Port 4 */ |
| 437 | #define D28IP_P3IP 8 /* PCI Express Port 3 */ |
| 438 | #define D28IP_P2IP 4 /* PCI Express Port 2 */ |
| 439 | #define D28IP_P1IP 0 /* PCI Express Port 1 */ |
| 440 | #define D27IP 0x3110 /* 32bit */ |
| 441 | #define D27IP_ZIP 0 /* HD Audio Pin */ |
| 442 | #define D26IP 0x3114 /* 32bit */ |
| 443 | #define D26IP_E2P 0 /* EHCI #2 Pin */ |
| 444 | #define D25IP 0x3118 /* 32bit */ |
| 445 | #define D25IP_LIP 0 /* GbE LAN Pin */ |
| 446 | #define D22IP 0x3124 /* 32bit */ |
| 447 | #define D22IP_KTIP 12 /* KT Pin */ |
| 448 | #define D22IP_IDERIP 8 /* IDE-R Pin */ |
| 449 | #define D22IP_MEI2IP 4 /* MEI #2 Pin */ |
| 450 | #define D22IP_MEI1IP 0 /* MEI #1 Pin */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 451 | #define D20IP 0x3128 /* 32bit */ |
| 452 | #define D20IP_XHCI 0 /* XHCI Pin */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 453 | #define D31IR 0x3140 /* 16bit */ |
| 454 | #define D30IR 0x3142 /* 16bit */ |
| 455 | #define D29IR 0x3144 /* 16bit */ |
| 456 | #define D28IR 0x3146 /* 16bit */ |
| 457 | #define D27IR 0x3148 /* 16bit */ |
| 458 | #define D26IR 0x314c /* 16bit */ |
| 459 | #define D25IR 0x3150 /* 16bit */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 460 | #define D23IR 0x3158 /* 16bit */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 461 | #define D22IR 0x315c /* 16bit */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 462 | #define D20IR 0x3160 /* 16bit */ |
| 463 | #define D21IR 0x3164 /* 16bit */ |
| 464 | #define D19IR 0x3168 /* 16bit */ |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 465 | #define ACPIIRQEN 0x31e0 /* 32bit */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 466 | #define OIC 0x31fe /* 16bit */ |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 467 | #define PMSYNC_CONFIG 0x33c4 /* 32bit */ |
| 468 | #define PMSYNC_CONFIG2 0x33cc /* 32bit */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 469 | #define SOFT_RESET_CTRL 0x38f4 |
| 470 | #define SOFT_RESET_DATA 0x38f8 |
| 471 | |
Aaron Durbin | 239c2e8 | 2012-12-19 11:31:17 -0600 | [diff] [blame] | 472 | #define DIR_ROUTE(a,b,c,d) \ |
| 473 | (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ |
| 474 | ((b) << DIR_IBR) | ((a) << DIR_IAR)) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 475 | |
| 476 | #define RC 0x3400 /* 32bit */ |
| 477 | #define HPTC 0x3404 /* 32bit */ |
| 478 | #define GCS 0x3410 /* 32bit */ |
| 479 | #define BUC 0x3414 /* 32bit */ |
| 480 | #define PCH_DISABLE_GBE (1 << 5) |
| 481 | #define FD 0x3418 /* 32bit */ |
| 482 | #define DISPBDF 0x3424 /* 16bit */ |
| 483 | #define FD2 0x3428 /* 32bit */ |
| 484 | #define CG 0x341c /* 32bit */ |
| 485 | |
| 486 | /* Function Disable 1 RCBA 0x3418 */ |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 487 | #define PCH_DISABLE_ALWAYS (1 << 0) |
| 488 | #define PCH_DISABLE_ADSPD (1 << 1) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 489 | #define PCH_DISABLE_SATA1 (1 << 2) |
| 490 | #define PCH_DISABLE_SMBUS (1 << 3) |
| 491 | #define PCH_DISABLE_HD_AUDIO (1 << 4) |
| 492 | #define PCH_DISABLE_EHCI2 (1 << 13) |
| 493 | #define PCH_DISABLE_LPC (1 << 14) |
| 494 | #define PCH_DISABLE_EHCI1 (1 << 15) |
| 495 | #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) |
| 496 | #define PCH_DISABLE_THERMAL (1 << 24) |
| 497 | #define PCH_DISABLE_SATA2 (1 << 25) |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 498 | #define PCH_DISABLE_XHCI (1 << 27) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 499 | |
| 500 | /* Function Disable 2 RCBA 0x3428 */ |
| 501 | #define PCH_DISABLE_KT (1 << 4) |
| 502 | #define PCH_DISABLE_IDER (1 << 3) |
| 503 | #define PCH_DISABLE_MEI2 (1 << 2) |
| 504 | #define PCH_DISABLE_MEI1 (1 << 1) |
| 505 | #define PCH_ENABLE_DBDF (1 << 0) |
| 506 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 507 | #define PCH_IOAPIC_PCI_BUS 250 |
| 508 | #define PCH_IOAPIC_PCI_SLOT 31 |
| 509 | #define PCH_HPET_PCI_BUS 250 |
| 510 | #define PCH_HPET_PCI_SLOT 15 |
| 511 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 512 | /* ICH7 PMBASE */ |
| 513 | #define PM1_STS 0x00 |
| 514 | #define WAK_STS (1 << 15) |
| 515 | #define PCIEXPWAK_STS (1 << 14) |
| 516 | #define PRBTNOR_STS (1 << 11) |
| 517 | #define RTC_STS (1 << 10) |
| 518 | #define PWRBTN_STS (1 << 8) |
| 519 | #define GBL_STS (1 << 5) |
| 520 | #define BM_STS (1 << 4) |
| 521 | #define TMROF_STS (1 << 0) |
| 522 | #define PM1_EN 0x02 |
| 523 | #define PCIEXPWAK_DIS (1 << 14) |
| 524 | #define RTC_EN (1 << 10) |
| 525 | #define PWRBTN_EN (1 << 8) |
| 526 | #define GBL_EN (1 << 5) |
| 527 | #define TMROF_EN (1 << 0) |
| 528 | #define PM1_CNT 0x04 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 529 | #define GBL_RLS (1 << 2) |
| 530 | #define BM_RLD (1 << 1) |
| 531 | #define SCI_EN (1 << 0) |
| 532 | #define PM1_TMR 0x08 |
| 533 | #define PROC_CNT 0x10 |
| 534 | #define LV2 0x14 |
| 535 | #define LV3 0x15 |
| 536 | #define LV4 0x16 |
| 537 | #define PM2_CNT 0x50 // mobile only |
| 538 | #define GPE0_STS 0x20 |
| 539 | #define PME_B0_STS (1 << 13) |
| 540 | #define PME_STS (1 << 11) |
| 541 | #define BATLOW_STS (1 << 10) |
| 542 | #define PCI_EXP_STS (1 << 9) |
| 543 | #define RI_STS (1 << 8) |
| 544 | #define SMB_WAK_STS (1 << 7) |
| 545 | #define TCOSCI_STS (1 << 6) |
| 546 | #define SWGPE_STS (1 << 2) |
| 547 | #define HOT_PLUG_STS (1 << 1) |
Duncan Laurie | 55cdf55 | 2013-03-08 16:01:44 -0800 | [diff] [blame] | 548 | #define GPE0_STS_2 0x24 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 549 | #define GPE0_EN 0x28 |
| 550 | #define PME_B0_EN (1 << 13) |
| 551 | #define PME_EN (1 << 11) |
| 552 | #define TCOSCI_EN (1 << 6) |
Duncan Laurie | 55cdf55 | 2013-03-08 16:01:44 -0800 | [diff] [blame] | 553 | #define GPE0_EN_2 0x2c |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 554 | #define SMI_EN 0x30 |
| 555 | #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic |
| 556 | #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic |
| 557 | #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS |
| 558 | #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) |
| 559 | #define MCSMI_EN (1 << 11) // Trap microcontroller range access |
| 560 | #define BIOS_RLS (1 << 7) // asserts SCI on bit set |
| 561 | #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set |
| 562 | #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# |
| 563 | #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# |
| 564 | #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic |
| 565 | #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit |
| 566 | #define EOS (1 << 1) // End of SMI (deassert SMI#) |
| 567 | #define GBL_SMI_EN (1 << 0) // SMI# generation at all? |
| 568 | #define SMI_STS 0x34 |
| 569 | #define ALT_GP_SMI_EN 0x38 |
| 570 | #define ALT_GP_SMI_STS 0x3a |
| 571 | #define GPE_CNTL 0x42 |
| 572 | #define DEVACT_STS 0x44 |
| 573 | #define SS_CNT 0x50 |
| 574 | #define C3_RES 0x54 |
| 575 | #define TCO1_STS 0x64 |
| 576 | #define DMISCI_STS (1 << 9) |
| 577 | #define TCO2_STS 0x66 |
Duncan Laurie | 55cdf55 | 2013-03-08 16:01:44 -0800 | [diff] [blame] | 578 | #define ALT_GP_SMI_EN2 0x5c |
| 579 | #define ALT_GP_SMI_STS2 0x5e |
| 580 | |
| 581 | /* Lynxpoint LP */ |
| 582 | #define LP_GPE0_STS_1 0x80 /* GPIO 0-31 */ |
| 583 | #define LP_GPE0_STS_2 0x84 /* GPIO 32-63 */ |
| 584 | #define LP_GPE0_STS_3 0x88 /* GPIO 64-94 */ |
| 585 | #define LP_GPE0_STS_4 0x8c /* Standard GPE */ |
| 586 | #define LP_GPE0_EN_1 0x90 |
| 587 | #define LP_GPE0_EN_2 0x94 |
| 588 | #define LP_GPE0_EN_3 0x98 |
| 589 | #define LP_GPE0_EN_4 0x9c |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 590 | |
| 591 | /* |
| 592 | * SPI Opcode Menu setup for SPIBAR lockdown |
| 593 | * should support most common flash chips. |
| 594 | */ |
| 595 | |
| 596 | #define SPIBAR_OFFSET 0x3800 |
| 597 | #define SPIBAR8(x) RCBA8(x + SPIBAR_OFFSET) |
| 598 | #define SPIBAR16(x) RCBA16(x + SPIBAR_OFFSET) |
| 599 | #define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET) |
| 600 | |
| 601 | /* Reigsters within the SPIBAR */ |
| 602 | #define SSFC 0x91 |
| 603 | #define FDOC 0xb0 |
| 604 | #define FDOD 0xb4 |
| 605 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 606 | #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ |
| 607 | #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ |
| 608 | #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ |
| 609 | #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ |
| 610 | #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ |
| 611 | #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ |
| 612 | #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) |
| 613 | #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ |
| 614 | #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ |
| 615 | #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ |
| 616 | #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ |
| 617 | #define SPIBAR_FADDR 0x3808 /* SPI flash address */ |
| 618 | #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ |
| 619 | |
| 620 | #endif /* __ACPI__ */ |
Shawn Nematbakhsh | ccb12fb | 2013-07-03 17:55:38 -0700 | [diff] [blame] | 621 | #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */ |