intel/lynxpoint: Export pch_enable_lpc() for Super I/O systems
In order to enable a Super I/O in non Chrome EC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c
BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino
Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6019
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 3396367..9b5cb6f 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -213,6 +213,7 @@
int early_spi_read(u32 offset, u32 size, u8 *buffer);
int early_pch_init(const void *gpio_map,
const struct rcba_config_instruction *rcba_config);
+void pch_enable_lpc(void);
#endif /* !__PRE_RAM__ && !__SMM__ */
#endif /* __ASSEMBLER__ */