Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H |
| 22 | #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H |
| 23 | |
| 24 | |
| 25 | /* |
| 26 | * Lynx Point PCH PCI Devices: |
| 27 | * |
| 28 | * Bus 0:Device 31:Function 0 LPC Controller1 |
| 29 | * Bus 0:Device 31:Function 2 SATA Controller #1 |
| 30 | * Bus 0:Device 31:Function 3 SMBus Controller |
| 31 | * Bus 0:Device 31:Function 5 SATA Controller #22 |
| 32 | * Bus 0:Device 31:Function 6 Thermal Subsystem |
| 33 | * Bus 0:Device 29:Function 03 USB EHCI Controller #1 |
| 34 | * Bus 0:Device 26:Function 03 USB EHCI Controller #2 |
| 35 | * Bus 0:Device 28:Function 0 PCI Express* Port 1 |
| 36 | * Bus 0:Device 28:Function 1 PCI Express Port 2 |
| 37 | * Bus 0:Device 28:Function 2 PCI Express Port 3 |
| 38 | * Bus 0:Device 28:Function 3 PCI Express Port 4 |
| 39 | * Bus 0:Device 28:Function 4 PCI Express Port 5 |
| 40 | * Bus 0:Device 28:Function 5 PCI Express Port 6 |
| 41 | * Bus 0:Device 28:Function 6 PCI Express Port 7 |
| 42 | * Bus 0:Device 28:Function 7 PCI Express Port 8 |
| 43 | * Bus 0:Device 27:Function 0 IntelĀ® High Definition Audio Controller |
| 44 | * Bus 0:Device 25:Function 0 Gigabit Ethernet Controller |
| 45 | * Bus 0:Device 22:Function 0 IntelĀ® Management Engine Interface #1 |
| 46 | * Bus 0:Device 22:Function 1 Intel Management Engine Interface #2 |
| 47 | * Bus 0:Device 22:Function 2 IDE-R |
| 48 | * Bus 0:Device 22:Function 3 KT |
| 49 | * Bus 0:Device 20:Function 0 xHCI Controller |
| 50 | */ |
| 51 | |
| 52 | /* PCH types */ |
| 53 | |
| 54 | /* PCH stepping values for LPC device */ |
| 55 | |
| 56 | /* |
| 57 | * It does not matter where we put the SMBus I/O base, as long as we |
| 58 | * keep it consistent and don't interfere with other devices. Stage2 |
| 59 | * will relocate this anyways. |
| 60 | * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE |
| 61 | * again. But handling static BARs is a generic problem that should be |
| 62 | * solved in the device allocator. |
| 63 | */ |
| 64 | #define SMBUS_IO_BASE 0x0400 |
| 65 | #define SMBUS_SLAVE_ADDR 0x24 |
| 66 | /* TODO Make sure these don't get changed by stage2 */ |
| 67 | #define DEFAULT_GPIOBASE 0x0480 |
| 68 | #define DEFAULT_PMBASE 0x0500 |
| 69 | |
| 70 | #define HPET_ADDR 0xfed00000 |
| 71 | #define DEFAULT_RCBA 0xfed1c000 |
| 72 | |
| 73 | #ifndef __ACPI__ |
| 74 | #define DEBUG_PERIODIC_SMIS 0 |
| 75 | |
| 76 | #if defined (__SMM__) && !defined(__ASSEMBLER__) |
| 77 | void intel_pch_finalize_smm(void); |
| 78 | #endif |
| 79 | |
| 80 | #if !defined(__ASSEMBLER__) && !defined(__ROMCC__) |
| 81 | #if !defined(__PRE_RAM__) && !defined(__SMM__) |
| 82 | #include <device/device.h> |
| 83 | #include <arch/acpi.h> |
| 84 | #include "chip.h" |
| 85 | int pch_silicon_revision(void); |
| 86 | int pch_silicon_type(void); |
| 87 | int pch_silicon_supported(int type, int rev); |
| 88 | void pch_enable(device_t dev); |
| 89 | void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); |
| 90 | #if CONFIG_ELOG |
| 91 | void pch_log_state(void); |
| 92 | #endif |
| 93 | void acpi_create_intel_hpet(acpi_hpet_t * hpet); |
| 94 | #else |
| 95 | void enable_smbus(void); |
| 96 | void enable_usb_bar(void); |
| 97 | int smbus_read_byte(unsigned device, unsigned address); |
| 98 | int early_spi_read(u32 offset, u32 size, u8 *buffer); |
| 99 | #endif |
| 100 | #endif |
| 101 | |
| 102 | #define MAINBOARD_POWER_OFF 0 |
| 103 | #define MAINBOARD_POWER_ON 1 |
| 104 | #define MAINBOARD_POWER_KEEP 2 |
| 105 | |
| 106 | #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| 107 | #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON |
| 108 | #endif |
| 109 | |
| 110 | /* PCI Configuration Space (D30:F0): PCI2PCI */ |
| 111 | #define PSTS 0x06 |
| 112 | #define SMLT 0x1b |
| 113 | #define SECSTS 0x1e |
| 114 | #define INTR 0x3c |
| 115 | #define BCTRL 0x3e |
| 116 | #define SBR (1 << 6) |
| 117 | #define SEE (1 << 1) |
| 118 | #define PERE (1 << 0) |
| 119 | |
| 120 | #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) |
| 121 | #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) |
| 122 | #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) |
| 123 | #define PCH_PCIE_DEV_SLOT 28 |
| 124 | |
| 125 | /* PCI Configuration Space (D31:F0): LPC */ |
| 126 | #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) |
| 127 | #define SERIRQ_CNTL 0x64 |
| 128 | |
| 129 | #define GEN_PMCON_1 0xa0 |
| 130 | #define GEN_PMCON_2 0xa2 |
| 131 | #define GEN_PMCON_3 0xa4 |
Aaron Durbin | b9ea8b3 | 2012-11-02 09:10:30 -0500 | [diff] [blame^] | 132 | #define PMIR 0xac |
| 133 | #define PMIR_CF9LOCK (1 << 31) |
| 134 | #define PMIR_CF9GR (1 << 20) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | |
| 136 | /* GEN_PMCON_3 bits */ |
| 137 | #define RTC_BATTERY_DEAD (1 << 2) |
| 138 | #define RTC_POWER_FAILED (1 << 1) |
| 139 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 140 | |
| 141 | #define PMBASE 0x40 |
| 142 | #define ACPI_CNTL 0x44 |
| 143 | #define BIOS_CNTL 0xDC |
| 144 | #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ |
| 145 | #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ |
| 146 | #define GPIO_ROUT 0xb8 |
| 147 | |
| 148 | #define PIRQA_ROUT 0x60 |
| 149 | #define PIRQB_ROUT 0x61 |
| 150 | #define PIRQC_ROUT 0x62 |
| 151 | #define PIRQD_ROUT 0x63 |
| 152 | #define PIRQE_ROUT 0x68 |
| 153 | #define PIRQF_ROUT 0x69 |
| 154 | #define PIRQG_ROUT 0x6A |
| 155 | #define PIRQH_ROUT 0x6B |
| 156 | |
| 157 | #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ |
| 158 | #define LPC_EN 0x82 /* LPC IF Enables Register */ |
| 159 | #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| 160 | #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| 161 | #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| 162 | #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| 163 | #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| 164 | #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| 165 | #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| 166 | #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| 167 | #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| 168 | #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ |
| 169 | #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ |
| 170 | #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ |
| 171 | #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ |
| 172 | #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ |
| 173 | |
| 174 | /* PCI Configuration Space (D31:F1): IDE */ |
| 175 | #define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) |
| 176 | #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) |
| 177 | #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) |
| 178 | #define INTR_LN 0x3c |
| 179 | #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
| 180 | #define IDE_DECODE_ENABLE (1 << 15) |
| 181 | #define IDE_SITRE (1 << 14) |
| 182 | #define IDE_ISP_5_CLOCKS (0 << 12) |
| 183 | #define IDE_ISP_4_CLOCKS (1 << 12) |
| 184 | #define IDE_ISP_3_CLOCKS (2 << 12) |
| 185 | #define IDE_RCT_4_CLOCKS (0 << 8) |
| 186 | #define IDE_RCT_3_CLOCKS (1 << 8) |
| 187 | #define IDE_RCT_2_CLOCKS (2 << 8) |
| 188 | #define IDE_RCT_1_CLOCKS (3 << 8) |
| 189 | #define IDE_DTE1 (1 << 7) |
| 190 | #define IDE_PPE1 (1 << 6) |
| 191 | #define IDE_IE1 (1 << 5) |
| 192 | #define IDE_TIME1 (1 << 4) |
| 193 | #define IDE_DTE0 (1 << 3) |
| 194 | #define IDE_PPE0 (1 << 2) |
| 195 | #define IDE_IE0 (1 << 1) |
| 196 | #define IDE_TIME0 (1 << 0) |
| 197 | #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
| 198 | |
| 199 | #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ |
| 200 | #define IDE_SSDE1 (1 << 3) |
| 201 | #define IDE_SSDE0 (1 << 2) |
| 202 | #define IDE_PSDE1 (1 << 1) |
| 203 | #define IDE_PSDE0 (1 << 0) |
| 204 | |
| 205 | #define IDE_SDMA_TIM 0x4a |
| 206 | |
| 207 | #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ |
| 208 | #define SIG_MODE_SEC_NORMAL (0 << 18) |
| 209 | #define SIG_MODE_SEC_TRISTATE (1 << 18) |
| 210 | #define SIG_MODE_SEC_DRIVELOW (2 << 18) |
| 211 | #define SIG_MODE_PRI_NORMAL (0 << 16) |
| 212 | #define SIG_MODE_PRI_TRISTATE (1 << 16) |
| 213 | #define SIG_MODE_PRI_DRIVELOW (2 << 16) |
| 214 | #define FAST_SCB1 (1 << 15) |
| 215 | #define FAST_SCB0 (1 << 14) |
| 216 | #define FAST_PCB1 (1 << 13) |
| 217 | #define FAST_PCB0 (1 << 12) |
| 218 | #define SCB1 (1 << 3) |
| 219 | #define SCB0 (1 << 2) |
| 220 | #define PCB1 (1 << 1) |
| 221 | #define PCB0 (1 << 0) |
| 222 | |
| 223 | #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ |
| 224 | #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ |
| 225 | #define SATA_SP 0xd0 /* Scratchpad */ |
| 226 | |
| 227 | /* SATA IOBP Registers */ |
| 228 | #define SATA_IOBP_SP0G3IR 0xea000151 |
| 229 | #define SATA_IOBP_SP1G3IR 0xea000051 |
| 230 | |
| 231 | /* PCI Configuration Space (D31:F3): SMBus */ |
| 232 | #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) |
| 233 | #define SMB_BASE 0x20 |
| 234 | #define HOSTC 0x40 |
| 235 | #define SMB_RCV_SLVA 0x09 |
| 236 | |
| 237 | /* HOSTC bits */ |
| 238 | #define I2C_EN (1 << 2) |
| 239 | #define SMB_SMI_EN (1 << 1) |
| 240 | #define HST_EN (1 << 0) |
| 241 | |
| 242 | /* SMBus I/O bits. */ |
| 243 | #define SMBHSTSTAT 0x0 |
| 244 | #define SMBHSTCTL 0x2 |
| 245 | #define SMBHSTCMD 0x3 |
| 246 | #define SMBXMITADD 0x4 |
| 247 | #define SMBHSTDAT0 0x5 |
| 248 | #define SMBHSTDAT1 0x6 |
| 249 | #define SMBBLKDAT 0x7 |
| 250 | #define SMBTRNSADD 0x9 |
| 251 | #define SMBSLVDATA 0xa |
| 252 | #define SMLINK_PIN_CTL 0xe |
| 253 | #define SMBUS_PIN_CTL 0xf |
| 254 | |
| 255 | #define SMBUS_TIMEOUT (10 * 1000 * 100) |
| 256 | |
| 257 | |
| 258 | /* Southbridge IO BARs */ |
| 259 | |
| 260 | #define GPIOBASE 0x48 |
| 261 | |
| 262 | #define PMBASE 0x40 |
| 263 | |
| 264 | /* Root Complex Register Block */ |
| 265 | #define RCBA 0xf0 |
| 266 | |
| 267 | #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) |
| 268 | #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) |
| 269 | #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) |
| 270 | |
| 271 | #define RCBA_AND_OR(bits, x, and, or) \ |
| 272 | RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) |
| 273 | #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) |
| 274 | #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) |
| 275 | #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) |
| 276 | #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) |
| 277 | |
| 278 | #define VCH 0x0000 /* 32bit */ |
| 279 | #define VCAP1 0x0004 /* 32bit */ |
| 280 | #define VCAP2 0x0008 /* 32bit */ |
| 281 | #define PVC 0x000c /* 16bit */ |
| 282 | #define PVS 0x000e /* 16bit */ |
| 283 | |
| 284 | #define V0CAP 0x0010 /* 32bit */ |
| 285 | #define V0CTL 0x0014 /* 32bit */ |
| 286 | #define V0STS 0x001a /* 16bit */ |
| 287 | |
| 288 | #define V1CAP 0x001c /* 32bit */ |
| 289 | #define V1CTL 0x0020 /* 32bit */ |
| 290 | #define V1STS 0x0026 /* 16bit */ |
| 291 | |
| 292 | #define RCTCL 0x0100 /* 32bit */ |
| 293 | #define ESD 0x0104 /* 32bit */ |
| 294 | #define ULD 0x0110 /* 32bit */ |
| 295 | #define ULBA 0x0118 /* 64bit */ |
| 296 | |
| 297 | #define RP1D 0x0120 /* 32bit */ |
| 298 | #define RP1BA 0x0128 /* 64bit */ |
| 299 | #define RP2D 0x0130 /* 32bit */ |
| 300 | #define RP2BA 0x0138 /* 64bit */ |
| 301 | #define RP3D 0x0140 /* 32bit */ |
| 302 | #define RP3BA 0x0148 /* 64bit */ |
| 303 | #define RP4D 0x0150 /* 32bit */ |
| 304 | #define RP4BA 0x0158 /* 64bit */ |
| 305 | #define HDD 0x0160 /* 32bit */ |
| 306 | #define HDBA 0x0168 /* 64bit */ |
| 307 | #define RP5D 0x0170 /* 32bit */ |
| 308 | #define RP5BA 0x0178 /* 64bit */ |
| 309 | #define RP6D 0x0180 /* 32bit */ |
| 310 | #define RP6BA 0x0188 /* 64bit */ |
| 311 | |
| 312 | #define RPFN 0x0404 /* 32bit */ |
| 313 | |
| 314 | /* Root Port configuratinon space hide */ |
| 315 | #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) |
| 316 | /* Get the function number assigned to a Root Port */ |
| 317 | #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) |
| 318 | /* Set the function number for a Root Port */ |
| 319 | #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) |
| 320 | /* Root Port function number mask */ |
| 321 | #define RPFN_FNMASK(port) (7 << ((port) * 4)) |
| 322 | |
| 323 | #define TRSR 0x1e00 /* 8bit */ |
| 324 | #define TRCR 0x1e10 /* 64bit */ |
| 325 | #define TWDR 0x1e18 /* 64bit */ |
| 326 | |
| 327 | #define IOTR0 0x1e80 /* 64bit */ |
| 328 | #define IOTR1 0x1e88 /* 64bit */ |
| 329 | #define IOTR2 0x1e90 /* 64bit */ |
| 330 | #define IOTR3 0x1e98 /* 64bit */ |
| 331 | |
| 332 | #define TCTL 0x3000 /* 8bit */ |
| 333 | |
| 334 | #define NOINT 0 |
| 335 | #define INTA 1 |
| 336 | #define INTB 2 |
| 337 | #define INTC 3 |
| 338 | #define INTD 4 |
| 339 | |
| 340 | #define DIR_IDR 12 /* Interrupt D Pin Offset */ |
| 341 | #define DIR_ICR 8 /* Interrupt C Pin Offset */ |
| 342 | #define DIR_IBR 4 /* Interrupt B Pin Offset */ |
| 343 | #define DIR_IAR 0 /* Interrupt A Pin Offset */ |
| 344 | |
| 345 | #define PIRQA 0 |
| 346 | #define PIRQB 1 |
| 347 | #define PIRQC 2 |
| 348 | #define PIRQD 3 |
| 349 | #define PIRQE 4 |
| 350 | #define PIRQF 5 |
| 351 | #define PIRQG 6 |
| 352 | #define PIRQH 7 |
| 353 | |
| 354 | /* IO Buffer Programming */ |
| 355 | #define IOBPIRI 0x2330 |
| 356 | #define IOBPD 0x2334 |
| 357 | #define IOBPS 0x2338 |
Duncan Laurie | 7302d1e | 2013-01-10 13:19:23 -0800 | [diff] [blame] | 358 | #define IOBPS_READY 0x0001 |
| 359 | #define IOBPS_TX_MASK 0x0006 |
| 360 | #define IOBPS_MASK 0xff00 |
| 361 | #define IOBPS_READ 0x0600 |
| 362 | #define IOBPS_WRITE 0x0700 |
| 363 | #define IOBPU 0x233a |
| 364 | #define IOBPU_MAGIC 0xf000 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 365 | |
| 366 | #define D31IP 0x3100 /* 32bit */ |
| 367 | #define D31IP_TTIP 24 /* Thermal Throttle Pin */ |
| 368 | #define D31IP_SIP2 20 /* SATA Pin 2 */ |
| 369 | #define D31IP_SMIP 12 /* SMBUS Pin */ |
| 370 | #define D31IP_SIP 8 /* SATA Pin */ |
| 371 | #define D30IP 0x3104 /* 32bit */ |
| 372 | #define D30IP_PIP 0 /* PCI Bridge Pin */ |
| 373 | #define D29IP 0x3108 /* 32bit */ |
| 374 | #define D29IP_E1P 0 /* EHCI #1 Pin */ |
| 375 | #define D28IP 0x310c /* 32bit */ |
| 376 | #define D28IP_P8IP 28 /* PCI Express Port 8 */ |
| 377 | #define D28IP_P7IP 24 /* PCI Express Port 7 */ |
| 378 | #define D28IP_P6IP 20 /* PCI Express Port 6 */ |
| 379 | #define D28IP_P5IP 16 /* PCI Express Port 5 */ |
| 380 | #define D28IP_P4IP 12 /* PCI Express Port 4 */ |
| 381 | #define D28IP_P3IP 8 /* PCI Express Port 3 */ |
| 382 | #define D28IP_P2IP 4 /* PCI Express Port 2 */ |
| 383 | #define D28IP_P1IP 0 /* PCI Express Port 1 */ |
| 384 | #define D27IP 0x3110 /* 32bit */ |
| 385 | #define D27IP_ZIP 0 /* HD Audio Pin */ |
| 386 | #define D26IP 0x3114 /* 32bit */ |
| 387 | #define D26IP_E2P 0 /* EHCI #2 Pin */ |
| 388 | #define D25IP 0x3118 /* 32bit */ |
| 389 | #define D25IP_LIP 0 /* GbE LAN Pin */ |
| 390 | #define D22IP 0x3124 /* 32bit */ |
| 391 | #define D22IP_KTIP 12 /* KT Pin */ |
| 392 | #define D22IP_IDERIP 8 /* IDE-R Pin */ |
| 393 | #define D22IP_MEI2IP 4 /* MEI #2 Pin */ |
| 394 | #define D22IP_MEI1IP 0 /* MEI #1 Pin */ |
| 395 | #define D31IR 0x3140 /* 16bit */ |
| 396 | #define D30IR 0x3142 /* 16bit */ |
| 397 | #define D29IR 0x3144 /* 16bit */ |
| 398 | #define D28IR 0x3146 /* 16bit */ |
| 399 | #define D27IR 0x3148 /* 16bit */ |
| 400 | #define D26IR 0x314c /* 16bit */ |
| 401 | #define D25IR 0x3150 /* 16bit */ |
| 402 | #define D22IR 0x315c /* 16bit */ |
| 403 | #define OIC 0x31fe /* 16bit */ |
| 404 | #define SOFT_RESET_CTRL 0x38f4 |
| 405 | #define SOFT_RESET_DATA 0x38f8 |
| 406 | |
| 407 | #define DIR_ROUTE(x,a,b,c,d) \ |
| 408 | RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ |
| 409 | ((b) << DIR_IBR) | ((a) << DIR_IAR)) |
| 410 | |
| 411 | #define RC 0x3400 /* 32bit */ |
| 412 | #define HPTC 0x3404 /* 32bit */ |
| 413 | #define GCS 0x3410 /* 32bit */ |
| 414 | #define BUC 0x3414 /* 32bit */ |
| 415 | #define PCH_DISABLE_GBE (1 << 5) |
| 416 | #define FD 0x3418 /* 32bit */ |
| 417 | #define DISPBDF 0x3424 /* 16bit */ |
| 418 | #define FD2 0x3428 /* 32bit */ |
| 419 | #define CG 0x341c /* 32bit */ |
| 420 | |
| 421 | /* Function Disable 1 RCBA 0x3418 */ |
| 422 | #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27)) |
| 423 | #define PCH_DISABLE_P2P (1 << 1) |
| 424 | #define PCH_DISABLE_SATA1 (1 << 2) |
| 425 | #define PCH_DISABLE_SMBUS (1 << 3) |
| 426 | #define PCH_DISABLE_HD_AUDIO (1 << 4) |
| 427 | #define PCH_DISABLE_EHCI2 (1 << 13) |
| 428 | #define PCH_DISABLE_LPC (1 << 14) |
| 429 | #define PCH_DISABLE_EHCI1 (1 << 15) |
| 430 | #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) |
| 431 | #define PCH_DISABLE_THERMAL (1 << 24) |
| 432 | #define PCH_DISABLE_SATA2 (1 << 25) |
| 433 | |
| 434 | /* Function Disable 2 RCBA 0x3428 */ |
| 435 | #define PCH_DISABLE_KT (1 << 4) |
| 436 | #define PCH_DISABLE_IDER (1 << 3) |
| 437 | #define PCH_DISABLE_MEI2 (1 << 2) |
| 438 | #define PCH_DISABLE_MEI1 (1 << 1) |
| 439 | #define PCH_ENABLE_DBDF (1 << 0) |
| 440 | |
| 441 | /* ICH7 GPIOBASE */ |
| 442 | #define GPIO_USE_SEL 0x00 |
| 443 | #define GP_IO_SEL 0x04 |
| 444 | #define GP_LVL 0x0c |
| 445 | #define GPO_BLINK 0x18 |
| 446 | #define GPI_INV 0x2c |
| 447 | #define GPIO_USE_SEL2 0x30 |
| 448 | #define GP_IO_SEL2 0x34 |
| 449 | #define GP_LVL2 0x38 |
| 450 | #define GPIO_USE_SEL3 0x40 |
| 451 | #define GP_IO_SEL3 0x44 |
| 452 | #define GP_LVL3 0x48 |
| 453 | #define GP_RST_SEL1 0x60 |
| 454 | #define GP_RST_SEL2 0x64 |
| 455 | #define GP_RST_SEL3 0x68 |
| 456 | |
| 457 | /* ICH7 PMBASE */ |
| 458 | #define PM1_STS 0x00 |
| 459 | #define WAK_STS (1 << 15) |
| 460 | #define PCIEXPWAK_STS (1 << 14) |
| 461 | #define PRBTNOR_STS (1 << 11) |
| 462 | #define RTC_STS (1 << 10) |
| 463 | #define PWRBTN_STS (1 << 8) |
| 464 | #define GBL_STS (1 << 5) |
| 465 | #define BM_STS (1 << 4) |
| 466 | #define TMROF_STS (1 << 0) |
| 467 | #define PM1_EN 0x02 |
| 468 | #define PCIEXPWAK_DIS (1 << 14) |
| 469 | #define RTC_EN (1 << 10) |
| 470 | #define PWRBTN_EN (1 << 8) |
| 471 | #define GBL_EN (1 << 5) |
| 472 | #define TMROF_EN (1 << 0) |
| 473 | #define PM1_CNT 0x04 |
| 474 | #define SLP_EN (1 << 13) |
| 475 | #define SLP_TYP (7 << 10) |
| 476 | #define SLP_TYP_S0 0 |
| 477 | #define SLP_TYP_S1 1 |
| 478 | #define SLP_TYP_S3 5 |
| 479 | #define SLP_TYP_S4 6 |
| 480 | #define SLP_TYP_S5 7 |
| 481 | #define GBL_RLS (1 << 2) |
| 482 | #define BM_RLD (1 << 1) |
| 483 | #define SCI_EN (1 << 0) |
| 484 | #define PM1_TMR 0x08 |
| 485 | #define PROC_CNT 0x10 |
| 486 | #define LV2 0x14 |
| 487 | #define LV3 0x15 |
| 488 | #define LV4 0x16 |
| 489 | #define PM2_CNT 0x50 // mobile only |
| 490 | #define GPE0_STS 0x20 |
| 491 | #define PME_B0_STS (1 << 13) |
| 492 | #define PME_STS (1 << 11) |
| 493 | #define BATLOW_STS (1 << 10) |
| 494 | #define PCI_EXP_STS (1 << 9) |
| 495 | #define RI_STS (1 << 8) |
| 496 | #define SMB_WAK_STS (1 << 7) |
| 497 | #define TCOSCI_STS (1 << 6) |
| 498 | #define SWGPE_STS (1 << 2) |
| 499 | #define HOT_PLUG_STS (1 << 1) |
| 500 | #define GPE0_EN 0x28 |
| 501 | #define PME_B0_EN (1 << 13) |
| 502 | #define PME_EN (1 << 11) |
| 503 | #define TCOSCI_EN (1 << 6) |
| 504 | #define SMI_EN 0x30 |
| 505 | #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic |
| 506 | #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic |
| 507 | #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS |
| 508 | #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) |
| 509 | #define MCSMI_EN (1 << 11) // Trap microcontroller range access |
| 510 | #define BIOS_RLS (1 << 7) // asserts SCI on bit set |
| 511 | #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set |
| 512 | #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# |
| 513 | #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# |
| 514 | #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic |
| 515 | #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit |
| 516 | #define EOS (1 << 1) // End of SMI (deassert SMI#) |
| 517 | #define GBL_SMI_EN (1 << 0) // SMI# generation at all? |
| 518 | #define SMI_STS 0x34 |
| 519 | #define ALT_GP_SMI_EN 0x38 |
| 520 | #define ALT_GP_SMI_STS 0x3a |
| 521 | #define GPE_CNTL 0x42 |
| 522 | #define DEVACT_STS 0x44 |
| 523 | #define SS_CNT 0x50 |
| 524 | #define C3_RES 0x54 |
| 525 | #define TCO1_STS 0x64 |
| 526 | #define DMISCI_STS (1 << 9) |
| 527 | #define TCO2_STS 0x66 |
| 528 | |
| 529 | /* |
| 530 | * SPI Opcode Menu setup for SPIBAR lockdown |
| 531 | * should support most common flash chips. |
| 532 | */ |
| 533 | |
| 534 | #define SPIBAR_OFFSET 0x3800 |
| 535 | #define SPIBAR8(x) RCBA8(x + SPIBAR_OFFSET) |
| 536 | #define SPIBAR16(x) RCBA16(x + SPIBAR_OFFSET) |
| 537 | #define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET) |
| 538 | |
| 539 | /* Reigsters within the SPIBAR */ |
| 540 | #define SSFC 0x91 |
| 541 | #define FDOC 0xb0 |
| 542 | #define FDOD 0xb4 |
| 543 | |
| 544 | #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ |
| 545 | #define SPI_OPTYPE_0 0x01 /* Write, no address */ |
| 546 | |
| 547 | #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ |
| 548 | #define SPI_OPTYPE_1 0x03 /* Write, address required */ |
| 549 | |
| 550 | #define SPI_OPMENU_2 0x03 /* READ: Read Data */ |
| 551 | #define SPI_OPTYPE_2 0x02 /* Read, address required */ |
| 552 | |
| 553 | #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ |
| 554 | #define SPI_OPTYPE_3 0x00 /* Read, no address */ |
| 555 | |
| 556 | #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ |
| 557 | #define SPI_OPTYPE_4 0x03 /* Write, address required */ |
| 558 | |
| 559 | #define SPI_OPMENU_5 0x9f /* RDID: Read ID */ |
| 560 | #define SPI_OPTYPE_5 0x00 /* Read, no address */ |
| 561 | |
| 562 | #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ |
| 563 | #define SPI_OPTYPE_6 0x03 /* Write, address required */ |
| 564 | |
| 565 | #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ |
| 566 | #define SPI_OPTYPE_7 0x02 /* Read, address required */ |
| 567 | |
| 568 | #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ |
| 569 | (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) |
| 570 | #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ |
| 571 | (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) |
| 572 | |
| 573 | #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ |
| 574 | (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ |
| 575 | (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ |
| 576 | (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) |
| 577 | |
| 578 | #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ |
| 579 | |
| 580 | #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ |
| 581 | #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ |
| 582 | #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ |
| 583 | #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ |
| 584 | #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ |
| 585 | #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ |
| 586 | #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) |
| 587 | #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ |
| 588 | #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ |
| 589 | #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ |
| 590 | #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ |
| 591 | #define SPIBAR_FADDR 0x3808 /* SPI flash address */ |
| 592 | #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ |
| 593 | |
| 594 | #endif /* __ACPI__ */ |
| 595 | #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */ |