Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Subrata Banik | 72d616c | 2023-11-30 19:09:46 +0530 | [diff] [blame] | 4 | #include <bootmode.h> |
Subrata Banik | 0cf2674 | 2023-05-16 12:18:00 +0530 | [diff] [blame] | 5 | #include <bootsplash.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 6 | #include <console/console.h> |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 7 | #include <cpu/intel/microcode.h> |
Jeremy Compostella | a2a7fec | 2023-01-19 19:06:09 -0700 | [diff] [blame] | 8 | #include <delay.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 11 | #include <device/pci_ids.h> |
Jeremy Compostella | a2a7fec | 2023-01-19 19:06:09 -0700 | [diff] [blame] | 12 | #include <device/pci_ops.h> |
| 13 | #include <drivers/intel/gma/i915_reg.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 14 | #include <fsp/api.h> |
Subrata Banik | 7cb6d72 | 2022-03-23 01:33:27 +0530 | [diff] [blame] | 15 | #include <fsp/fsp_debug_event.h> |
Subrata Banik | 03dfc21 | 2023-08-16 02:50:16 +0530 | [diff] [blame] | 16 | #include <fsp/fsp_gop_blt.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <fsp/ppi/mp_service_ppi.h> |
| 18 | #include <fsp/util.h> |
Dinesh Gehlot | d910fec | 2022-12-25 13:00:04 +0000 | [diff] [blame] | 19 | #include <gpio.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 20 | #include <intelblocks/irq.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 21 | #include <intelblocks/lpss.h> |
Subrata Banik | b6c3a03 | 2022-06-05 22:39:34 +0530 | [diff] [blame] | 22 | #include <intelblocks/mp_init.h> |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 23 | #include <intelblocks/pmclib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 24 | #include <intelblocks/xdci.h> |
| 25 | #include <intelpch/lockdown.h> |
Subrata Banik | b6c3a03 | 2022-06-05 22:39:34 +0530 | [diff] [blame] | 26 | #include <intelblocks/systemagent.h> |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 27 | #include <intelblocks/tcss.h> |
Dinesh Gehlot | d910fec | 2022-12-25 13:00:04 +0000 | [diff] [blame] | 28 | #include <option.h> |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 29 | #include <soc/cpu.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 30 | #include <soc/intel/common/vbt.h> |
| 31 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 32 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 33 | #include <soc/ramstage.h> |
| 34 | #include <soc/soc_chip.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 35 | #include <stdlib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 36 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 37 | #include <types.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 38 | |
| 39 | /* THC assignment definition */ |
| 40 | #define THC_NONE 0 |
| 41 | #define THC_0 1 |
| 42 | #define THC_1 2 |
| 43 | |
| 44 | /* SATA DEVSLP idle timeout default values */ |
| 45 | #define DEF_DMVAL 15 |
| 46 | #define DEF_DITOVAL 625 |
| 47 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 48 | /* VccIn Aux Imon IccMax values in mA */ |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 49 | #define MILLIAMPS_TO_AMPS 1000 |
| 50 | #define ICC_MAX_TDP_45W 34250 |
| 51 | #define ICC_MAX_TDP_15W_28W 32000 |
| 52 | #define ICC_MAX_ID_ADL_M_MA 12000 |
V Sowmya | 2af9602 | 2022-04-05 17:03:04 +0530 | [diff] [blame] | 53 | #define ICC_MAX_ID_ADL_N_MA 27000 |
Michał Żygowski | bda2a15 | 2022-04-25 15:02:10 +0200 | [diff] [blame] | 54 | #define ICC_MAX_ADL_S 33000 |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 55 | #define ICC_MAX_RPL_S 36000 |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 56 | |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 57 | /* |
| 58 | * ME End of Post configuration |
| 59 | * 0 - Disable EOP. |
| 60 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 61 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 62 | */ |
| 63 | enum fsp_end_of_post { |
| 64 | EOP_DISABLE = 0, |
| 65 | EOP_PEI = 1, |
| 66 | EOP_DXE = 2, |
| 67 | }; |
| 68 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 69 | static const struct slot_irq_constraints irq_constraints[] = { |
| 70 | { |
Tim Crawford | b739d80 | 2022-07-29 12:07:15 -0600 | [diff] [blame] | 71 | .slot = SA_DEV_SLOT_CPU_1, |
| 72 | .fns = { |
| 73 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_0, PCI_INT_A, PIRQ_A), |
| 74 | }, |
| 75 | }, |
| 76 | { |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 77 | .slot = SA_DEV_SLOT_IGD, |
| 78 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 79 | /* INTERRUPT_PIN is RO/0x01 */ |
| 80 | FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 81 | }, |
| 82 | }, |
| 83 | { |
| 84 | .slot = SA_DEV_SLOT_DPTF, |
| 85 | .fns = { |
| 86 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 87 | }, |
| 88 | }, |
| 89 | { |
| 90 | .slot = SA_DEV_SLOT_IPU, |
| 91 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 92 | /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, |
| 93 | but S0ix fails when not set to 16 (b/193434192) */ |
| 94 | FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 95 | }, |
| 96 | }, |
| 97 | { |
| 98 | .slot = SA_DEV_SLOT_CPU_6, |
| 99 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 100 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A), |
| 101 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 102 | }, |
| 103 | }, |
| 104 | { |
| 105 | .slot = SA_DEV_SLOT_TBT, |
| 106 | .fns = { |
| 107 | ANY_PIRQ(SA_DEVFN_TBT0), |
| 108 | ANY_PIRQ(SA_DEVFN_TBT1), |
| 109 | ANY_PIRQ(SA_DEVFN_TBT2), |
| 110 | ANY_PIRQ(SA_DEVFN_TBT3), |
| 111 | }, |
| 112 | }, |
| 113 | { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 114 | .slot = SA_DEV_SLOT_GNA, |
| 115 | .fns = { |
| 116 | /* INTERRUPT_PIN is RO/0x01 */ |
| 117 | FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A), |
| 118 | }, |
| 119 | }, |
| 120 | { |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 121 | .slot = SA_DEV_SLOT_TCSS, |
| 122 | .fns = { |
| 123 | ANY_PIRQ(SA_DEVFN_TCSS_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 124 | ANY_PIRQ(SA_DEVFN_TCSS_XDCI), |
| 125 | }, |
| 126 | }, |
| 127 | { |
| 128 | .slot = PCH_DEV_SLOT_SIO0, |
| 129 | .fns = { |
| 130 | DIRECT_IRQ(PCH_DEVFN_I2C6), |
| 131 | DIRECT_IRQ(PCH_DEVFN_I2C7), |
| 132 | ANY_PIRQ(PCH_DEVFN_THC0), |
| 133 | ANY_PIRQ(PCH_DEVFN_THC1), |
| 134 | }, |
| 135 | }, |
| 136 | { |
| 137 | .slot = PCH_DEV_SLOT_SIO6, |
| 138 | .fns = { |
| 139 | DIRECT_IRQ(PCH_DEVFN_UART3), |
| 140 | DIRECT_IRQ(PCH_DEVFN_UART4), |
| 141 | DIRECT_IRQ(PCH_DEVFN_UART5), |
| 142 | DIRECT_IRQ(PCH_DEVFN_UART6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 143 | }, |
| 144 | }, |
| 145 | { |
| 146 | .slot = PCH_DEV_SLOT_ISH, |
| 147 | .fns = { |
| 148 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 149 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 150 | ANY_PIRQ(PCH_DEVFN_UFS), |
| 151 | }, |
| 152 | }, |
| 153 | { |
| 154 | .slot = PCH_DEV_SLOT_SIO2, |
| 155 | .fns = { |
| 156 | DIRECT_IRQ(PCH_DEVFN_GSPI3), |
| 157 | DIRECT_IRQ(PCH_DEVFN_GSPI4), |
| 158 | DIRECT_IRQ(PCH_DEVFN_GSPI5), |
| 159 | DIRECT_IRQ(PCH_DEVFN_GSPI6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 160 | }, |
| 161 | }, |
| 162 | { |
| 163 | .slot = PCH_DEV_SLOT_XHCI, |
| 164 | .fns = { |
| 165 | ANY_PIRQ(PCH_DEVFN_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 166 | DIRECT_IRQ(PCH_DEVFN_USBOTG), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 167 | ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), |
| 168 | }, |
| 169 | }, |
| 170 | { |
| 171 | .slot = PCH_DEV_SLOT_SIO3, |
| 172 | .fns = { |
| 173 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 174 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 175 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 176 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 177 | }, |
| 178 | }, |
| 179 | { |
| 180 | .slot = PCH_DEV_SLOT_CSE, |
| 181 | .fns = { |
| 182 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 183 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 184 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 185 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 186 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 187 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 188 | }, |
| 189 | }, |
| 190 | { |
| 191 | .slot = PCH_DEV_SLOT_SATA, |
| 192 | .fns = { |
| 193 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 194 | }, |
| 195 | }, |
| 196 | { |
| 197 | .slot = PCH_DEV_SLOT_SIO4, |
| 198 | .fns = { |
| 199 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 200 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 201 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 202 | }, |
| 203 | }, |
Krishna Prasad Bhat | a6d642f | 2022-01-16 23:16:24 +0530 | [diff] [blame] | 204 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 205 | { |
| 206 | .slot = PCH_DEV_SLOT_EMMC, |
| 207 | .fns = { |
| 208 | ANY_PIRQ(PCH_DEVFN_EMMC), |
| 209 | }, |
| 210 | }, |
| 211 | #endif |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 212 | { |
| 213 | .slot = PCH_DEV_SLOT_PCIE, |
| 214 | .fns = { |
| 215 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 216 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 217 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 218 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 219 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 220 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 221 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 222 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 223 | }, |
| 224 | }, |
| 225 | { |
| 226 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 227 | .fns = { |
| 228 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 229 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 230 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 231 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 232 | }, |
| 233 | }, |
| 234 | { |
| 235 | .slot = PCH_DEV_SLOT_SIO5, |
| 236 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 237 | /* UART0 shares an interrupt line with TSN0, so must use |
| 238 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 239 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 240 | /* UART1 shares an interrupt line with TSN1, so must use |
| 241 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 242 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 243 | DIRECT_IRQ(PCH_DEVFN_GSPI0), |
| 244 | DIRECT_IRQ(PCH_DEVFN_GSPI1), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 245 | }, |
| 246 | }, |
| 247 | { |
| 248 | .slot = PCH_DEV_SLOT_ESPI, |
| 249 | .fns = { |
| 250 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 251 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 252 | ANY_PIRQ(PCH_DEVFN_GBE), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 253 | /* INTERRUPT_PIN is RO/0x01 */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 254 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 255 | }, |
| 256 | }, |
| 257 | }; |
| 258 | |
Michał Żygowski | 72704be | 2022-06-20 18:10:14 +0200 | [diff] [blame] | 259 | static const struct slot_irq_constraints irq_constraints_pch_s[] = { |
| 260 | { |
| 261 | .slot = SA_DEV_SLOT_CPU_1, |
| 262 | .fns = { |
| 263 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_0, PCI_INT_A, PIRQ_A), |
| 264 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_1, PCI_INT_B, PIRQ_B), |
| 265 | }, |
| 266 | }, |
| 267 | { |
| 268 | .slot = SA_DEV_SLOT_IGD, |
| 269 | .fns = { |
| 270 | /* INTERRUPT_PIN is RO/0x01 */ |
| 271 | FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A), |
| 272 | }, |
| 273 | }, |
| 274 | { |
| 275 | .slot = SA_DEV_SLOT_DPTF, |
| 276 | .fns = { |
| 277 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 278 | }, |
| 279 | }, |
| 280 | { |
| 281 | .slot = SA_DEV_SLOT_CPU_6, |
| 282 | .fns = { |
| 283 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_D, PIRQ_A), |
| 284 | }, |
| 285 | }, |
| 286 | { |
| 287 | .slot = SA_DEV_SLOT_GNA, |
| 288 | .fns = { |
| 289 | /* INTERRUPT_PIN is RO/0x01 */ |
| 290 | FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A), |
| 291 | }, |
| 292 | }, |
| 293 | { |
| 294 | .slot = PCH_DEV_SLOT_SIO6, |
| 295 | .fns = { |
| 296 | DIRECT_IRQ(PCH_DEVFN_UART3), |
| 297 | }, |
| 298 | }, |
| 299 | { |
| 300 | .slot = PCH_DEV_SLOT_ISH, |
| 301 | .fns = { |
| 302 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 303 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
| 304 | }, |
| 305 | }, |
| 306 | { |
| 307 | .slot = PCH_DEV_SLOT_SIO2, |
| 308 | .fns = { |
| 309 | DIRECT_IRQ(PCH_DEVFN_GSPI3), |
| 310 | }, |
| 311 | }, |
| 312 | { |
| 313 | .slot = PCH_DEV_SLOT_XHCI, |
| 314 | .fns = { |
| 315 | ANY_PIRQ(PCH_DEVFN_XHCI), |
| 316 | DIRECT_IRQ(PCH_DEVFN_USBOTG), |
| 317 | ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), |
| 318 | }, |
| 319 | }, |
| 320 | { |
| 321 | .slot = PCH_DEV_SLOT_SIO3, |
| 322 | .fns = { |
| 323 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 324 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 325 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 326 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 327 | }, |
| 328 | }, |
| 329 | { |
| 330 | .slot = PCH_DEV_SLOT_CSE, |
| 331 | .fns = { |
| 332 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 333 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 334 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 335 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 336 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 337 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 338 | }, |
| 339 | }, |
| 340 | { |
| 341 | .slot = PCH_DEV_SLOT_SATA, |
| 342 | .fns = { |
| 343 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 344 | }, |
| 345 | }, |
| 346 | { |
| 347 | .slot = PCH_DEV_SLOT_SIO4, |
| 348 | .fns = { |
| 349 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 350 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 351 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 352 | }, |
| 353 | }, |
| 354 | { |
| 355 | .slot = PCH_DEV_SLOT_PCIE, |
| 356 | .fns = { |
| 357 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 358 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 359 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 360 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 361 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 362 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 363 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 364 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 365 | }, |
| 366 | }, |
| 367 | { |
| 368 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 369 | .fns = { |
| 370 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 371 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 372 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 373 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 374 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE13, PCI_INT_A, PIRQ_A), |
| 375 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE14, PCI_INT_B, PIRQ_B), |
| 376 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE15, PCI_INT_C, PIRQ_C), |
| 377 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE16, PCI_INT_D, PIRQ_D), |
| 378 | }, |
| 379 | }, |
| 380 | { |
| 381 | .slot = PCH_DEV_SLOT_PCIE_2, |
| 382 | .fns = { |
| 383 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE17, PCI_INT_A, PIRQ_A), |
| 384 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE18, PCI_INT_B, PIRQ_B), |
| 385 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE19, PCI_INT_C, PIRQ_C), |
| 386 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE20, PCI_INT_D, PIRQ_D), |
| 387 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE21, PCI_INT_A, PIRQ_A), |
| 388 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE22, PCI_INT_B, PIRQ_B), |
| 389 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE23, PCI_INT_C, PIRQ_C), |
| 390 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE24, PCI_INT_D, PIRQ_D), |
| 391 | }, |
| 392 | }, |
| 393 | { |
| 394 | .slot = PCH_DEV_SLOT_PCIE_3, |
| 395 | .fns = { |
| 396 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE25, PCI_INT_A, PIRQ_A), |
| 397 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE26, PCI_INT_B, PIRQ_B), |
| 398 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE27, PCI_INT_C, PIRQ_C), |
| 399 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE28, PCI_INT_D, PIRQ_D), |
| 400 | }, |
| 401 | }, |
| 402 | { |
| 403 | .slot = PCH_DEV_SLOT_SIO5, |
| 404 | .fns = { |
| 405 | /* UART0 shares an interrupt line with TSN0, so must use |
| 406 | a PIRQ */ |
| 407 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
| 408 | /* UART1 shares an interrupt line with TSN1, so must use |
| 409 | a PIRQ */ |
| 410 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
| 411 | DIRECT_IRQ(PCH_DEVFN_GSPI0), |
| 412 | DIRECT_IRQ(PCH_DEVFN_GSPI1), |
| 413 | }, |
| 414 | }, |
| 415 | { |
| 416 | .slot = PCH_DEV_SLOT_ESPI, |
| 417 | .fns = { |
| 418 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 419 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 420 | ANY_PIRQ(PCH_DEVFN_GBE), |
| 421 | /* INTERRUPT_PIN is RO/0x01 */ |
| 422 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 423 | }, |
| 424 | }, |
| 425 | }; |
| 426 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 427 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) |
| 428 | { |
| 429 | const struct pci_irq_entry *entry = get_cached_pci_irqs(); |
| 430 | SI_PCH_DEVICE_INTERRUPT_CONFIG *config; |
| 431 | size_t pch_total = 0; |
| 432 | size_t cfg_count = 0; |
| 433 | |
| 434 | if (!entry) |
| 435 | return NULL; |
| 436 | |
| 437 | /* Count PCH devices */ |
| 438 | while (entry) { |
Kapil Porwal | 9395cf9 | 2022-12-22 23:08:26 +0530 | [diff] [blame] | 439 | if (is_pch_slot(entry->devfn)) |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 440 | ++pch_total; |
| 441 | entry = entry->next; |
| 442 | } |
| 443 | |
| 444 | /* Convert PCH device entries to FSP format */ |
| 445 | config = calloc(pch_total, sizeof(*config)); |
| 446 | entry = get_cached_pci_irqs(); |
| 447 | while (entry) { |
Kapil Porwal | 9395cf9 | 2022-12-22 23:08:26 +0530 | [diff] [blame] | 448 | if (!is_pch_slot(entry->devfn)) { |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 449 | entry = entry->next; |
| 450 | continue; |
| 451 | } |
| 452 | |
| 453 | config[cfg_count].Device = PCI_SLOT(entry->devfn); |
| 454 | config[cfg_count].Function = PCI_FUNC(entry->devfn); |
| 455 | config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; |
| 456 | config[cfg_count].Irq = entry->irq; |
| 457 | ++cfg_count; |
| 458 | |
| 459 | entry = entry->next; |
| 460 | } |
| 461 | |
| 462 | *out_count = cfg_count; |
| 463 | |
| 464 | return config; |
| 465 | } |
| 466 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 467 | /* |
| 468 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 469 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 470 | * In order to ensure that mainboard setting does not disable L1 substates |
| 471 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 472 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 473 | * value is set in fsp_params. |
| 474 | * 0: Use FSP UPD default |
| 475 | * 1: Disable L1 substates |
| 476 | * 2: Use L1.1 |
| 477 | * 3: Use L1.2 (FSP UPD default) |
| 478 | */ |
| 479 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 480 | { |
Bora Guvendik | 8c46232 | 2022-11-29 15:45:06 -0800 | [diff] [blame] | 481 | if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) |
| 482 | ctl = L1_SS_DISABLED; |
| 483 | else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 484 | ctl = L1_SS_L1_2; |
| 485 | return ctl - 1; |
| 486 | } |
| 487 | |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 488 | /* |
Jeremy Soller | d59c799 | 2023-05-16 15:04:08 -0600 | [diff] [blame] | 489 | * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because |
| 490 | * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure |
| 491 | * that the mainboard setting does not disable ASPM incorrectly, chip |
| 492 | * config parameter values are offset by 1 with 0 meaning use FSP UPD default. |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 493 | * get_aspm_control() ensures that the right UPD value is set in fsp_params. |
Jeremy Soller | d59c799 | 2023-05-16 15:04:08 -0600 | [diff] [blame] | 494 | * 0: Use FSP UPD default |
| 495 | * 1: Disable ASPM |
| 496 | * 2: L0s only |
| 497 | * 3: L1 only |
| 498 | * 4: L0s and L1 |
| 499 | * 5: Auto configuration |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 500 | */ |
| 501 | static unsigned int get_aspm_control(enum ASPM_control ctl) |
| 502 | { |
Jeremy Soller | d59c799 | 2023-05-16 15:04:08 -0600 | [diff] [blame] | 503 | if ((ctl > ASPM_AUTO) || (ctl == ASPM_DEFAULT)) |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 504 | ctl = ASPM_AUTO; |
Jeremy Soller | d59c799 | 2023-05-16 15:04:08 -0600 | [diff] [blame] | 505 | return ctl - 1; |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 506 | } |
| 507 | |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 508 | /* This function returns the VccIn Aux Imon IccMax values for ADL and RPL |
| 509 | SKU's */ |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 510 | static uint16_t get_vccin_aux_imon_iccmax(void) |
| 511 | { |
Jeremy Compostella | cb08c79 | 2022-06-30 16:31:14 -0700 | [diff] [blame] | 512 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 513 | uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 514 | uint8_t tdp; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 515 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 516 | switch (mch_id) { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 517 | case PCI_DID_INTEL_ADL_P_ID_1: |
| 518 | case PCI_DID_INTEL_ADL_P_ID_3: |
Curtis Chen | 3fc3e6c | 2022-03-10 11:51:38 +0800 | [diff] [blame] | 519 | case PCI_DID_INTEL_ADL_P_ID_4: |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 520 | case PCI_DID_INTEL_ADL_P_ID_5: |
| 521 | case PCI_DID_INTEL_ADL_P_ID_6: |
| 522 | case PCI_DID_INTEL_ADL_P_ID_7: |
Curtis Chen | 3fc3e6c | 2022-03-10 11:51:38 +0800 | [diff] [blame] | 523 | case PCI_DID_INTEL_ADL_P_ID_8: |
| 524 | case PCI_DID_INTEL_ADL_P_ID_9: |
| 525 | case PCI_DID_INTEL_ADL_P_ID_10: |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 526 | case PCI_DID_INTEL_RPL_P_ID_1: |
| 527 | case PCI_DID_INTEL_RPL_P_ID_2: |
| 528 | case PCI_DID_INTEL_RPL_P_ID_3: |
Lawrence Chang | 0a5da51 | 2022-10-19 14:38:41 +0800 | [diff] [blame] | 529 | case PCI_DID_INTEL_RPL_P_ID_4: |
Marx Wang | 39ede0a | 2022-12-20 10:48:33 +0800 | [diff] [blame] | 530 | case PCI_DID_INTEL_RPL_P_ID_5: |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 531 | tdp = get_cpu_tdp(); |
| 532 | if (tdp == TDP_45W) |
| 533 | return ICC_MAX_TDP_45W; |
| 534 | return ICC_MAX_TDP_15W_28W; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 535 | case PCI_DID_INTEL_ADL_M_ID_1: |
| 536 | case PCI_DID_INTEL_ADL_M_ID_2: |
Bora Guvendik | 3160595 | 2021-09-01 17:32:07 -0700 | [diff] [blame] | 537 | return ICC_MAX_ID_ADL_M_MA; |
V Sowmya | 2af9602 | 2022-04-05 17:03:04 +0530 | [diff] [blame] | 538 | case PCI_DID_INTEL_ADL_N_ID_1: |
| 539 | case PCI_DID_INTEL_ADL_N_ID_2: |
| 540 | case PCI_DID_INTEL_ADL_N_ID_3: |
| 541 | case PCI_DID_INTEL_ADL_N_ID_4: |
Sean Rhodes | 00b81ad | 2024-02-13 20:44:52 +0000 | [diff] [blame] | 542 | case PCI_DID_INTEL_ADL_N_ID_5: |
V Sowmya | 2af9602 | 2022-04-05 17:03:04 +0530 | [diff] [blame] | 543 | return ICC_MAX_ID_ADL_N_MA; |
Michał Żygowski | bda2a15 | 2022-04-25 15:02:10 +0200 | [diff] [blame] | 544 | case PCI_DID_INTEL_ADL_S_ID_1: |
| 545 | case PCI_DID_INTEL_ADL_S_ID_3: |
| 546 | case PCI_DID_INTEL_ADL_S_ID_8: |
| 547 | case PCI_DID_INTEL_ADL_S_ID_10: |
Michał Żygowski | a01b62a | 2022-07-21 18:08:19 +0200 | [diff] [blame] | 548 | case PCI_DID_INTEL_ADL_S_ID_11: |
| 549 | case PCI_DID_INTEL_ADL_S_ID_12: |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 550 | case PCI_DID_INTEL_RPL_HX_ID_1: |
| 551 | case PCI_DID_INTEL_RPL_HX_ID_2: |
| 552 | case PCI_DID_INTEL_RPL_HX_ID_3: |
| 553 | case PCI_DID_INTEL_RPL_HX_ID_4: |
| 554 | case PCI_DID_INTEL_RPL_HX_ID_5: |
| 555 | case PCI_DID_INTEL_RPL_HX_ID_6: |
| 556 | case PCI_DID_INTEL_RPL_HX_ID_7: |
| 557 | case PCI_DID_INTEL_RPL_HX_ID_8: |
Michał Żygowski | bda2a15 | 2022-04-25 15:02:10 +0200 | [diff] [blame] | 558 | return ICC_MAX_ADL_S; |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 559 | case PCI_DID_INTEL_RPL_S_ID_1: |
| 560 | case PCI_DID_INTEL_RPL_S_ID_2: |
| 561 | case PCI_DID_INTEL_RPL_S_ID_3: |
| 562 | case PCI_DID_INTEL_RPL_S_ID_4: |
| 563 | case PCI_DID_INTEL_RPL_S_ID_5: |
| 564 | return ICC_MAX_RPL_S; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 565 | default: |
| 566 | printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", |
| 567 | mch_id); |
| 568 | return 0; |
| 569 | } |
| 570 | } |
| 571 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 572 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 573 | { |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 574 | /* Override settings per board. */ |
| 575 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 576 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 577 | static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, |
| 578 | const struct soc_intel_alderlake_config *config) |
| 579 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 580 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 581 | s_cfg->SerialIoI2cMode[i] = config->serial_io_i2c_mode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 582 | |
| 583 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 584 | s_cfg->SerialIoSpiMode[i] = config->serial_io_gspi_mode[i]; |
| 585 | s_cfg->SerialIoSpiCsMode[i] = config->serial_io_gspi_cs_mode[i]; |
| 586 | s_cfg->SerialIoSpiCsState[i] = config->serial_io_gspi_cs_state[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 590 | s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 591 | } |
| 592 | |
Subrata Banik | fad1cb0 | 2022-08-12 18:12:46 +0530 | [diff] [blame] | 593 | static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 594 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 595 | { |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 596 | const struct microcode *microcode_file; |
| 597 | size_t microcode_len; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 598 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 599 | /* Locate microcode and pass to FSP-S for 2nd microcode loading */ |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 600 | microcode_file = intel_microcode_find(); |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 601 | |
Selma Bensaid | 291294d | 2021-10-11 16:37:36 -0700 | [diff] [blame] | 602 | if (microcode_file != NULL) { |
| 603 | microcode_len = get_microcode_size(microcode_file); |
| 604 | if (microcode_len != 0) { |
| 605 | /* Update CPU Microcode patch base address/size */ |
| 606 | s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; |
| 607 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
| 608 | } |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 609 | } |
Subrata Banik | fad1cb0 | 2022-08-12 18:12:46 +0530 | [diff] [blame] | 610 | } |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 611 | |
Subrata Banik | fad1cb0 | 2022-08-12 18:12:46 +0530 | [diff] [blame] | 612 | static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, |
| 613 | const struct soc_intel_alderlake_config *config) |
| 614 | { |
Subrata Banik | 8409f15 | 2022-08-15 17:08:13 +0530 | [diff] [blame] | 615 | /* |
| 616 | * FIXME: FSP assumes ownership of the APs (Application Processors) |
| 617 | * upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. |
| 618 | * Hence, pass a valid pointer to the CpuMpPpi UPD unconditionally. |
| 619 | * This would avoid APs from getting hijacked by FSP while coreboot |
| 620 | * decides to set SkipMpInit UPD. |
| 621 | */ |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 622 | s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); |
Subrata Banik | 8409f15 | 2022-08-15 17:08:13 +0530 | [diff] [blame] | 623 | |
Subrata Banik | a247319 | 2023-02-22 13:03:04 +0000 | [diff] [blame] | 624 | if (CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS)) |
Subrata Banik | ceaf9d1 | 2022-06-05 19:33:33 +0530 | [diff] [blame] | 625 | /* |
Subrata Banik | fad1cb0 | 2022-08-12 18:12:46 +0530 | [diff] [blame] | 626 | * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature |
| 627 | * programming. |
| 628 | */ |
| 629 | fill_fsps_microcode_params(s_cfg, config); |
Subrata Banik | 8409f15 | 2022-08-15 17:08:13 +0530 | [diff] [blame] | 630 | else |
Subrata Banik | ceaf9d1 | 2022-06-05 19:33:33 +0530 | [diff] [blame] | 631 | s_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, |
| 635 | const struct soc_intel_alderlake_config *config) |
| 636 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 637 | /* Load VBT before devicetree-specific config. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 638 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 639 | |
| 640 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 641 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
Subrata Banik | 72d616c | 2023-11-30 19:09:46 +0530 | [diff] [blame] | 642 | s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); |
Lean Sheng Tan | e8df93a | 2022-04-01 19:07:53 +0200 | [diff] [blame] | 643 | s_cfg->PavpEnable = CONFIG(PAVP); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 644 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 645 | |
Michał Kopeć | 75a49fe | 2022-04-08 11:28:45 +0200 | [diff] [blame] | 646 | WEAK_DEV_PTR(tcss_usb3_port1); |
| 647 | WEAK_DEV_PTR(tcss_usb3_port2); |
| 648 | WEAK_DEV_PTR(tcss_usb3_port3); |
| 649 | WEAK_DEV_PTR(tcss_usb3_port4); |
| 650 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 651 | static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, |
| 652 | const struct soc_intel_alderlake_config *config) |
| 653 | { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 654 | const struct device *tcss_port_arr[] = { |
| 655 | DEV_PTR(tcss_usb3_port1), |
| 656 | DEV_PTR(tcss_usb3_port2), |
| 657 | DEV_PTR(tcss_usb3_port3), |
| 658 | DEV_PTR(tcss_usb3_port4), |
| 659 | }; |
| 660 | |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 661 | s_cfg->TcssAuxOri = config->tcss_aux_ori; |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 662 | |
| 663 | /* Explicitly clear this field to avoid using defaults */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 664 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 665 | |
| 666 | /* |
| 667 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 668 | * evaluate this UPD value and skip sending command. There will be no |
| 669 | * delay for command completion. |
| 670 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 671 | s_cfg->ITbtConnectTopologyTimeoutInMs = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 672 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 673 | /* D3Hot and D3Cold for TCSS */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 674 | s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; |
Sean Rhodes | 6bb11a3 | 2023-04-17 20:29:45 +0100 | [diff] [blame] | 675 | s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT); |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 676 | |
| 677 | s_cfg->UsbTcPortEn = 0; |
| 678 | for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 679 | if (is_dev_enabled(tcss_port_arr[i])) |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 680 | s_cfg->UsbTcPortEn |= BIT(i); |
| 681 | } |
Sean Rhodes | fb401e7 | 2023-08-30 13:14:21 +0100 | [diff] [blame^] | 682 | |
| 683 | #if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) |
| 684 | s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER); |
| 685 | #endif |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 686 | } |
| 687 | |
| 688 | static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |
| 689 | const struct soc_intel_alderlake_config *config) |
| 690 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 691 | /* Chipset Lockdown */ |
Felix Singer | f9d7dc7 | 2021-05-03 02:33:15 +0200 | [diff] [blame] | 692 | const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |
| 693 | s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp; |
| 694 | s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; |
Subrata Banik | 393b093 | 2022-01-11 11:59:39 +0530 | [diff] [blame] | 695 | s_cfg->PchUnlockGpioPads = lockdown_by_fsp; |
Felix Singer | f9d7dc7 | 2021-05-03 02:33:15 +0200 | [diff] [blame] | 696 | s_cfg->RtcMemoryLock = lockdown_by_fsp; |
Tim Wawrzynczak | 091dfa1 | 2021-08-24 09:32:09 -0600 | [diff] [blame] | 697 | s_cfg->SkipPamLock = !lockdown_by_fsp; |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 698 | |
| 699 | /* coreboot will send EOP before loading payload */ |
| 700 | s_cfg->EndOfPostMessage = EOP_DISABLE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 701 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 702 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 703 | static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, |
| 704 | const struct soc_intel_alderlake_config *config) |
| 705 | { |
| 706 | int i; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 707 | /* USB */ |
| 708 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 709 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 710 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 711 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 712 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 713 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 714 | |
| 715 | if (config->usb2_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 716 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 717 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 718 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
Anil Kumar | c6b65c1 | 2022-02-01 12:59:03 -0800 | [diff] [blame] | 719 | |
| 720 | if (config->usb2_ports[i].type_c) |
| 721 | s_cfg->PortResetMessageEnable[i] = 1; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 722 | } |
| 723 | |
| 724 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 725 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 726 | if (config->usb3_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 727 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 728 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 729 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 730 | |
| 731 | if (config->usb3_ports[i].tx_de_emp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 732 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 733 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 734 | } |
| 735 | if (config->usb3_ports[i].tx_downscale_amp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 736 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 737 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 738 | config->usb3_ports[i].tx_downscale_amp; |
| 739 | } |
| 740 | } |
| 741 | |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 742 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 743 | if (config->tcss_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 744 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 745 | } |
Sridhar Siricilla | 37c3305 | 2022-04-02 10:33:00 +0530 | [diff] [blame] | 746 | |
| 747 | s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 748 | } |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 749 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 750 | static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, |
| 751 | const struct soc_intel_alderlake_config *config) |
| 752 | { |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 753 | s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 754 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 755 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 756 | static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |
| 757 | const struct soc_intel_alderlake_config *config) |
| 758 | { |
Subrata Banik | 88381c9 | 2022-03-29 11:26:11 +0530 | [diff] [blame] | 759 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && |
| 760 | CONFIG(FSP_ENABLE_SERIAL_DEBUG)) |
| 761 | s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) |
| 762 | fsp_debug_event_handler); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 763 | /* PCH UART selection for FSP Debug */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 764 | s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 765 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 766 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 767 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 768 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 769 | static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, |
| 770 | const struct soc_intel_alderlake_config *config) |
| 771 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 772 | /* SATA */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 773 | s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
| 774 | if (s_cfg->SataEnable) { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 775 | s_cfg->SataMode = config->sata_mode; |
| 776 | s_cfg->SataSalpSupport = config->sata_salp_support; |
| 777 | memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable, |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 778 | sizeof(s_cfg->SataPortsEnable)); |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 779 | memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp, |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 780 | sizeof(s_cfg->SataPortsDevSlp)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 781 | } |
| 782 | |
| 783 | /* |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 784 | * Power Optimizer for SATA. |
| 785 | * SataPwrOptimizeDisable is default to 0. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 786 | * Boards not needing the optimizers explicitly disables them by setting |
| 787 | * these disable variables to 1 in devicetree overrides. |
| 788 | */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 789 | s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable); |
Lean Sheng Tan | 1ec8f97 | 2022-09-07 16:07:33 +0200 | [diff] [blame] | 790 | /* Test mode for SATA margining */ |
| 791 | s_cfg->SataTestMode = CONFIG(ENABLE_SATA_TEST_MODE); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 792 | /* |
| 793 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 794 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 795 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 796 | * The default values can be changed from devicetree. |
| 797 | */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 798 | for (size_t i = 0; i < ARRAY_SIZE(config->sata_ports_enable_dito_config); i++) { |
| 799 | if (config->sata_ports_enable_dito_config[i]) { |
| 800 | s_cfg->SataPortsDmVal[i] = config->sata_ports_dm_val[i]; |
| 801 | s_cfg->SataPortsDitoVal[i] = config->sata_ports_dito_val[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 802 | } |
| 803 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 804 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 805 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 806 | static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, |
| 807 | const struct soc_intel_alderlake_config *config) |
| 808 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 809 | /* Enable TCPU for processor thermal control */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 810 | s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 811 | |
| 812 | /* Set TccActivationOffset */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 813 | s_cfg->TccActivationOffset = config->tcc_offset; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 814 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 815 | |
Jeremy Soller | 9601b1e | 2022-05-26 10:21:36 -0600 | [diff] [blame] | 816 | static void fill_fsps_gna_params(FSP_S_CONFIG *s_cfg, |
| 817 | const struct soc_intel_alderlake_config *config) |
| 818 | { |
| 819 | s_cfg->GnaEnable = is_devfn_enabled(SA_DEVFN_GNA); |
| 820 | } |
| 821 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 822 | static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, |
| 823 | const struct soc_intel_alderlake_config *config) |
| 824 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 825 | /* LAN */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 826 | s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 827 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 828 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 829 | static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, |
| 830 | const struct soc_intel_alderlake_config *config) |
| 831 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 832 | /* CNVi */ |
Michał Żygowski | 01025d3 | 2023-07-12 13:22:09 +0200 | [diff] [blame] | 833 | #if CONFIG(FSP_USE_REPO) |
| 834 | /* This option is only available in public FSP headers on FSP repo */ |
Michał Żygowski | 9707464 | 2022-06-30 18:19:27 +0200 | [diff] [blame] | 835 | s_cfg->CnviWifiCore = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
| 836 | #endif |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 837 | s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 838 | s_cfg->CnviBtCore = config->cnvi_bt_core; |
| 839 | s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 840 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 841 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 842 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 843 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 844 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 845 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 846 | static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, |
| 847 | const struct soc_intel_alderlake_config *config) |
| 848 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 849 | /* VMD */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 850 | s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 851 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 852 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 853 | static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, |
| 854 | const struct soc_intel_alderlake_config *config) |
| 855 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 856 | /* THC */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 857 | s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; |
| 858 | s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 859 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 860 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 861 | static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, |
| 862 | const struct soc_intel_alderlake_config *config) |
| 863 | { |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 864 | /* USB4/TBT */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 865 | for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 866 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i)); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 867 | } |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 868 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 869 | static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, |
| 870 | const struct soc_intel_alderlake_config *config) |
| 871 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 872 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 873 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 874 | s_cfg->Enable8254ClockGating = !use_8254; |
| 875 | s_cfg->Enable8254ClockGatingOnS3 = !use_8254; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 876 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 877 | |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 878 | static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, |
| 879 | const struct soc_intel_alderlake_config *config) |
| 880 | { |
| 881 | /* |
| 882 | * Legacy PM ACPI Timer (and TCO Timer) |
| 883 | * This *must* be 1 in any case to keep FSP from |
| 884 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 885 | * 2) disabling the PM ACPI Timer. |
| 886 | * We handle both by ourself! |
| 887 | */ |
| 888 | s_cfg->EnableTcoTimer = 1; |
| 889 | } |
| 890 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 891 | static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, |
| 892 | const struct soc_intel_alderlake_config *config) |
| 893 | { |
Krishna Prasad Bhat | a6d642f | 2022-01-16 23:16:24 +0530 | [diff] [blame] | 894 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 895 | /* eMMC Configuration */ |
| 896 | s_cfg->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); |
| 897 | if (s_cfg->ScsEmmcEnabled) |
| 898 | s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode; |
| 899 | #endif |
Meera Ravindranath | d8ea360 | 2022-03-16 15:27:00 +0530 | [diff] [blame] | 900 | |
| 901 | /* UFS Configuration */ |
| 902 | s_cfg->UfsEnable[0] = 0; /* UFS Controller 0 is fuse disabled */ |
| 903 | s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS); |
| 904 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 905 | /* Enable Hybrid storage auto detection */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 906 | s_cfg->HybridStorageMode = config->hybrid_storage_mode; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 907 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 908 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 909 | static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, |
| 910 | const struct soc_intel_alderlake_config *config) |
| 911 | { |
| 912 | uint32_t enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
| 913 | for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 914 | if (!(enable_mask & BIT(i))) |
| 915 | continue; |
| 916 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 917 | s_cfg->PcieRpL1Substates[i] = |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 918 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 919 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 920 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 921 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) |
| 922 | || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 923 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 924 | if (rp_cfg->pcie_rp_aspm) |
| 925 | s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); |
Cliff Huang | 61a442ec | 2022-04-28 18:06:54 -0700 | [diff] [blame] | 926 | /* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */ |
| 927 | if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN)) |
| 928 | s_cfg->PcieRpSlotImplemented[i] = 0; |
| 929 | s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 930 | } |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 931 | s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Patrick Rudolph | b8abde7 | 2023-07-21 09:09:07 +0200 | [diff] [blame] | 932 | |
Michał Żygowski | 12a1fc2 | 2023-08-21 11:12:04 +0200 | [diff] [blame] | 933 | #if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_RAPTORLAKE) |
Patrick Rudolph | b8abde7 | 2023-07-21 09:09:07 +0200 | [diff] [blame] | 934 | /* |
| 935 | * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. |
| 936 | * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 |
| 937 | * link-state is also entered on PCI-PM D3, even with ASPM L1 disabled. |
| 938 | * When no CLK_REQ signal is used, for example when it's using a free running |
| 939 | * clock the Root port silicon will never wake from L1 link state. |
| 940 | * This will trigger a MCE. |
| 941 | * |
| 942 | * Starting with FSP MR4 the UPD 'PchPcieClockGating' allows to work around |
| 943 | * this issue by disabling ClockGating. Disabling ClockGating should be avoided |
| 944 | * as the silicon draws more power when it is idle. |
| 945 | */ |
| 946 | for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
| 947 | bool clk_req_missing = false; |
| 948 | if (!(enable_mask & BIT(i))) |
| 949 | continue; |
| 950 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
| 951 | if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { |
| 952 | clk_req_missing = true; |
| 953 | } else if (!rp_cfg->flags && rp_cfg->clk_src == 0 && rp_cfg->clk_req == 0) { |
| 954 | clk_req_missing = true; |
| 955 | } else if (rp_cfg->flags & PCIE_RP_CLK_REQ_UNUSED) { |
| 956 | clk_req_missing = true; |
| 957 | } |
| 958 | if (clk_req_missing) { |
| 959 | printk(BIOS_INFO, "PCH PCIe port %d has no CLK_REQ\n", i + 1); |
| 960 | printk(BIOS_INFO, "Disabling PCH PCIE ClockGating+PowerGating.\n"); |
| 961 | s_cfg->PchPcieClockGating = false; |
| 962 | s_cfg->PchPciePowerGating = false; |
| 963 | break; |
| 964 | } |
| 965 | } |
| 966 | #endif |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 967 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 968 | |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 969 | static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg, |
| 970 | const struct soc_intel_alderlake_config *config) |
| 971 | { |
| 972 | if (!CONFIG_MAX_CPU_ROOT_PORTS) |
| 973 | return; |
| 974 | |
| 975 | const uint32_t enable_mask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); |
| 976 | for (int i = 0; i < CONFIG_MAX_CPU_ROOT_PORTS; i++) { |
| 977 | if (!(enable_mask & BIT(i))) |
| 978 | continue; |
| 979 | |
| 980 | const struct pcie_rp_config *rp_cfg = &config->cpu_pcie_rp[i]; |
| 981 | s_cfg->CpuPcieRpL1Substates[i] = |
| 982 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
| 983 | s_cfg->CpuPcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 984 | s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 985 | s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) |
| 986 | || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Tim Wawrzynczak | d6b763c | 2022-07-27 09:53:58 -0600 | [diff] [blame] | 987 | s_cfg->CpuPcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 988 | s_cfg->PtmEnabled[i] = 0; |
Tim Wawrzynczak | d6b763c | 2022-07-27 09:53:58 -0600 | [diff] [blame] | 989 | if (rp_cfg->pcie_rp_aspm) |
| 990 | s_cfg->CpuPcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); |
| 991 | |
| 992 | if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN)) |
| 993 | s_cfg->CpuPcieRpSlotImplemented[i] = 0; |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 994 | } |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 995 | s_cfg->CpuPcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 996 | } |
| 997 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 998 | static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, |
| 999 | const struct soc_intel_alderlake_config *config) |
| 1000 | { |
Anil Kumar | e822fb3 | 2023-02-09 16:55:57 -0800 | [diff] [blame] | 1001 | u32 cpu_id = cpu_get_cpuid(); |
Subrata Banik | d6da4ef | 2021-10-07 00:39:31 +0530 | [diff] [blame] | 1002 | /* Skip setting D0I3 bit for all HECI devices */ |
| 1003 | s_cfg->DisableD0I3SettingForHeci = 1; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1004 | /* |
| 1005 | * Power Optimizer for DMI |
| 1006 | * DmiPwrOptimizeDisable is default to 0. |
| 1007 | * Boards not needing the optimizers explicitly disables them by setting |
| 1008 | * these disable variables to 1 in devicetree overrides. |
| 1009 | */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 1010 | s_cfg->PchPwrOptEnable = !(config->dmi_power_optimize_disable); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 1011 | s_cfg->PmSupport = 1; |
| 1012 | s_cfg->Hwp = 1; |
| 1013 | s_cfg->Cx = 1; |
| 1014 | s_cfg->PsOnEnable = 1; |
V Sowmya | af42906 | 2021-06-21 10:23:33 +0530 | [diff] [blame] | 1015 | s_cfg->PkgCStateLimit = LIMIT_AUTO; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 1016 | |
Jeremy Compostella | 92d3899 | 2022-09-14 11:06:06 -0700 | [diff] [blame] | 1017 | /* Disable Energy Efficient Turbo mode */ |
| 1018 | s_cfg->EnergyEfficientTurbo = 0; |
| 1019 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 1020 | /* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */ |
| 1021 | s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax() * 4 / MILLIAMPS_TO_AMPS; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 1022 | |
| 1023 | /* VrConfig Settings for IA and GT domains */ |
| 1024 | for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 1025 | fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 1026 | |
Nick Vaccaro | 577afe6 | 2022-01-12 12:03:41 -0800 | [diff] [blame] | 1027 | s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 1028 | |
| 1029 | /* Apply minimum assertion width settings */ |
| 1030 | if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT) |
| 1031 | s_cfg->PchPmSlpS3MinAssert = SLP_S3_ASSERTION_50_MS; |
| 1032 | else |
| 1033 | s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width; |
| 1034 | |
| 1035 | if (config->pch_slp_s4_min_assertion_width == SLP_S4_ASSERTION_DEFAULT) |
| 1036 | s_cfg->PchPmSlpS4MinAssert = SLP_S4_ASSERTION_1S; |
| 1037 | else |
| 1038 | s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width; |
| 1039 | |
| 1040 | if (config->pch_slp_sus_min_assertion_width == SLP_SUS_ASSERTION_DEFAULT) |
| 1041 | s_cfg->PchPmSlpSusMinAssert = SLP_SUS_ASSERTION_4_S; |
| 1042 | else |
| 1043 | s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width; |
| 1044 | |
| 1045 | if (config->pch_slp_a_min_assertion_width == SLP_A_ASSERTION_DEFAULT) |
| 1046 | s_cfg->PchPmSlpAMinAssert = SLP_A_ASSERTION_2_S; |
| 1047 | else |
| 1048 | s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width; |
| 1049 | |
| 1050 | unsigned int power_cycle_duration = config->pch_reset_power_cycle_duration; |
| 1051 | if (power_cycle_duration == POWER_CYCLE_DURATION_DEFAULT) |
| 1052 | power_cycle_duration = POWER_CYCLE_DURATION_4S; |
| 1053 | |
| 1054 | s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(s_cfg->PchPmSlpS4MinAssert, |
| 1055 | s_cfg->PchPmSlpS3MinAssert, |
| 1056 | s_cfg->PchPmSlpAMinAssert, |
| 1057 | power_cycle_duration); |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 1058 | |
| 1059 | /* Set PsysPmax if it is available from DT */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 1060 | if (config->platform_pmax) { |
| 1061 | printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->platform_pmax); |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 1062 | /* PsysPmax is in unit of 1/8 Watt */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 1063 | s_cfg->PsysPmax = config->platform_pmax * 8; |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 1064 | } |
MAULIK V VAGHELA | 9935638 | 2022-03-03 13:07:57 +0530 | [diff] [blame] | 1065 | |
| 1066 | s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion; |
Lean Sheng Tan | 4b45d4c | 2022-04-01 19:01:59 +0200 | [diff] [blame] | 1067 | |
| 1068 | s_cfg->VrPowerDeliveryDesign = config->vr_power_delivery_design; |
V Sowmya | 4be8d9e | 2022-07-05 20:49:57 +0530 | [diff] [blame] | 1069 | |
Sean Rhodes | 42f8b59 | 2023-08-08 13:46:53 +0100 | [diff] [blame] | 1070 | /* C state demotion must be disabled for Raptorlake J0 and Q0 SKUs */ |
| 1071 | assert(!(config->s0ix_enable && ((cpu_id == CPUID_RAPTORLAKE_J0) || |
| 1072 | (cpu_id == CPUID_RAPTORLAKE_Q0)) && |
| 1073 | !config->disable_package_c_state_demotion)); |
| 1074 | |
| 1075 | s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; |
Joey Peng | ea2a38b | 2023-04-25 15:18:00 +0800 | [diff] [blame] | 1076 | |
Michał Żygowski | d54a5b29 | 2023-07-03 17:17:32 +0200 | [diff] [blame] | 1077 | if (cpu_id == CPUID_RAPTORLAKE_J0 || cpu_id == CPUID_RAPTORLAKE_Q0) |
Sean Rhodes | 06f4f65 | 2023-08-08 13:56:37 +0100 | [diff] [blame] | 1078 | s_cfg->C1e = config->enable_c1e; |
Joey Peng | ea2a38b | 2023-04-25 15:18:00 +0800 | [diff] [blame] | 1079 | else |
| 1080 | s_cfg->C1e = 1; |
Michał Żygowski | 01025d3 | 2023-07-12 13:22:09 +0200 | [diff] [blame] | 1081 | #if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) |
Bora Guvendik | 6e64c01 | 2023-04-24 18:12:19 -0700 | [diff] [blame] | 1082 | s_cfg->EnableHwpScalabilityTracking = config->enable_hwp_scalability_tracking; |
| 1083 | #endif |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 1084 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1085 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 1086 | static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |
| 1087 | const struct soc_intel_alderlake_config *config) |
| 1088 | { |
Michał Żygowski | 72704be | 2022-06-20 18:10:14 +0200 | [diff] [blame] | 1089 | const struct slot_irq_constraints *constraints; |
| 1090 | size_t num_slots; |
| 1091 | |
| 1092 | if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) { |
| 1093 | constraints = irq_constraints_pch_s; |
| 1094 | num_slots = ARRAY_SIZE(irq_constraints_pch_s); |
| 1095 | } else { |
| 1096 | constraints = irq_constraints; |
| 1097 | num_slots = ARRAY_SIZE(irq_constraints); |
| 1098 | } |
| 1099 | |
| 1100 | if (!assign_pci_irqs(constraints, num_slots)) |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 1101 | die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); |
| 1102 | |
| 1103 | size_t pch_count = 0; |
| 1104 | const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); |
| 1105 | |
| 1106 | s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); |
| 1107 | s_cfg->NumOfDevIntConfig = pch_count; |
| 1108 | printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); |
| 1109 | } |
| 1110 | |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 1111 | static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, |
| 1112 | const struct soc_intel_alderlake_config *config) |
| 1113 | { |
| 1114 | /* PCH FIVR settings override */ |
| 1115 | if (!config->ext_fivr_settings.configure_ext_fivr) |
| 1116 | return; |
| 1117 | |
| 1118 | s_cfg->PchFivrExtV1p05RailEnabledStates = |
| 1119 | config->ext_fivr_settings.v1p05_enable_bitmap; |
| 1120 | |
| 1121 | s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = |
| 1122 | config->ext_fivr_settings.v1p05_supported_voltage_bitmap; |
| 1123 | |
| 1124 | s_cfg->PchFivrExtVnnRailEnabledStates = |
| 1125 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 1126 | |
| 1127 | s_cfg->PchFivrExtVnnRailSupportedVoltageStates = |
| 1128 | config->ext_fivr_settings.vnn_supported_voltage_bitmap; |
| 1129 | |
| 1130 | s_cfg->PchFivrExtVnnRailSxEnabledStates = |
Bora Guvendik | fbf874f | 2021-10-18 14:17:41 -0700 | [diff] [blame] | 1131 | config->ext_fivr_settings.vnn_sx_enable_bitmap; |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 1132 | |
| 1133 | /* Convert the voltages to increments of 2.5mv */ |
| 1134 | s_cfg->PchFivrExtV1p05RailVoltage = |
| 1135 | (config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25; |
| 1136 | |
| 1137 | s_cfg->PchFivrExtVnnRailVoltage = |
| 1138 | (config->ext_fivr_settings.vnn_voltage_mv * 10) / 25; |
| 1139 | |
| 1140 | s_cfg->PchFivrExtVnnRailSxVoltage = |
| 1141 | (config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25); |
| 1142 | |
| 1143 | s_cfg->PchFivrExtV1p05RailIccMaximum = |
| 1144 | config->ext_fivr_settings.v1p05_icc_max_ma; |
| 1145 | |
| 1146 | s_cfg->PchFivrExtVnnRailIccMaximum = |
| 1147 | config->ext_fivr_settings.vnn_icc_max_ma; |
V Sowmya | 036b16b | 2022-10-10 12:46:18 +0530 | [diff] [blame] | 1148 | |
| 1149 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 1150 | /* Enable the FIVR VCCST ICCMax Control for ADL-N. |
| 1151 | * TODO:Right now the UPD is update in partial headers for only ADL-N and when its |
| 1152 | * updated for ADL-P then we will remove the config since this needs to be enabled for |
| 1153 | * all the Alderlake platforms. |
| 1154 | */ |
| 1155 | s_cfg->PchFivrVccstIccMaxControl = 1; |
| 1156 | #endif |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 1157 | } |
| 1158 | |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 1159 | static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg, |
| 1160 | const struct soc_intel_alderlake_config *config) |
| 1161 | { |
| 1162 | /* transform from Hz to 100 KHz */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 1163 | s_cfg->FivrRfiFrequency = config->fivr_rfi_frequency / (100 * KHz); |
| 1164 | s_cfg->FivrSpreadSpectrum = config->fivr_spread_spectrum; |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 1165 | } |
| 1166 | |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1167 | static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg, |
| 1168 | const struct soc_intel_alderlake_config *config) |
| 1169 | { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 1170 | s_cfg->AcousticNoiseMitigation = config->acoustic_noise_mitigation; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1171 | |
| 1172 | if (s_cfg->AcousticNoiseMitigation) { |
leo.chou | aef916a | 2022-05-13 10:41:03 +0800 | [diff] [blame] | 1173 | s_cfg->PreWake = config->PreWake; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1174 | for (int i = 0; i < NUM_VR_DOMAINS; i++) { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 1175 | s_cfg->FastPkgCRampDisable[i] = config->fast_pkg_c_ramp_disable[i]; |
| 1176 | s_cfg->SlowSlewRate[i] = config->slow_slew_rate[i]; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1177 | } |
| 1178 | } |
| 1179 | } |
| 1180 | |
Michał Żygowski | 46d7477 | 2022-04-25 12:15:55 +0200 | [diff] [blame] | 1181 | static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg, |
| 1182 | const struct soc_intel_alderlake_config *config) |
| 1183 | { |
| 1184 | struct device *dev; |
| 1185 | int i; |
| 1186 | /* |
| 1187 | * Prevent FSP from programming write-once subsystem IDs by providing |
| 1188 | * a custom SSID table. Must have at least one entry for the FSP to |
| 1189 | * use the table. |
| 1190 | */ |
| 1191 | struct svid_ssid_init_entry { |
| 1192 | union { |
| 1193 | struct { |
| 1194 | uint64_t reg:12; /* Register offset */ |
| 1195 | uint64_t function:3; |
| 1196 | uint64_t device:5; |
| 1197 | uint64_t bus:8; |
| 1198 | uint64_t :4; |
| 1199 | uint64_t segment:16; |
| 1200 | uint64_t :16; |
| 1201 | }; |
| 1202 | uint64_t segbusdevfuncregister; |
| 1203 | }; |
| 1204 | struct { |
| 1205 | uint16_t svid; |
| 1206 | uint16_t ssid; |
| 1207 | }; |
| 1208 | uint32_t reserved; |
| 1209 | }; |
| 1210 | |
| 1211 | /* |
| 1212 | * The xHCI and HDA devices have RW/L rather than RW/O registers for |
| 1213 | * subsystem IDs and so must be written before FspSiliconInit locks |
| 1214 | * them with their default values. |
| 1215 | */ |
| 1216 | const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA }; |
| 1217 | static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)]; |
| 1218 | |
| 1219 | for (i = 0; i < ARRAY_SIZE(devfn_table); i++) { |
| 1220 | ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; |
| 1221 | ssid_table[i].device = PCI_SLOT(devfn_table[i]); |
| 1222 | ssid_table[i].function = PCI_FUNC(devfn_table[i]); |
| 1223 | dev = pcidev_path_on_root(devfn_table[i]); |
| 1224 | if (dev) { |
| 1225 | ssid_table[i].svid = dev->subsystem_vendor; |
| 1226 | ssid_table[i].ssid = dev->subsystem_device; |
| 1227 | } |
| 1228 | } |
| 1229 | |
| 1230 | s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table; |
| 1231 | s_cfg->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table); |
| 1232 | |
| 1233 | /* |
| 1234 | * Replace the default SVID:SSID value with the values specified in |
| 1235 | * the devicetree for the root device. |
| 1236 | */ |
| 1237 | dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 1238 | s_cfg->SiCustomizedSvid = dev->subsystem_vendor; |
| 1239 | s_cfg->SiCustomizedSsid = dev->subsystem_device; |
| 1240 | |
| 1241 | /* Ensure FSP will program the registers */ |
| 1242 | s_cfg->SiSkipSsidProgramming = 0; |
| 1243 | } |
| 1244 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1245 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
| 1246 | struct soc_intel_alderlake_config *config) |
| 1247 | { |
| 1248 | /* Override settings per board if required. */ |
| 1249 | mainboard_update_soc_chip_config(config); |
| 1250 | |
Arthur Heymans | 02967e6 | 2022-02-18 13:22:25 +0100 | [diff] [blame] | 1251 | void (*const fill_fsps_params[])(FSP_S_CONFIG *s_cfg, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1252 | const struct soc_intel_alderlake_config *config) = { |
| 1253 | fill_fsps_lpss_params, |
| 1254 | fill_fsps_cpu_params, |
| 1255 | fill_fsps_igd_params, |
| 1256 | fill_fsps_tcss_params, |
| 1257 | fill_fsps_chipset_lockdown_params, |
| 1258 | fill_fsps_xhci_params, |
| 1259 | fill_fsps_xdci_params, |
| 1260 | fill_fsps_uart_params, |
| 1261 | fill_fsps_sata_params, |
| 1262 | fill_fsps_thermal_params, |
Jeremy Soller | 9601b1e | 2022-05-26 10:21:36 -0600 | [diff] [blame] | 1263 | fill_fsps_gna_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1264 | fill_fsps_lan_params, |
| 1265 | fill_fsps_cnvi_params, |
| 1266 | fill_fsps_vmd_params, |
| 1267 | fill_fsps_thc_params, |
| 1268 | fill_fsps_tbt_params, |
| 1269 | fill_fsps_8254_params, |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 1270 | fill_fsps_pm_timer_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1271 | fill_fsps_storage_params, |
| 1272 | fill_fsps_pcie_params, |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 1273 | fill_fsps_cpu_pcie_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1274 | fill_fsps_misc_power_params, |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 1275 | fill_fsps_irq_params, |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 1276 | fill_fsps_fivr_params, |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 1277 | fill_fsps_fivr_rfi_params, |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1278 | fill_fsps_acoustic_params, |
Michał Żygowski | 46d7477 | 2022-04-25 12:15:55 +0200 | [diff] [blame] | 1279 | fill_fsps_pci_ssid_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1280 | }; |
| 1281 | |
| 1282 | for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |
| 1283 | fill_fsps_params[i](s_cfg, config); |
| 1284 | } |
| 1285 | |
Jeremy Compostella | a2a7fec | 2023-01-19 19:06:09 -0700 | [diff] [blame] | 1286 | /* |
| 1287 | * The Alder Lake PEIM graphics driver executed as part of the FSP does not wait |
| 1288 | * for the panel power cycle to complete before it initializes communication |
| 1289 | * with the display. It can result in AUX channel communication time out and |
| 1290 | * PEIM graphics driver failing to bring up graphics. |
| 1291 | * |
| 1292 | * If we have performed some graphics operations in romstage, it is possible |
| 1293 | * that a panel power cycle is still in progress. To prevent any issue with the |
| 1294 | * PEIM graphics driver it is preferable to ensure that panel power cycle is |
| 1295 | * complete. |
| 1296 | * |
| 1297 | * BUG:b:264526798 |
| 1298 | */ |
| 1299 | static void wait_for_panel_power_cycle_done(const struct soc_intel_alderlake_config *config) |
| 1300 | { |
| 1301 | const struct i915_gpu_panel_config *panel_cfg; |
| 1302 | uint32_t bar0; |
| 1303 | void *mmio; |
| 1304 | |
| 1305 | if (!CONFIG(RUN_FSP_GOP)) |
| 1306 | return; |
| 1307 | |
| 1308 | bar0 = pci_s_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0); |
| 1309 | mmio = (void *)(bar0 & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); |
| 1310 | if (!mmio) |
| 1311 | return; |
| 1312 | |
| 1313 | panel_cfg = &config->panel_cfg; |
| 1314 | for (size_t i = 0;; i++) { |
| 1315 | uint32_t status = read32(mmio + PCH_PP_STATUS); |
| 1316 | if (!(status & PANEL_POWER_CYCLE_ACTIVE)) |
| 1317 | break; |
| 1318 | if (i == panel_cfg->cycle_delay_ms) { |
| 1319 | printk(BIOS_ERR, "Panel power cycle is still active.\n"); |
| 1320 | break; |
| 1321 | } |
| 1322 | mdelay(1); |
| 1323 | } |
| 1324 | } |
| 1325 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 1326 | /* UPD parameters to be initialized before SiliconInit */ |
| 1327 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 1328 | { |
| 1329 | struct soc_intel_alderlake_config *config; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 1330 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 1331 | |
| 1332 | config = config_of_soc(); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 1333 | soc_silicon_init_params(s_cfg, config); |
| 1334 | mainboard_silicon_init_params(s_cfg); |
Jeremy Compostella | a2a7fec | 2023-01-19 19:06:09 -0700 | [diff] [blame] | 1335 | |
| 1336 | wait_for_panel_power_cycle_done(config); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1337 | } |
| 1338 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1339 | /* |
| 1340 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 1341 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 1342 | * Phase | FSP return point | Purpose |
| 1343 | * ------- + ------------------------------------------------ + ------------------------------- |
| 1344 | * 1 | After TCSS initialization completed | for TCSS specific init |
Subrata Banik | b6c3a03 | 2022-06-05 22:39:34 +0530 | [diff] [blame] | 1345 | * 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1346 | */ |
| 1347 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 1348 | { |
| 1349 | switch (phase_index) { |
| 1350 | case 1: |
| 1351 | /* TCSS specific initialization here */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 1352 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 1353 | __FILE__, __func__); |
| 1354 | |
| 1355 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 1356 | const config_t *config = config_of_soc(); |
| 1357 | tcss_configure(config->typec_aux_bias_pads); |
| 1358 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1359 | break; |
Subrata Banik | b6c3a03 | 2022-06-05 22:39:34 +0530 | [diff] [blame] | 1360 | case 2: |
| 1361 | /* CPU specific initialization here */ |
| 1362 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 1363 | __FILE__, __func__); |
| 1364 | before_post_cpus_init(); |
| 1365 | /* Enable BIOS Reset CPL */ |
| 1366 | enable_bios_reset_cpl(); |
| 1367 | break; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1368 | default: |
| 1369 | break; |
| 1370 | } |
| 1371 | } |
| 1372 | |
| 1373 | /* Mainboard GPIO Configuration */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 1374 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1375 | { |
| 1376 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 1377 | } |
Subrata Banik | 0cf2674 | 2023-05-16 12:18:00 +0530 | [diff] [blame] | 1378 | |
| 1379 | /* Handle FSP logo params */ |
| 1380 | void soc_load_logo(FSPS_UPD *supd) |
| 1381 | { |
Subrata Banik | 03dfc21 | 2023-08-16 02:50:16 +0530 | [diff] [blame] | 1382 | fsp_convert_bmp_to_gop_blt(&supd->FspsConfig.LogoPtr, |
| 1383 | &supd->FspsConfig.LogoSize, |
| 1384 | &supd->FspsConfig.BltBufferAddress, |
| 1385 | &supd->FspsConfig.BltBufferSize, |
| 1386 | &supd->FspsConfig.LogoPixelHeight, |
| 1387 | &supd->FspsConfig.LogoPixelWidth); |
Subrata Banik | 0cf2674 | 2023-05-16 12:18:00 +0530 | [diff] [blame] | 1388 | } |