Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 5 | #include <cpu/intel/microcode.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 8 | #include <device/pci_ids.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 9 | #include <fsp/api.h> |
Subrata Banik | 7cb6d72 | 2022-03-23 01:33:27 +0530 | [diff] [blame] | 10 | #include <fsp/fsp_debug_event.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 11 | #include <fsp/ppi/mp_service_ppi.h> |
| 12 | #include <fsp/util.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 13 | #include <option.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 14 | #include <intelblocks/irq.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 15 | #include <intelblocks/lpss.h> |
Subrata Banik | b6c3a03 | 2022-06-05 22:39:34 +0530 | [diff] [blame] | 16 | #include <intelblocks/mp_init.h> |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 17 | #include <intelblocks/pmclib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 18 | #include <intelblocks/xdci.h> |
| 19 | #include <intelpch/lockdown.h> |
Subrata Banik | b6c3a03 | 2022-06-05 22:39:34 +0530 | [diff] [blame] | 20 | #include <intelblocks/systemagent.h> |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 21 | #include <intelblocks/tcss.h> |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 22 | #include <soc/cpu.h> |
Michał Kopeć | febaf2f | 2022-04-07 14:14:31 +0200 | [diff] [blame] | 23 | #include <soc/gpio.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 24 | #include <soc/intel/common/vbt.h> |
| 25 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 26 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 27 | #include <soc/ramstage.h> |
| 28 | #include <soc/soc_chip.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 29 | #include <stdlib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 30 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 31 | #include <types.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 32 | |
| 33 | /* THC assignment definition */ |
| 34 | #define THC_NONE 0 |
| 35 | #define THC_0 1 |
| 36 | #define THC_1 2 |
| 37 | |
| 38 | /* SATA DEVSLP idle timeout default values */ |
| 39 | #define DEF_DMVAL 15 |
| 40 | #define DEF_DITOVAL 625 |
| 41 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 42 | /* VccIn Aux Imon IccMax values in mA */ |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 43 | #define MILLIAMPS_TO_AMPS 1000 |
| 44 | #define ICC_MAX_TDP_45W 34250 |
| 45 | #define ICC_MAX_TDP_15W_28W 32000 |
| 46 | #define ICC_MAX_ID_ADL_M_MA 12000 |
V Sowmya | 2af9602 | 2022-04-05 17:03:04 +0530 | [diff] [blame] | 47 | #define ICC_MAX_ID_ADL_N_MA 27000 |
Michał Żygowski | bda2a15 | 2022-04-25 15:02:10 +0200 | [diff] [blame] | 48 | #define ICC_MAX_ADL_S 33000 |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 49 | |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 50 | /* |
| 51 | * ME End of Post configuration |
| 52 | * 0 - Disable EOP. |
| 53 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 54 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 55 | */ |
| 56 | enum fsp_end_of_post { |
| 57 | EOP_DISABLE = 0, |
| 58 | EOP_PEI = 1, |
| 59 | EOP_DXE = 2, |
| 60 | }; |
| 61 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 62 | static const struct slot_irq_constraints irq_constraints[] = { |
| 63 | { |
Tim Crawford | b739d80 | 2022-07-29 12:07:15 -0600 | [diff] [blame] | 64 | .slot = SA_DEV_SLOT_CPU_1, |
| 65 | .fns = { |
| 66 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_0, PCI_INT_A, PIRQ_A), |
| 67 | }, |
| 68 | }, |
| 69 | { |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 70 | .slot = SA_DEV_SLOT_IGD, |
| 71 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 72 | /* INTERRUPT_PIN is RO/0x01 */ |
| 73 | FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 74 | }, |
| 75 | }, |
| 76 | { |
| 77 | .slot = SA_DEV_SLOT_DPTF, |
| 78 | .fns = { |
| 79 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 80 | }, |
| 81 | }, |
| 82 | { |
| 83 | .slot = SA_DEV_SLOT_IPU, |
| 84 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 85 | /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, |
| 86 | but S0ix fails when not set to 16 (b/193434192) */ |
| 87 | FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 88 | }, |
| 89 | }, |
| 90 | { |
| 91 | .slot = SA_DEV_SLOT_CPU_6, |
| 92 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 93 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A), |
| 94 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 95 | }, |
| 96 | }, |
| 97 | { |
| 98 | .slot = SA_DEV_SLOT_TBT, |
| 99 | .fns = { |
| 100 | ANY_PIRQ(SA_DEVFN_TBT0), |
| 101 | ANY_PIRQ(SA_DEVFN_TBT1), |
| 102 | ANY_PIRQ(SA_DEVFN_TBT2), |
| 103 | ANY_PIRQ(SA_DEVFN_TBT3), |
| 104 | }, |
| 105 | }, |
| 106 | { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 107 | .slot = SA_DEV_SLOT_GNA, |
| 108 | .fns = { |
| 109 | /* INTERRUPT_PIN is RO/0x01 */ |
| 110 | FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A), |
| 111 | }, |
| 112 | }, |
| 113 | { |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 114 | .slot = SA_DEV_SLOT_TCSS, |
| 115 | .fns = { |
| 116 | ANY_PIRQ(SA_DEVFN_TCSS_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 117 | ANY_PIRQ(SA_DEVFN_TCSS_XDCI), |
| 118 | }, |
| 119 | }, |
| 120 | { |
| 121 | .slot = PCH_DEV_SLOT_SIO0, |
| 122 | .fns = { |
| 123 | DIRECT_IRQ(PCH_DEVFN_I2C6), |
| 124 | DIRECT_IRQ(PCH_DEVFN_I2C7), |
| 125 | ANY_PIRQ(PCH_DEVFN_THC0), |
| 126 | ANY_PIRQ(PCH_DEVFN_THC1), |
| 127 | }, |
| 128 | }, |
| 129 | { |
| 130 | .slot = PCH_DEV_SLOT_SIO6, |
| 131 | .fns = { |
| 132 | DIRECT_IRQ(PCH_DEVFN_UART3), |
| 133 | DIRECT_IRQ(PCH_DEVFN_UART4), |
| 134 | DIRECT_IRQ(PCH_DEVFN_UART5), |
| 135 | DIRECT_IRQ(PCH_DEVFN_UART6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 136 | }, |
| 137 | }, |
| 138 | { |
| 139 | .slot = PCH_DEV_SLOT_ISH, |
| 140 | .fns = { |
| 141 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 142 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 143 | ANY_PIRQ(PCH_DEVFN_UFS), |
| 144 | }, |
| 145 | }, |
| 146 | { |
| 147 | .slot = PCH_DEV_SLOT_SIO2, |
| 148 | .fns = { |
| 149 | DIRECT_IRQ(PCH_DEVFN_GSPI3), |
| 150 | DIRECT_IRQ(PCH_DEVFN_GSPI4), |
| 151 | DIRECT_IRQ(PCH_DEVFN_GSPI5), |
| 152 | DIRECT_IRQ(PCH_DEVFN_GSPI6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 153 | }, |
| 154 | }, |
| 155 | { |
| 156 | .slot = PCH_DEV_SLOT_XHCI, |
| 157 | .fns = { |
| 158 | ANY_PIRQ(PCH_DEVFN_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 159 | DIRECT_IRQ(PCH_DEVFN_USBOTG), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 160 | ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), |
| 161 | }, |
| 162 | }, |
| 163 | { |
| 164 | .slot = PCH_DEV_SLOT_SIO3, |
| 165 | .fns = { |
| 166 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 167 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 168 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 169 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 170 | }, |
| 171 | }, |
| 172 | { |
| 173 | .slot = PCH_DEV_SLOT_CSE, |
| 174 | .fns = { |
| 175 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 176 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 177 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 178 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 179 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 180 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 181 | }, |
| 182 | }, |
| 183 | { |
| 184 | .slot = PCH_DEV_SLOT_SATA, |
| 185 | .fns = { |
| 186 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 187 | }, |
| 188 | }, |
| 189 | { |
| 190 | .slot = PCH_DEV_SLOT_SIO4, |
| 191 | .fns = { |
| 192 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 193 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 194 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 195 | }, |
| 196 | }, |
Krishna Prasad Bhat | a6d642f | 2022-01-16 23:16:24 +0530 | [diff] [blame] | 197 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 198 | { |
| 199 | .slot = PCH_DEV_SLOT_EMMC, |
| 200 | .fns = { |
| 201 | ANY_PIRQ(PCH_DEVFN_EMMC), |
| 202 | }, |
| 203 | }, |
| 204 | #endif |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 205 | { |
| 206 | .slot = PCH_DEV_SLOT_PCIE, |
| 207 | .fns = { |
| 208 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 209 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 210 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 211 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 212 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 213 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 214 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 215 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 216 | }, |
| 217 | }, |
| 218 | { |
| 219 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 220 | .fns = { |
| 221 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 222 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 223 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 224 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 225 | }, |
| 226 | }, |
| 227 | { |
| 228 | .slot = PCH_DEV_SLOT_SIO5, |
| 229 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 230 | /* UART0 shares an interrupt line with TSN0, so must use |
| 231 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 232 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 233 | /* UART1 shares an interrupt line with TSN1, so must use |
| 234 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 235 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 236 | DIRECT_IRQ(PCH_DEVFN_GSPI0), |
| 237 | DIRECT_IRQ(PCH_DEVFN_GSPI1), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 238 | }, |
| 239 | }, |
| 240 | { |
| 241 | .slot = PCH_DEV_SLOT_ESPI, |
| 242 | .fns = { |
| 243 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 244 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 245 | ANY_PIRQ(PCH_DEVFN_GBE), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 246 | /* INTERRUPT_PIN is RO/0x01 */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 247 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 248 | }, |
| 249 | }, |
| 250 | }; |
| 251 | |
Michał Żygowski | 72704be | 2022-06-20 18:10:14 +0200 | [diff] [blame] | 252 | static const struct slot_irq_constraints irq_constraints_pch_s[] = { |
| 253 | { |
| 254 | .slot = SA_DEV_SLOT_CPU_1, |
| 255 | .fns = { |
| 256 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_0, PCI_INT_A, PIRQ_A), |
| 257 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_1, PCI_INT_B, PIRQ_B), |
| 258 | }, |
| 259 | }, |
| 260 | { |
| 261 | .slot = SA_DEV_SLOT_IGD, |
| 262 | .fns = { |
| 263 | /* INTERRUPT_PIN is RO/0x01 */ |
| 264 | FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A), |
| 265 | }, |
| 266 | }, |
| 267 | { |
| 268 | .slot = SA_DEV_SLOT_DPTF, |
| 269 | .fns = { |
| 270 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 271 | }, |
| 272 | }, |
| 273 | { |
| 274 | .slot = SA_DEV_SLOT_CPU_6, |
| 275 | .fns = { |
| 276 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_D, PIRQ_A), |
| 277 | }, |
| 278 | }, |
| 279 | { |
| 280 | .slot = SA_DEV_SLOT_GNA, |
| 281 | .fns = { |
| 282 | /* INTERRUPT_PIN is RO/0x01 */ |
| 283 | FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A), |
| 284 | }, |
| 285 | }, |
| 286 | { |
| 287 | .slot = PCH_DEV_SLOT_SIO6, |
| 288 | .fns = { |
| 289 | DIRECT_IRQ(PCH_DEVFN_UART3), |
| 290 | }, |
| 291 | }, |
| 292 | { |
| 293 | .slot = PCH_DEV_SLOT_ISH, |
| 294 | .fns = { |
| 295 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 296 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
| 297 | }, |
| 298 | }, |
| 299 | { |
| 300 | .slot = PCH_DEV_SLOT_SIO2, |
| 301 | .fns = { |
| 302 | DIRECT_IRQ(PCH_DEVFN_GSPI3), |
| 303 | }, |
| 304 | }, |
| 305 | { |
| 306 | .slot = PCH_DEV_SLOT_XHCI, |
| 307 | .fns = { |
| 308 | ANY_PIRQ(PCH_DEVFN_XHCI), |
| 309 | DIRECT_IRQ(PCH_DEVFN_USBOTG), |
| 310 | ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), |
| 311 | }, |
| 312 | }, |
| 313 | { |
| 314 | .slot = PCH_DEV_SLOT_SIO3, |
| 315 | .fns = { |
| 316 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 317 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 318 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 319 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 320 | }, |
| 321 | }, |
| 322 | { |
| 323 | .slot = PCH_DEV_SLOT_CSE, |
| 324 | .fns = { |
| 325 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 326 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 327 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 328 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 329 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 330 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 331 | }, |
| 332 | }, |
| 333 | { |
| 334 | .slot = PCH_DEV_SLOT_SATA, |
| 335 | .fns = { |
| 336 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 337 | }, |
| 338 | }, |
| 339 | { |
| 340 | .slot = PCH_DEV_SLOT_SIO4, |
| 341 | .fns = { |
| 342 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 343 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 344 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 345 | }, |
| 346 | }, |
| 347 | { |
| 348 | .slot = PCH_DEV_SLOT_PCIE, |
| 349 | .fns = { |
| 350 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 351 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 352 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 353 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 354 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 355 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 356 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 357 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 358 | }, |
| 359 | }, |
| 360 | { |
| 361 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 362 | .fns = { |
| 363 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 364 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 365 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 366 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 367 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE13, PCI_INT_A, PIRQ_A), |
| 368 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE14, PCI_INT_B, PIRQ_B), |
| 369 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE15, PCI_INT_C, PIRQ_C), |
| 370 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE16, PCI_INT_D, PIRQ_D), |
| 371 | }, |
| 372 | }, |
| 373 | { |
| 374 | .slot = PCH_DEV_SLOT_PCIE_2, |
| 375 | .fns = { |
| 376 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE17, PCI_INT_A, PIRQ_A), |
| 377 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE18, PCI_INT_B, PIRQ_B), |
| 378 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE19, PCI_INT_C, PIRQ_C), |
| 379 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE20, PCI_INT_D, PIRQ_D), |
| 380 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE21, PCI_INT_A, PIRQ_A), |
| 381 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE22, PCI_INT_B, PIRQ_B), |
| 382 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE23, PCI_INT_C, PIRQ_C), |
| 383 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE24, PCI_INT_D, PIRQ_D), |
| 384 | }, |
| 385 | }, |
| 386 | { |
| 387 | .slot = PCH_DEV_SLOT_PCIE_3, |
| 388 | .fns = { |
| 389 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE25, PCI_INT_A, PIRQ_A), |
| 390 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE26, PCI_INT_B, PIRQ_B), |
| 391 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE27, PCI_INT_C, PIRQ_C), |
| 392 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE28, PCI_INT_D, PIRQ_D), |
| 393 | }, |
| 394 | }, |
| 395 | { |
| 396 | .slot = PCH_DEV_SLOT_SIO5, |
| 397 | .fns = { |
| 398 | /* UART0 shares an interrupt line with TSN0, so must use |
| 399 | a PIRQ */ |
| 400 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
| 401 | /* UART1 shares an interrupt line with TSN1, so must use |
| 402 | a PIRQ */ |
| 403 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
| 404 | DIRECT_IRQ(PCH_DEVFN_GSPI0), |
| 405 | DIRECT_IRQ(PCH_DEVFN_GSPI1), |
| 406 | }, |
| 407 | }, |
| 408 | { |
| 409 | .slot = PCH_DEV_SLOT_ESPI, |
| 410 | .fns = { |
| 411 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 412 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 413 | ANY_PIRQ(PCH_DEVFN_GBE), |
| 414 | /* INTERRUPT_PIN is RO/0x01 */ |
| 415 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 416 | }, |
| 417 | }, |
| 418 | }; |
| 419 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 420 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) |
| 421 | { |
| 422 | const struct pci_irq_entry *entry = get_cached_pci_irqs(); |
| 423 | SI_PCH_DEVICE_INTERRUPT_CONFIG *config; |
| 424 | size_t pch_total = 0; |
| 425 | size_t cfg_count = 0; |
| 426 | |
| 427 | if (!entry) |
| 428 | return NULL; |
| 429 | |
| 430 | /* Count PCH devices */ |
| 431 | while (entry) { |
| 432 | if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) |
| 433 | ++pch_total; |
| 434 | entry = entry->next; |
| 435 | } |
| 436 | |
| 437 | /* Convert PCH device entries to FSP format */ |
| 438 | config = calloc(pch_total, sizeof(*config)); |
| 439 | entry = get_cached_pci_irqs(); |
| 440 | while (entry) { |
| 441 | if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { |
| 442 | entry = entry->next; |
| 443 | continue; |
| 444 | } |
| 445 | |
| 446 | config[cfg_count].Device = PCI_SLOT(entry->devfn); |
| 447 | config[cfg_count].Function = PCI_FUNC(entry->devfn); |
| 448 | config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; |
| 449 | config[cfg_count].Irq = entry->irq; |
| 450 | ++cfg_count; |
| 451 | |
| 452 | entry = entry->next; |
| 453 | } |
| 454 | |
| 455 | *out_count = cfg_count; |
| 456 | |
| 457 | return config; |
| 458 | } |
| 459 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 460 | /* |
| 461 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 462 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 463 | * In order to ensure that mainboard setting does not disable L1 substates |
| 464 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 465 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 466 | * value is set in fsp_params. |
| 467 | * 0: Use FSP UPD default |
| 468 | * 1: Disable L1 substates |
| 469 | * 2: Use L1.1 |
| 470 | * 3: Use L1.2 (FSP UPD default) |
| 471 | */ |
| 472 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 473 | { |
Bora Guvendik | 8c46232 | 2022-11-29 15:45:06 -0800 | [diff] [blame] | 474 | if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) |
| 475 | ctl = L1_SS_DISABLED; |
| 476 | else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 477 | ctl = L1_SS_L1_2; |
| 478 | return ctl - 1; |
| 479 | } |
| 480 | |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 481 | /* |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 482 | * get_aspm_control() ensures that the right UPD value is set in fsp_params. |
Subrata Banik | 5dfec71 | 2022-12-13 14:10:48 +0530 | [diff] [blame] | 483 | * 0: Disable ASPM |
| 484 | * 1: L0s only |
| 485 | * 2: L1 only |
| 486 | * 3: L0s and L1 |
| 487 | * 4: Auto configuration |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 488 | */ |
| 489 | static unsigned int get_aspm_control(enum ASPM_control ctl) |
| 490 | { |
Subrata Banik | 5dfec71 | 2022-12-13 14:10:48 +0530 | [diff] [blame] | 491 | if (ctl > ASPM_AUTO) |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 492 | ctl = ASPM_AUTO; |
Subrata Banik | 5dfec71 | 2022-12-13 14:10:48 +0530 | [diff] [blame] | 493 | return ctl; |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 494 | } |
| 495 | |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 496 | /* This function returns the VccIn Aux Imon IccMax values for ADL and RPL |
| 497 | SKU's */ |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 498 | static uint16_t get_vccin_aux_imon_iccmax(void) |
| 499 | { |
Jeremy Compostella | cb08c79 | 2022-06-30 16:31:14 -0700 | [diff] [blame] | 500 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 501 | uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 502 | uint8_t tdp; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 503 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 504 | switch (mch_id) { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 505 | case PCI_DID_INTEL_ADL_P_ID_1: |
| 506 | case PCI_DID_INTEL_ADL_P_ID_3: |
Curtis Chen | 3fc3e6c | 2022-03-10 11:51:38 +0800 | [diff] [blame] | 507 | case PCI_DID_INTEL_ADL_P_ID_4: |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 508 | case PCI_DID_INTEL_ADL_P_ID_5: |
| 509 | case PCI_DID_INTEL_ADL_P_ID_6: |
| 510 | case PCI_DID_INTEL_ADL_P_ID_7: |
Curtis Chen | 3fc3e6c | 2022-03-10 11:51:38 +0800 | [diff] [blame] | 511 | case PCI_DID_INTEL_ADL_P_ID_8: |
| 512 | case PCI_DID_INTEL_ADL_P_ID_9: |
| 513 | case PCI_DID_INTEL_ADL_P_ID_10: |
Jeremy Compostella | 1b44c81 | 2022-06-17 15:18:02 -0700 | [diff] [blame] | 514 | case PCI_DID_INTEL_RPL_P_ID_1: |
| 515 | case PCI_DID_INTEL_RPL_P_ID_2: |
| 516 | case PCI_DID_INTEL_RPL_P_ID_3: |
Lawrence Chang | 0a5da51 | 2022-10-19 14:38:41 +0800 | [diff] [blame] | 517 | case PCI_DID_INTEL_RPL_P_ID_4: |
Marx Wang | 39ede0a | 2022-12-20 10:48:33 +0800 | [diff] [blame^] | 518 | case PCI_DID_INTEL_RPL_P_ID_5: |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 519 | tdp = get_cpu_tdp(); |
| 520 | if (tdp == TDP_45W) |
| 521 | return ICC_MAX_TDP_45W; |
| 522 | return ICC_MAX_TDP_15W_28W; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 523 | case PCI_DID_INTEL_ADL_M_ID_1: |
| 524 | case PCI_DID_INTEL_ADL_M_ID_2: |
Bora Guvendik | 3160595 | 2021-09-01 17:32:07 -0700 | [diff] [blame] | 525 | return ICC_MAX_ID_ADL_M_MA; |
V Sowmya | 2af9602 | 2022-04-05 17:03:04 +0530 | [diff] [blame] | 526 | case PCI_DID_INTEL_ADL_N_ID_1: |
| 527 | case PCI_DID_INTEL_ADL_N_ID_2: |
| 528 | case PCI_DID_INTEL_ADL_N_ID_3: |
| 529 | case PCI_DID_INTEL_ADL_N_ID_4: |
| 530 | return ICC_MAX_ID_ADL_N_MA; |
Michał Żygowski | bda2a15 | 2022-04-25 15:02:10 +0200 | [diff] [blame] | 531 | case PCI_DID_INTEL_ADL_S_ID_1: |
| 532 | case PCI_DID_INTEL_ADL_S_ID_3: |
| 533 | case PCI_DID_INTEL_ADL_S_ID_8: |
| 534 | case PCI_DID_INTEL_ADL_S_ID_10: |
Michał Żygowski | a01b62a | 2022-07-21 18:08:19 +0200 | [diff] [blame] | 535 | case PCI_DID_INTEL_ADL_S_ID_11: |
| 536 | case PCI_DID_INTEL_ADL_S_ID_12: |
Michał Żygowski | bda2a15 | 2022-04-25 15:02:10 +0200 | [diff] [blame] | 537 | return ICC_MAX_ADL_S; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 538 | default: |
| 539 | printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", |
| 540 | mch_id); |
| 541 | return 0; |
| 542 | } |
| 543 | } |
| 544 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 545 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 546 | { |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 547 | /* Override settings per board. */ |
| 548 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 549 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 550 | static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, |
| 551 | const struct soc_intel_alderlake_config *config) |
| 552 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 553 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 554 | s_cfg->SerialIoI2cMode[i] = config->serial_io_i2c_mode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 555 | |
| 556 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 557 | s_cfg->SerialIoSpiMode[i] = config->serial_io_gspi_mode[i]; |
| 558 | s_cfg->SerialIoSpiCsMode[i] = config->serial_io_gspi_cs_mode[i]; |
| 559 | s_cfg->SerialIoSpiCsState[i] = config->serial_io_gspi_cs_state[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 563 | s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 564 | } |
| 565 | |
Subrata Banik | fad1cb0 | 2022-08-12 18:12:46 +0530 | [diff] [blame] | 566 | static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 567 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 568 | { |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 569 | const struct microcode *microcode_file; |
| 570 | size_t microcode_len; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 571 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 572 | /* Locate microcode and pass to FSP-S for 2nd microcode loading */ |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 573 | microcode_file = intel_microcode_find(); |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 574 | |
Selma Bensaid | 291294d | 2021-10-11 16:37:36 -0700 | [diff] [blame] | 575 | if (microcode_file != NULL) { |
| 576 | microcode_len = get_microcode_size(microcode_file); |
| 577 | if (microcode_len != 0) { |
| 578 | /* Update CPU Microcode patch base address/size */ |
| 579 | s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; |
| 580 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
| 581 | } |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 582 | } |
Subrata Banik | fad1cb0 | 2022-08-12 18:12:46 +0530 | [diff] [blame] | 583 | } |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 584 | |
Subrata Banik | fad1cb0 | 2022-08-12 18:12:46 +0530 | [diff] [blame] | 585 | static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, |
| 586 | const struct soc_intel_alderlake_config *config) |
| 587 | { |
Subrata Banik | 8409f15 | 2022-08-15 17:08:13 +0530 | [diff] [blame] | 588 | /* |
| 589 | * FIXME: FSP assumes ownership of the APs (Application Processors) |
| 590 | * upon passing `NULL` pointer to the CpuMpPpi FSP-S UPD. |
| 591 | * Hence, pass a valid pointer to the CpuMpPpi UPD unconditionally. |
| 592 | * This would avoid APs from getting hijacked by FSP while coreboot |
| 593 | * decides to set SkipMpInit UPD. |
| 594 | */ |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 595 | s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); |
Subrata Banik | 8409f15 | 2022-08-15 17:08:13 +0530 | [diff] [blame] | 596 | |
| 597 | if (CONFIG(USE_FSP_MP_INIT)) |
Subrata Banik | ceaf9d1 | 2022-06-05 19:33:33 +0530 | [diff] [blame] | 598 | /* |
Subrata Banik | fad1cb0 | 2022-08-12 18:12:46 +0530 | [diff] [blame] | 599 | * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature |
| 600 | * programming. |
| 601 | */ |
| 602 | fill_fsps_microcode_params(s_cfg, config); |
Subrata Banik | 8409f15 | 2022-08-15 17:08:13 +0530 | [diff] [blame] | 603 | else |
Subrata Banik | ceaf9d1 | 2022-06-05 19:33:33 +0530 | [diff] [blame] | 604 | s_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 605 | } |
| 606 | |
| 607 | static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, |
| 608 | const struct soc_intel_alderlake_config *config) |
| 609 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 610 | /* Load VBT before devicetree-specific config. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 611 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 612 | |
| 613 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 614 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
| 615 | s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); |
Lean Sheng Tan | e8df93a | 2022-04-01 19:07:53 +0200 | [diff] [blame] | 616 | s_cfg->PavpEnable = CONFIG(PAVP); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 617 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 618 | |
Michał Kopeć | 75a49fe | 2022-04-08 11:28:45 +0200 | [diff] [blame] | 619 | WEAK_DEV_PTR(tcss_usb3_port1); |
| 620 | WEAK_DEV_PTR(tcss_usb3_port2); |
| 621 | WEAK_DEV_PTR(tcss_usb3_port3); |
| 622 | WEAK_DEV_PTR(tcss_usb3_port4); |
| 623 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 624 | static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, |
| 625 | const struct soc_intel_alderlake_config *config) |
| 626 | { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 627 | const struct device *tcss_port_arr[] = { |
| 628 | DEV_PTR(tcss_usb3_port1), |
| 629 | DEV_PTR(tcss_usb3_port2), |
| 630 | DEV_PTR(tcss_usb3_port3), |
| 631 | DEV_PTR(tcss_usb3_port4), |
| 632 | }; |
| 633 | |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 634 | s_cfg->TcssAuxOri = config->tcss_aux_ori; |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 635 | |
| 636 | /* Explicitly clear this field to avoid using defaults */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 637 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 638 | |
| 639 | /* |
| 640 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 641 | * evaluate this UPD value and skip sending command. There will be no |
| 642 | * delay for command completion. |
| 643 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 644 | s_cfg->ITbtConnectTopologyTimeoutInMs = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 645 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 646 | /* D3Hot and D3Cold for TCSS */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 647 | s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; |
Lean Sheng Tan | cf46099 | 2022-09-07 16:37:21 +0200 | [diff] [blame] | 648 | s_cfg->D3ColdEnable = !CONFIG(SOC_INTEL_ALDERLAKE_S3) && !config->tcss_d3_cold_disable; |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 649 | |
| 650 | s_cfg->UsbTcPortEn = 0; |
| 651 | for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 652 | if (is_dev_enabled(tcss_port_arr[i])) |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 653 | s_cfg->UsbTcPortEn |= BIT(i); |
| 654 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 655 | } |
| 656 | |
| 657 | static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |
| 658 | const struct soc_intel_alderlake_config *config) |
| 659 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 660 | /* Chipset Lockdown */ |
Felix Singer | f9d7dc7 | 2021-05-03 02:33:15 +0200 | [diff] [blame] | 661 | const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |
| 662 | s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp; |
| 663 | s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; |
Subrata Banik | 393b093 | 2022-01-11 11:59:39 +0530 | [diff] [blame] | 664 | s_cfg->PchUnlockGpioPads = lockdown_by_fsp; |
Felix Singer | f9d7dc7 | 2021-05-03 02:33:15 +0200 | [diff] [blame] | 665 | s_cfg->RtcMemoryLock = lockdown_by_fsp; |
Tim Wawrzynczak | 091dfa1 | 2021-08-24 09:32:09 -0600 | [diff] [blame] | 666 | s_cfg->SkipPamLock = !lockdown_by_fsp; |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 667 | |
| 668 | /* coreboot will send EOP before loading payload */ |
| 669 | s_cfg->EndOfPostMessage = EOP_DISABLE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 670 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 671 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 672 | static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, |
| 673 | const struct soc_intel_alderlake_config *config) |
| 674 | { |
| 675 | int i; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 676 | /* USB */ |
| 677 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 678 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 679 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 680 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 681 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 682 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 683 | |
| 684 | if (config->usb2_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 685 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 686 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 687 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
Anil Kumar | c6b65c1 | 2022-02-01 12:59:03 -0800 | [diff] [blame] | 688 | |
| 689 | if (config->usb2_ports[i].type_c) |
| 690 | s_cfg->PortResetMessageEnable[i] = 1; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 691 | } |
| 692 | |
| 693 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 694 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 695 | if (config->usb3_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 696 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 697 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 698 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 699 | |
| 700 | if (config->usb3_ports[i].tx_de_emp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 701 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 702 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 703 | } |
| 704 | if (config->usb3_ports[i].tx_downscale_amp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 705 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 706 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 707 | config->usb3_ports[i].tx_downscale_amp; |
| 708 | } |
| 709 | } |
| 710 | |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 711 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 712 | if (config->tcss_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 713 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 714 | } |
Sridhar Siricilla | 37c3305 | 2022-04-02 10:33:00 +0530 | [diff] [blame] | 715 | |
| 716 | s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 717 | } |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 718 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 719 | static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, |
| 720 | const struct soc_intel_alderlake_config *config) |
| 721 | { |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 722 | s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 723 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 724 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 725 | static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |
| 726 | const struct soc_intel_alderlake_config *config) |
| 727 | { |
Subrata Banik | 88381c9 | 2022-03-29 11:26:11 +0530 | [diff] [blame] | 728 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && |
| 729 | CONFIG(FSP_ENABLE_SERIAL_DEBUG)) |
| 730 | s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) |
| 731 | fsp_debug_event_handler); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 732 | /* PCH UART selection for FSP Debug */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 733 | s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 734 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 735 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 736 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 737 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 738 | static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, |
| 739 | const struct soc_intel_alderlake_config *config) |
| 740 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 741 | /* SATA */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 742 | s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
| 743 | if (s_cfg->SataEnable) { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 744 | s_cfg->SataMode = config->sata_mode; |
| 745 | s_cfg->SataSalpSupport = config->sata_salp_support; |
| 746 | memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable, |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 747 | sizeof(s_cfg->SataPortsEnable)); |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 748 | memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp, |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 749 | sizeof(s_cfg->SataPortsDevSlp)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 750 | } |
| 751 | |
| 752 | /* |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 753 | * Power Optimizer for SATA. |
| 754 | * SataPwrOptimizeDisable is default to 0. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 755 | * Boards not needing the optimizers explicitly disables them by setting |
| 756 | * these disable variables to 1 in devicetree overrides. |
| 757 | */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 758 | s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable); |
Lean Sheng Tan | 1ec8f97 | 2022-09-07 16:07:33 +0200 | [diff] [blame] | 759 | /* Test mode for SATA margining */ |
| 760 | s_cfg->SataTestMode = CONFIG(ENABLE_SATA_TEST_MODE); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 761 | /* |
| 762 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 763 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 764 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 765 | * The default values can be changed from devicetree. |
| 766 | */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 767 | for (size_t i = 0; i < ARRAY_SIZE(config->sata_ports_enable_dito_config); i++) { |
| 768 | if (config->sata_ports_enable_dito_config[i]) { |
| 769 | s_cfg->SataPortsDmVal[i] = config->sata_ports_dm_val[i]; |
| 770 | s_cfg->SataPortsDitoVal[i] = config->sata_ports_dito_val[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 771 | } |
| 772 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 773 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 774 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 775 | static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, |
| 776 | const struct soc_intel_alderlake_config *config) |
| 777 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 778 | /* Enable TCPU for processor thermal control */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 779 | s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 780 | |
| 781 | /* Set TccActivationOffset */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 782 | s_cfg->TccActivationOffset = config->tcc_offset; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 783 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 784 | |
Jeremy Soller | 9601b1e | 2022-05-26 10:21:36 -0600 | [diff] [blame] | 785 | static void fill_fsps_gna_params(FSP_S_CONFIG *s_cfg, |
| 786 | const struct soc_intel_alderlake_config *config) |
| 787 | { |
| 788 | s_cfg->GnaEnable = is_devfn_enabled(SA_DEVFN_GNA); |
| 789 | } |
| 790 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 791 | static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, |
| 792 | const struct soc_intel_alderlake_config *config) |
| 793 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 794 | /* LAN */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 795 | s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 796 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 797 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 798 | static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, |
| 799 | const struct soc_intel_alderlake_config *config) |
| 800 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 801 | /* CNVi */ |
Michał Żygowski | 9707464 | 2022-06-30 18:19:27 +0200 | [diff] [blame] | 802 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) |
| 803 | #if !CONFIG(SOC_INTEL_RAPTORLAKE) |
| 804 | /* This option is only available in public FSP headers of ADL-P and ADL-S */ |
| 805 | s_cfg->CnviWifiCore = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
| 806 | #endif |
| 807 | #endif |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 808 | s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 809 | s_cfg->CnviBtCore = config->cnvi_bt_core; |
| 810 | s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 811 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 812 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 813 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 814 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 815 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 816 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 817 | static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, |
| 818 | const struct soc_intel_alderlake_config *config) |
| 819 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 820 | /* VMD */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 821 | s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 822 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 823 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 824 | static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, |
| 825 | const struct soc_intel_alderlake_config *config) |
| 826 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 827 | /* THC */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 828 | s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; |
| 829 | s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 830 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 831 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 832 | static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, |
| 833 | const struct soc_intel_alderlake_config *config) |
| 834 | { |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 835 | /* USB4/TBT */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 836 | for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 837 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i)); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 838 | } |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 839 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 840 | static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, |
| 841 | const struct soc_intel_alderlake_config *config) |
| 842 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 843 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 844 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 845 | s_cfg->Enable8254ClockGating = !use_8254; |
| 846 | s_cfg->Enable8254ClockGatingOnS3 = !use_8254; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 847 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 848 | |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 849 | static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, |
| 850 | const struct soc_intel_alderlake_config *config) |
| 851 | { |
| 852 | /* |
| 853 | * Legacy PM ACPI Timer (and TCO Timer) |
| 854 | * This *must* be 1 in any case to keep FSP from |
| 855 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 856 | * 2) disabling the PM ACPI Timer. |
| 857 | * We handle both by ourself! |
| 858 | */ |
| 859 | s_cfg->EnableTcoTimer = 1; |
| 860 | } |
| 861 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 862 | static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, |
| 863 | const struct soc_intel_alderlake_config *config) |
| 864 | { |
Krishna Prasad Bhat | a6d642f | 2022-01-16 23:16:24 +0530 | [diff] [blame] | 865 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 866 | /* eMMC Configuration */ |
| 867 | s_cfg->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); |
| 868 | if (s_cfg->ScsEmmcEnabled) |
| 869 | s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode; |
| 870 | #endif |
Meera Ravindranath | d8ea360 | 2022-03-16 15:27:00 +0530 | [diff] [blame] | 871 | |
| 872 | /* UFS Configuration */ |
| 873 | s_cfg->UfsEnable[0] = 0; /* UFS Controller 0 is fuse disabled */ |
| 874 | s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS); |
| 875 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 876 | /* Enable Hybrid storage auto detection */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 877 | s_cfg->HybridStorageMode = config->hybrid_storage_mode; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 878 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 879 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 880 | static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, |
| 881 | const struct soc_intel_alderlake_config *config) |
| 882 | { |
| 883 | uint32_t enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
| 884 | for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 885 | if (!(enable_mask & BIT(i))) |
| 886 | continue; |
| 887 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 888 | s_cfg->PcieRpL1Substates[i] = |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 889 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 890 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 891 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 892 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) |
| 893 | || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 894 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 895 | if (rp_cfg->pcie_rp_aspm) |
| 896 | s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); |
Cliff Huang | 61a442ec | 2022-04-28 18:06:54 -0700 | [diff] [blame] | 897 | /* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */ |
| 898 | if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN)) |
| 899 | s_cfg->PcieRpSlotImplemented[i] = 0; |
| 900 | s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 901 | } |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 902 | s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 903 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 904 | |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 905 | static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg, |
| 906 | const struct soc_intel_alderlake_config *config) |
| 907 | { |
| 908 | if (!CONFIG_MAX_CPU_ROOT_PORTS) |
| 909 | return; |
| 910 | |
| 911 | const uint32_t enable_mask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); |
| 912 | for (int i = 0; i < CONFIG_MAX_CPU_ROOT_PORTS; i++) { |
| 913 | if (!(enable_mask & BIT(i))) |
| 914 | continue; |
| 915 | |
| 916 | const struct pcie_rp_config *rp_cfg = &config->cpu_pcie_rp[i]; |
| 917 | s_cfg->CpuPcieRpL1Substates[i] = |
| 918 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
| 919 | s_cfg->CpuPcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 920 | s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 921 | s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) |
| 922 | || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Tim Wawrzynczak | d6b763c | 2022-07-27 09:53:58 -0600 | [diff] [blame] | 923 | s_cfg->CpuPcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 924 | s_cfg->PtmEnabled[i] = 0; |
Tim Wawrzynczak | d6b763c | 2022-07-27 09:53:58 -0600 | [diff] [blame] | 925 | if (rp_cfg->pcie_rp_aspm) |
| 926 | s_cfg->CpuPcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); |
| 927 | |
| 928 | if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN)) |
| 929 | s_cfg->CpuPcieRpSlotImplemented[i] = 0; |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 930 | } |
Sridahr Siricilla | 096ce14 | 2021-09-17 22:25:17 +0530 | [diff] [blame] | 931 | s_cfg->CpuPcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 932 | } |
| 933 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 934 | static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, |
| 935 | const struct soc_intel_alderlake_config *config) |
| 936 | { |
Subrata Banik | d6da4ef | 2021-10-07 00:39:31 +0530 | [diff] [blame] | 937 | /* Skip setting D0I3 bit for all HECI devices */ |
| 938 | s_cfg->DisableD0I3SettingForHeci = 1; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 939 | /* |
| 940 | * Power Optimizer for DMI |
| 941 | * DmiPwrOptimizeDisable is default to 0. |
| 942 | * Boards not needing the optimizers explicitly disables them by setting |
| 943 | * these disable variables to 1 in devicetree overrides. |
| 944 | */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 945 | s_cfg->PchPwrOptEnable = !(config->dmi_power_optimize_disable); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 946 | s_cfg->PmSupport = 1; |
| 947 | s_cfg->Hwp = 1; |
| 948 | s_cfg->Cx = 1; |
| 949 | s_cfg->PsOnEnable = 1; |
V Sowmya | af42906 | 2021-06-21 10:23:33 +0530 | [diff] [blame] | 950 | s_cfg->PkgCStateLimit = LIMIT_AUTO; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 951 | |
Jeremy Compostella | 92d3899 | 2022-09-14 11:06:06 -0700 | [diff] [blame] | 952 | /* Disable Energy Efficient Turbo mode */ |
| 953 | s_cfg->EnergyEfficientTurbo = 0; |
| 954 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 955 | /* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */ |
| 956 | s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax() * 4 / MILLIAMPS_TO_AMPS; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 957 | |
| 958 | /* VrConfig Settings for IA and GT domains */ |
| 959 | for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 960 | fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 961 | |
Nick Vaccaro | 577afe6 | 2022-01-12 12:03:41 -0800 | [diff] [blame] | 962 | s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 963 | |
| 964 | /* Apply minimum assertion width settings */ |
| 965 | if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT) |
| 966 | s_cfg->PchPmSlpS3MinAssert = SLP_S3_ASSERTION_50_MS; |
| 967 | else |
| 968 | s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width; |
| 969 | |
| 970 | if (config->pch_slp_s4_min_assertion_width == SLP_S4_ASSERTION_DEFAULT) |
| 971 | s_cfg->PchPmSlpS4MinAssert = SLP_S4_ASSERTION_1S; |
| 972 | else |
| 973 | s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width; |
| 974 | |
| 975 | if (config->pch_slp_sus_min_assertion_width == SLP_SUS_ASSERTION_DEFAULT) |
| 976 | s_cfg->PchPmSlpSusMinAssert = SLP_SUS_ASSERTION_4_S; |
| 977 | else |
| 978 | s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width; |
| 979 | |
| 980 | if (config->pch_slp_a_min_assertion_width == SLP_A_ASSERTION_DEFAULT) |
| 981 | s_cfg->PchPmSlpAMinAssert = SLP_A_ASSERTION_2_S; |
| 982 | else |
| 983 | s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width; |
| 984 | |
| 985 | unsigned int power_cycle_duration = config->pch_reset_power_cycle_duration; |
| 986 | if (power_cycle_duration == POWER_CYCLE_DURATION_DEFAULT) |
| 987 | power_cycle_duration = POWER_CYCLE_DURATION_4S; |
| 988 | |
| 989 | s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(s_cfg->PchPmSlpS4MinAssert, |
| 990 | s_cfg->PchPmSlpS3MinAssert, |
| 991 | s_cfg->PchPmSlpAMinAssert, |
| 992 | power_cycle_duration); |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 993 | |
| 994 | /* Set PsysPmax if it is available from DT */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 995 | if (config->platform_pmax) { |
| 996 | printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->platform_pmax); |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 997 | /* PsysPmax is in unit of 1/8 Watt */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 998 | s_cfg->PsysPmax = config->platform_pmax * 8; |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 999 | } |
MAULIK V VAGHELA | 9935638 | 2022-03-03 13:07:57 +0530 | [diff] [blame] | 1000 | |
| 1001 | s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion; |
Lean Sheng Tan | 4b45d4c | 2022-04-01 19:01:59 +0200 | [diff] [blame] | 1002 | |
| 1003 | s_cfg->VrPowerDeliveryDesign = config->vr_power_delivery_design; |
V Sowmya | 4be8d9e | 2022-07-05 20:49:57 +0530 | [diff] [blame] | 1004 | |
| 1005 | s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 1006 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1007 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 1008 | static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |
| 1009 | const struct soc_intel_alderlake_config *config) |
| 1010 | { |
Michał Żygowski | 72704be | 2022-06-20 18:10:14 +0200 | [diff] [blame] | 1011 | const struct slot_irq_constraints *constraints; |
| 1012 | size_t num_slots; |
| 1013 | |
| 1014 | if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) { |
| 1015 | constraints = irq_constraints_pch_s; |
| 1016 | num_slots = ARRAY_SIZE(irq_constraints_pch_s); |
| 1017 | } else { |
| 1018 | constraints = irq_constraints; |
| 1019 | num_slots = ARRAY_SIZE(irq_constraints); |
| 1020 | } |
| 1021 | |
| 1022 | if (!assign_pci_irqs(constraints, num_slots)) |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 1023 | die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); |
| 1024 | |
| 1025 | size_t pch_count = 0; |
| 1026 | const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); |
| 1027 | |
| 1028 | s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); |
| 1029 | s_cfg->NumOfDevIntConfig = pch_count; |
| 1030 | printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); |
| 1031 | } |
| 1032 | |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 1033 | static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, |
| 1034 | const struct soc_intel_alderlake_config *config) |
| 1035 | { |
| 1036 | /* PCH FIVR settings override */ |
| 1037 | if (!config->ext_fivr_settings.configure_ext_fivr) |
| 1038 | return; |
| 1039 | |
| 1040 | s_cfg->PchFivrExtV1p05RailEnabledStates = |
| 1041 | config->ext_fivr_settings.v1p05_enable_bitmap; |
| 1042 | |
| 1043 | s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = |
| 1044 | config->ext_fivr_settings.v1p05_supported_voltage_bitmap; |
| 1045 | |
| 1046 | s_cfg->PchFivrExtVnnRailEnabledStates = |
| 1047 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 1048 | |
| 1049 | s_cfg->PchFivrExtVnnRailSupportedVoltageStates = |
| 1050 | config->ext_fivr_settings.vnn_supported_voltage_bitmap; |
| 1051 | |
| 1052 | s_cfg->PchFivrExtVnnRailSxEnabledStates = |
Bora Guvendik | fbf874f | 2021-10-18 14:17:41 -0700 | [diff] [blame] | 1053 | config->ext_fivr_settings.vnn_sx_enable_bitmap; |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 1054 | |
| 1055 | /* Convert the voltages to increments of 2.5mv */ |
| 1056 | s_cfg->PchFivrExtV1p05RailVoltage = |
| 1057 | (config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25; |
| 1058 | |
| 1059 | s_cfg->PchFivrExtVnnRailVoltage = |
| 1060 | (config->ext_fivr_settings.vnn_voltage_mv * 10) / 25; |
| 1061 | |
| 1062 | s_cfg->PchFivrExtVnnRailSxVoltage = |
| 1063 | (config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25); |
| 1064 | |
| 1065 | s_cfg->PchFivrExtV1p05RailIccMaximum = |
| 1066 | config->ext_fivr_settings.v1p05_icc_max_ma; |
| 1067 | |
| 1068 | s_cfg->PchFivrExtVnnRailIccMaximum = |
| 1069 | config->ext_fivr_settings.vnn_icc_max_ma; |
V Sowmya | 036b16b | 2022-10-10 12:46:18 +0530 | [diff] [blame] | 1070 | |
| 1071 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 1072 | /* Enable the FIVR VCCST ICCMax Control for ADL-N. |
| 1073 | * TODO:Right now the UPD is update in partial headers for only ADL-N and when its |
| 1074 | * updated for ADL-P then we will remove the config since this needs to be enabled for |
| 1075 | * all the Alderlake platforms. |
| 1076 | */ |
| 1077 | s_cfg->PchFivrVccstIccMaxControl = 1; |
| 1078 | #endif |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 1079 | } |
| 1080 | |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 1081 | static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg, |
| 1082 | const struct soc_intel_alderlake_config *config) |
| 1083 | { |
| 1084 | /* transform from Hz to 100 KHz */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 1085 | s_cfg->FivrRfiFrequency = config->fivr_rfi_frequency / (100 * KHz); |
| 1086 | s_cfg->FivrSpreadSpectrum = config->fivr_spread_spectrum; |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 1087 | } |
| 1088 | |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1089 | static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg, |
| 1090 | const struct soc_intel_alderlake_config *config) |
| 1091 | { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 1092 | s_cfg->AcousticNoiseMitigation = config->acoustic_noise_mitigation; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1093 | |
| 1094 | if (s_cfg->AcousticNoiseMitigation) { |
leo.chou | aef916a | 2022-05-13 10:41:03 +0800 | [diff] [blame] | 1095 | s_cfg->PreWake = config->PreWake; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1096 | for (int i = 0; i < NUM_VR_DOMAINS; i++) { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 1097 | s_cfg->FastPkgCRampDisable[i] = config->fast_pkg_c_ramp_disable[i]; |
| 1098 | s_cfg->SlowSlewRate[i] = config->slow_slew_rate[i]; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1099 | } |
| 1100 | } |
| 1101 | } |
| 1102 | |
Michał Żygowski | 46d7477 | 2022-04-25 12:15:55 +0200 | [diff] [blame] | 1103 | static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg, |
| 1104 | const struct soc_intel_alderlake_config *config) |
| 1105 | { |
| 1106 | struct device *dev; |
| 1107 | int i; |
| 1108 | /* |
| 1109 | * Prevent FSP from programming write-once subsystem IDs by providing |
| 1110 | * a custom SSID table. Must have at least one entry for the FSP to |
| 1111 | * use the table. |
| 1112 | */ |
| 1113 | struct svid_ssid_init_entry { |
| 1114 | union { |
| 1115 | struct { |
| 1116 | uint64_t reg:12; /* Register offset */ |
| 1117 | uint64_t function:3; |
| 1118 | uint64_t device:5; |
| 1119 | uint64_t bus:8; |
| 1120 | uint64_t :4; |
| 1121 | uint64_t segment:16; |
| 1122 | uint64_t :16; |
| 1123 | }; |
| 1124 | uint64_t segbusdevfuncregister; |
| 1125 | }; |
| 1126 | struct { |
| 1127 | uint16_t svid; |
| 1128 | uint16_t ssid; |
| 1129 | }; |
| 1130 | uint32_t reserved; |
| 1131 | }; |
| 1132 | |
| 1133 | /* |
| 1134 | * The xHCI and HDA devices have RW/L rather than RW/O registers for |
| 1135 | * subsystem IDs and so must be written before FspSiliconInit locks |
| 1136 | * them with their default values. |
| 1137 | */ |
| 1138 | const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA }; |
| 1139 | static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)]; |
| 1140 | |
| 1141 | for (i = 0; i < ARRAY_SIZE(devfn_table); i++) { |
| 1142 | ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID; |
| 1143 | ssid_table[i].device = PCI_SLOT(devfn_table[i]); |
| 1144 | ssid_table[i].function = PCI_FUNC(devfn_table[i]); |
| 1145 | dev = pcidev_path_on_root(devfn_table[i]); |
| 1146 | if (dev) { |
| 1147 | ssid_table[i].svid = dev->subsystem_vendor; |
| 1148 | ssid_table[i].ssid = dev->subsystem_device; |
| 1149 | } |
| 1150 | } |
| 1151 | |
| 1152 | s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table; |
| 1153 | s_cfg->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table); |
| 1154 | |
| 1155 | /* |
| 1156 | * Replace the default SVID:SSID value with the values specified in |
| 1157 | * the devicetree for the root device. |
| 1158 | */ |
| 1159 | dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 1160 | s_cfg->SiCustomizedSvid = dev->subsystem_vendor; |
| 1161 | s_cfg->SiCustomizedSsid = dev->subsystem_device; |
| 1162 | |
| 1163 | /* Ensure FSP will program the registers */ |
| 1164 | s_cfg->SiSkipSsidProgramming = 0; |
| 1165 | } |
| 1166 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1167 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
| 1168 | struct soc_intel_alderlake_config *config) |
| 1169 | { |
| 1170 | /* Override settings per board if required. */ |
| 1171 | mainboard_update_soc_chip_config(config); |
| 1172 | |
Arthur Heymans | 02967e6 | 2022-02-18 13:22:25 +0100 | [diff] [blame] | 1173 | void (*const fill_fsps_params[])(FSP_S_CONFIG *s_cfg, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1174 | const struct soc_intel_alderlake_config *config) = { |
| 1175 | fill_fsps_lpss_params, |
| 1176 | fill_fsps_cpu_params, |
| 1177 | fill_fsps_igd_params, |
| 1178 | fill_fsps_tcss_params, |
| 1179 | fill_fsps_chipset_lockdown_params, |
| 1180 | fill_fsps_xhci_params, |
| 1181 | fill_fsps_xdci_params, |
| 1182 | fill_fsps_uart_params, |
| 1183 | fill_fsps_sata_params, |
| 1184 | fill_fsps_thermal_params, |
Jeremy Soller | 9601b1e | 2022-05-26 10:21:36 -0600 | [diff] [blame] | 1185 | fill_fsps_gna_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1186 | fill_fsps_lan_params, |
| 1187 | fill_fsps_cnvi_params, |
| 1188 | fill_fsps_vmd_params, |
| 1189 | fill_fsps_thc_params, |
| 1190 | fill_fsps_tbt_params, |
| 1191 | fill_fsps_8254_params, |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 1192 | fill_fsps_pm_timer_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1193 | fill_fsps_storage_params, |
| 1194 | fill_fsps_pcie_params, |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 1195 | fill_fsps_cpu_pcie_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1196 | fill_fsps_misc_power_params, |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 1197 | fill_fsps_irq_params, |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 1198 | fill_fsps_fivr_params, |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 1199 | fill_fsps_fivr_rfi_params, |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 1200 | fill_fsps_acoustic_params, |
Michał Żygowski | 46d7477 | 2022-04-25 12:15:55 +0200 | [diff] [blame] | 1201 | fill_fsps_pci_ssid_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 1202 | }; |
| 1203 | |
| 1204 | for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |
| 1205 | fill_fsps_params[i](s_cfg, config); |
| 1206 | } |
| 1207 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 1208 | /* UPD parameters to be initialized before SiliconInit */ |
| 1209 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 1210 | { |
| 1211 | struct soc_intel_alderlake_config *config; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 1212 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 1213 | |
| 1214 | config = config_of_soc(); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 1215 | soc_silicon_init_params(s_cfg, config); |
| 1216 | mainboard_silicon_init_params(s_cfg); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1217 | } |
| 1218 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1219 | /* |
| 1220 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 1221 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 1222 | * Phase | FSP return point | Purpose |
| 1223 | * ------- + ------------------------------------------------ + ------------------------------- |
| 1224 | * 1 | After TCSS initialization completed | for TCSS specific init |
Subrata Banik | b6c3a03 | 2022-06-05 22:39:34 +0530 | [diff] [blame] | 1225 | * 2 | Before BIOS Reset CPL is set by FSP-S | for CPU specific init |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1226 | */ |
| 1227 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 1228 | { |
| 1229 | switch (phase_index) { |
| 1230 | case 1: |
| 1231 | /* TCSS specific initialization here */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 1232 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 1233 | __FILE__, __func__); |
| 1234 | |
| 1235 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 1236 | const config_t *config = config_of_soc(); |
| 1237 | tcss_configure(config->typec_aux_bias_pads); |
| 1238 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1239 | break; |
Subrata Banik | b6c3a03 | 2022-06-05 22:39:34 +0530 | [diff] [blame] | 1240 | case 2: |
| 1241 | /* CPU specific initialization here */ |
| 1242 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 1243 | __FILE__, __func__); |
| 1244 | before_post_cpus_init(); |
| 1245 | /* Enable BIOS Reset CPL */ |
| 1246 | enable_bios_reset_cpl(); |
| 1247 | break; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1248 | default: |
| 1249 | break; |
| 1250 | } |
| 1251 | } |
| 1252 | |
| 1253 | /* Mainboard GPIO Configuration */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 1254 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1255 | { |
| 1256 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 1257 | } |