commit 418d37e68956b13ea4e8abff8bf6ed30c0059bcd
author V Sowmya <v.sowmya@intel.com> Mon Jun 21 08:47:17 2021 +0530
committer Patrick Georgi <pgeorgi@google.com> Mon Jul 05 10:47:17 2021 +0000
tree aea55239fd0c9273a0af0d91a2a34cf074473ebd
parent 912a2353d244eae35ab39c80e8bb6d52ee5d5967

soc/intel/alderlake: Add support to update the FIVR configs

This patch adds the supports to update the optimal FIVR
configurations for external voltage rails via devicetree.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55702
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/fsp_params.c

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index e29133e..5b0d631 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -549,6 +549,45 @@
 	printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
 }
 
+static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
+		const struct soc_intel_alderlake_config *config)
+{
+	/* PCH FIVR settings override */
+	if (!config->ext_fivr_settings.configure_ext_fivr)
+		return;
+
+	s_cfg->PchFivrExtV1p05RailEnabledStates =
+			config->ext_fivr_settings.v1p05_enable_bitmap;
+
+	s_cfg->PchFivrExtV1p05RailSupportedVoltageStates =
+			config->ext_fivr_settings.v1p05_supported_voltage_bitmap;
+
+	s_cfg->PchFivrExtVnnRailEnabledStates =
+			config->ext_fivr_settings.vnn_enable_bitmap;
+
+	s_cfg->PchFivrExtVnnRailSupportedVoltageStates =
+			config->ext_fivr_settings.vnn_supported_voltage_bitmap;
+
+	s_cfg->PchFivrExtVnnRailSxEnabledStates =
+			config->ext_fivr_settings.vnn_enable_bitmap;
+
+	/* Convert the voltages to increments of 2.5mv */
+	s_cfg->PchFivrExtV1p05RailVoltage =
+			(config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25;
+
+	s_cfg->PchFivrExtVnnRailVoltage =
+			(config->ext_fivr_settings.vnn_voltage_mv * 10) / 25;
+
+	s_cfg->PchFivrExtVnnRailSxVoltage =
+			(config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25);
+
+	s_cfg->PchFivrExtV1p05RailIccMaximum =
+			config->ext_fivr_settings.v1p05_icc_max_ma;
+
+	s_cfg->PchFivrExtVnnRailIccMaximum =
+			config->ext_fivr_settings.vnn_icc_max_ma;
+}
+
 static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
 {
 	/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
@@ -583,6 +622,7 @@
 		fill_fsps_pcie_params,
 		fill_fsps_misc_power_params,
 		fill_fsps_irq_params,
+		fill_fsps_fivr_params,
 	};
 
 	for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)