soc/intel/alderlake: Enable Intel FIVR RFI settings
Add RFI UPD settings to mitigate RFI noise issues and exporting
these UPDs to override via board devicetree.
BUG=b:200886627
TEST=build
Change-Id: I37bfef295fcd886d4f01abd40f9467a0791e9e34
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 9ed8acd..17edada 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -731,6 +731,14 @@
config->ext_fivr_settings.vnn_icc_max_ma;
}
+static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,
+ const struct soc_intel_alderlake_config *config)
+{
+ /* transform from Hz to 100 KHz */
+ s_cfg->FivrRfiFrequency = config->FivrRfiFrequency / (100 * KHz);
+ s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum;
+}
+
static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
struct soc_intel_alderlake_config *config)
{
@@ -761,6 +769,7 @@
fill_fsps_misc_power_params,
fill_fsps_irq_params,
fill_fsps_fivr_params,
+ fill_fsps_fivr_rfi_params,
};
for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)