Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 5 | #include <cpu/intel/microcode.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 8 | #include <device/pci_ids.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 9 | #include <fsp/api.h> |
Subrata Banik | 7cb6d72 | 2022-03-23 01:33:27 +0530 | [diff] [blame] | 10 | #include <fsp/fsp_debug_event.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 11 | #include <fsp/ppi/mp_service_ppi.h> |
| 12 | #include <fsp/util.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 13 | #include <option.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 14 | #include <intelblocks/irq.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 15 | #include <intelblocks/lpss.h> |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 16 | #include <intelblocks/pmclib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <intelblocks/xdci.h> |
| 18 | #include <intelpch/lockdown.h> |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 19 | #include <intelblocks/tcss.h> |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 20 | #include <soc/cpu.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 21 | #include <soc/gpio_soc_defs.h> |
| 22 | #include <soc/intel/common/vbt.h> |
| 23 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 24 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 25 | #include <soc/ramstage.h> |
| 26 | #include <soc/soc_chip.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 27 | #include <stdlib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 28 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 29 | #include <types.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 30 | |
| 31 | /* THC assignment definition */ |
| 32 | #define THC_NONE 0 |
| 33 | #define THC_0 1 |
| 34 | #define THC_1 2 |
| 35 | |
| 36 | /* SATA DEVSLP idle timeout default values */ |
| 37 | #define DEF_DMVAL 15 |
| 38 | #define DEF_DITOVAL 625 |
| 39 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 40 | /* VccIn Aux Imon IccMax values in mA */ |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 41 | #define MILLIAMPS_TO_AMPS 1000 |
| 42 | #define ICC_MAX_TDP_45W 34250 |
| 43 | #define ICC_MAX_TDP_15W_28W 32000 |
| 44 | #define ICC_MAX_ID_ADL_M_MA 12000 |
V Sowmya | 2af9602 | 2022-04-05 17:03:04 +0530 | [diff] [blame] | 45 | #define ICC_MAX_ID_ADL_N_MA 27000 |
Michał Żygowski | bda2a15 | 2022-04-25 15:02:10 +0200 | [diff] [blame^] | 46 | #define ICC_MAX_ADL_S 33000 |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 47 | |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 48 | /* |
| 49 | * ME End of Post configuration |
| 50 | * 0 - Disable EOP. |
| 51 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 52 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 53 | */ |
| 54 | enum fsp_end_of_post { |
| 55 | EOP_DISABLE = 0, |
| 56 | EOP_PEI = 1, |
| 57 | EOP_DXE = 2, |
| 58 | }; |
| 59 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 60 | static const struct slot_irq_constraints irq_constraints[] = { |
| 61 | { |
| 62 | .slot = SA_DEV_SLOT_IGD, |
| 63 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 64 | /* INTERRUPT_PIN is RO/0x01 */ |
| 65 | FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 66 | }, |
| 67 | }, |
| 68 | { |
| 69 | .slot = SA_DEV_SLOT_DPTF, |
| 70 | .fns = { |
| 71 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 72 | }, |
| 73 | }, |
| 74 | { |
| 75 | .slot = SA_DEV_SLOT_IPU, |
| 76 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 77 | /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, |
| 78 | but S0ix fails when not set to 16 (b/193434192) */ |
| 79 | FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 80 | }, |
| 81 | }, |
| 82 | { |
| 83 | .slot = SA_DEV_SLOT_CPU_6, |
| 84 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 85 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A), |
| 86 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 87 | }, |
| 88 | }, |
| 89 | { |
| 90 | .slot = SA_DEV_SLOT_TBT, |
| 91 | .fns = { |
| 92 | ANY_PIRQ(SA_DEVFN_TBT0), |
| 93 | ANY_PIRQ(SA_DEVFN_TBT1), |
| 94 | ANY_PIRQ(SA_DEVFN_TBT2), |
| 95 | ANY_PIRQ(SA_DEVFN_TBT3), |
| 96 | }, |
| 97 | }, |
| 98 | { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 99 | .slot = SA_DEV_SLOT_GNA, |
| 100 | .fns = { |
| 101 | /* INTERRUPT_PIN is RO/0x01 */ |
| 102 | FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A), |
| 103 | }, |
| 104 | }, |
| 105 | { |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 106 | .slot = SA_DEV_SLOT_TCSS, |
| 107 | .fns = { |
| 108 | ANY_PIRQ(SA_DEVFN_TCSS_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 109 | ANY_PIRQ(SA_DEVFN_TCSS_XDCI), |
| 110 | }, |
| 111 | }, |
| 112 | { |
| 113 | .slot = PCH_DEV_SLOT_SIO0, |
| 114 | .fns = { |
| 115 | DIRECT_IRQ(PCH_DEVFN_I2C6), |
| 116 | DIRECT_IRQ(PCH_DEVFN_I2C7), |
| 117 | ANY_PIRQ(PCH_DEVFN_THC0), |
| 118 | ANY_PIRQ(PCH_DEVFN_THC1), |
| 119 | }, |
| 120 | }, |
| 121 | { |
| 122 | .slot = PCH_DEV_SLOT_SIO6, |
| 123 | .fns = { |
| 124 | DIRECT_IRQ(PCH_DEVFN_UART3), |
| 125 | DIRECT_IRQ(PCH_DEVFN_UART4), |
| 126 | DIRECT_IRQ(PCH_DEVFN_UART5), |
| 127 | DIRECT_IRQ(PCH_DEVFN_UART6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 128 | }, |
| 129 | }, |
| 130 | { |
| 131 | .slot = PCH_DEV_SLOT_ISH, |
| 132 | .fns = { |
| 133 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 134 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 135 | ANY_PIRQ(PCH_DEVFN_UFS), |
| 136 | }, |
| 137 | }, |
| 138 | { |
| 139 | .slot = PCH_DEV_SLOT_SIO2, |
| 140 | .fns = { |
| 141 | DIRECT_IRQ(PCH_DEVFN_GSPI3), |
| 142 | DIRECT_IRQ(PCH_DEVFN_GSPI4), |
| 143 | DIRECT_IRQ(PCH_DEVFN_GSPI5), |
| 144 | DIRECT_IRQ(PCH_DEVFN_GSPI6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 145 | }, |
| 146 | }, |
| 147 | { |
| 148 | .slot = PCH_DEV_SLOT_XHCI, |
| 149 | .fns = { |
| 150 | ANY_PIRQ(PCH_DEVFN_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 151 | DIRECT_IRQ(PCH_DEVFN_USBOTG), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 152 | ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), |
| 153 | }, |
| 154 | }, |
| 155 | { |
| 156 | .slot = PCH_DEV_SLOT_SIO3, |
| 157 | .fns = { |
| 158 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 159 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 160 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 161 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 162 | }, |
| 163 | }, |
| 164 | { |
| 165 | .slot = PCH_DEV_SLOT_CSE, |
| 166 | .fns = { |
| 167 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 168 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 169 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 170 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 171 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 172 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 173 | }, |
| 174 | }, |
| 175 | { |
| 176 | .slot = PCH_DEV_SLOT_SATA, |
| 177 | .fns = { |
| 178 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 179 | }, |
| 180 | }, |
| 181 | { |
| 182 | .slot = PCH_DEV_SLOT_SIO4, |
| 183 | .fns = { |
| 184 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 185 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 186 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 187 | }, |
| 188 | }, |
Krishna Prasad Bhat | a6d642f | 2022-01-16 23:16:24 +0530 | [diff] [blame] | 189 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 190 | { |
| 191 | .slot = PCH_DEV_SLOT_EMMC, |
| 192 | .fns = { |
| 193 | ANY_PIRQ(PCH_DEVFN_EMMC), |
| 194 | }, |
| 195 | }, |
| 196 | #endif |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 197 | { |
| 198 | .slot = PCH_DEV_SLOT_PCIE, |
| 199 | .fns = { |
| 200 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 201 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 202 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 203 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 204 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 205 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 206 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 207 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 208 | }, |
| 209 | }, |
| 210 | { |
| 211 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 212 | .fns = { |
| 213 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 214 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 215 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 216 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 217 | }, |
| 218 | }, |
| 219 | { |
| 220 | .slot = PCH_DEV_SLOT_SIO5, |
| 221 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 222 | /* UART0 shares an interrupt line with TSN0, so must use |
| 223 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 224 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 225 | /* UART1 shares an interrupt line with TSN1, so must use |
| 226 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 227 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 228 | DIRECT_IRQ(PCH_DEVFN_GSPI0), |
| 229 | DIRECT_IRQ(PCH_DEVFN_GSPI1), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 230 | }, |
| 231 | }, |
| 232 | { |
| 233 | .slot = PCH_DEV_SLOT_ESPI, |
| 234 | .fns = { |
| 235 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 236 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 237 | ANY_PIRQ(PCH_DEVFN_GBE), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 238 | /* INTERRUPT_PIN is RO/0x01 */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 239 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 240 | }, |
| 241 | }, |
| 242 | }; |
| 243 | |
| 244 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) |
| 245 | { |
| 246 | const struct pci_irq_entry *entry = get_cached_pci_irqs(); |
| 247 | SI_PCH_DEVICE_INTERRUPT_CONFIG *config; |
| 248 | size_t pch_total = 0; |
| 249 | size_t cfg_count = 0; |
| 250 | |
| 251 | if (!entry) |
| 252 | return NULL; |
| 253 | |
| 254 | /* Count PCH devices */ |
| 255 | while (entry) { |
| 256 | if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) |
| 257 | ++pch_total; |
| 258 | entry = entry->next; |
| 259 | } |
| 260 | |
| 261 | /* Convert PCH device entries to FSP format */ |
| 262 | config = calloc(pch_total, sizeof(*config)); |
| 263 | entry = get_cached_pci_irqs(); |
| 264 | while (entry) { |
| 265 | if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { |
| 266 | entry = entry->next; |
| 267 | continue; |
| 268 | } |
| 269 | |
| 270 | config[cfg_count].Device = PCI_SLOT(entry->devfn); |
| 271 | config[cfg_count].Function = PCI_FUNC(entry->devfn); |
| 272 | config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; |
| 273 | config[cfg_count].Irq = entry->irq; |
| 274 | ++cfg_count; |
| 275 | |
| 276 | entry = entry->next; |
| 277 | } |
| 278 | |
| 279 | *out_count = cfg_count; |
| 280 | |
| 281 | return config; |
| 282 | } |
| 283 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 284 | /* |
| 285 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 286 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 287 | * In order to ensure that mainboard setting does not disable L1 substates |
| 288 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 289 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 290 | * value is set in fsp_params. |
| 291 | * 0: Use FSP UPD default |
| 292 | * 1: Disable L1 substates |
| 293 | * 2: Use L1.1 |
| 294 | * 3: Use L1.2 (FSP UPD default) |
| 295 | */ |
| 296 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 297 | { |
| 298 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 299 | ctl = L1_SS_L1_2; |
| 300 | return ctl - 1; |
| 301 | } |
| 302 | |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 303 | /* |
| 304 | * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because |
| 305 | * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure |
| 306 | * that the mainboard setting does not disable ASPM incorrectly, chip |
| 307 | * config parameter values are offset by 1 with 0 meaning use FSP UPD default. |
| 308 | * get_aspm_control() ensures that the right UPD value is set in fsp_params. |
| 309 | * 0: Use FSP UPD default |
| 310 | * 1: Disable ASPM |
| 311 | * 2: L0s only |
| 312 | * 3: L1 only |
| 313 | * 4: L0s and L1 |
| 314 | * 5: Auto configuration |
| 315 | */ |
| 316 | static unsigned int get_aspm_control(enum ASPM_control ctl) |
| 317 | { |
| 318 | if ((ctl > ASPM_AUTO) || (ctl == ASPM_DEFAULT)) |
| 319 | ctl = ASPM_AUTO; |
| 320 | return ctl - 1; |
| 321 | } |
| 322 | |
Michał Żygowski | bda2a15 | 2022-04-25 15:02:10 +0200 | [diff] [blame^] | 323 | /* This function returns the VccIn Aux Imon IccMax values for ADL-P and ADL-S SKU's */ |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 324 | static uint16_t get_vccin_aux_imon_iccmax(void) |
| 325 | { |
| 326 | uint16_t mch_id = 0; |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 327 | uint8_t tdp; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 328 | |
| 329 | if (!mch_id) { |
| 330 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 331 | mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 332 | } |
| 333 | |
| 334 | switch (mch_id) { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 335 | case PCI_DID_INTEL_ADL_P_ID_1: |
| 336 | case PCI_DID_INTEL_ADL_P_ID_3: |
Curtis Chen | 3fc3e6c | 2022-03-10 11:51:38 +0800 | [diff] [blame] | 337 | case PCI_DID_INTEL_ADL_P_ID_4: |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 338 | case PCI_DID_INTEL_ADL_P_ID_5: |
| 339 | case PCI_DID_INTEL_ADL_P_ID_6: |
| 340 | case PCI_DID_INTEL_ADL_P_ID_7: |
Curtis Chen | 3fc3e6c | 2022-03-10 11:51:38 +0800 | [diff] [blame] | 341 | case PCI_DID_INTEL_ADL_P_ID_8: |
| 342 | case PCI_DID_INTEL_ADL_P_ID_9: |
| 343 | case PCI_DID_INTEL_ADL_P_ID_10: |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 344 | tdp = get_cpu_tdp(); |
| 345 | if (tdp == TDP_45W) |
| 346 | return ICC_MAX_TDP_45W; |
| 347 | return ICC_MAX_TDP_15W_28W; |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 348 | case PCI_DID_INTEL_ADL_M_ID_1: |
| 349 | case PCI_DID_INTEL_ADL_M_ID_2: |
Bora Guvendik | 3160595 | 2021-09-01 17:32:07 -0700 | [diff] [blame] | 350 | return ICC_MAX_ID_ADL_M_MA; |
V Sowmya | 2af9602 | 2022-04-05 17:03:04 +0530 | [diff] [blame] | 351 | case PCI_DID_INTEL_ADL_N_ID_1: |
| 352 | case PCI_DID_INTEL_ADL_N_ID_2: |
| 353 | case PCI_DID_INTEL_ADL_N_ID_3: |
| 354 | case PCI_DID_INTEL_ADL_N_ID_4: |
| 355 | return ICC_MAX_ID_ADL_N_MA; |
Michał Żygowski | bda2a15 | 2022-04-25 15:02:10 +0200 | [diff] [blame^] | 356 | case PCI_DID_INTEL_ADL_S_ID_1: |
| 357 | case PCI_DID_INTEL_ADL_S_ID_3: |
| 358 | case PCI_DID_INTEL_ADL_S_ID_8: |
| 359 | case PCI_DID_INTEL_ADL_S_ID_10: |
| 360 | return ICC_MAX_ADL_S; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 361 | default: |
| 362 | printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", |
| 363 | mch_id); |
| 364 | return 0; |
| 365 | } |
| 366 | } |
| 367 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 368 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 369 | { |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 370 | /* Override settings per board. */ |
| 371 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 372 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 373 | static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, |
| 374 | const struct soc_intel_alderlake_config *config) |
| 375 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 376 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 377 | s_cfg->SerialIoI2cMode[i] = config->serial_io_i2c_mode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 378 | |
| 379 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 380 | s_cfg->SerialIoSpiMode[i] = config->serial_io_gspi_mode[i]; |
| 381 | s_cfg->SerialIoSpiCsMode[i] = config->serial_io_gspi_cs_mode[i]; |
| 382 | s_cfg->SerialIoSpiCsState[i] = config->serial_io_gspi_cs_state[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 383 | } |
| 384 | |
| 385 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 386 | s_cfg->SerialIoUartMode[i] = config->serial_io_uart_mode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 387 | } |
| 388 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 389 | static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, |
| 390 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 391 | { |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 392 | const struct microcode *microcode_file; |
| 393 | size_t microcode_len; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 394 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 395 | /* Locate microcode and pass to FSP-S for 2nd microcode loading */ |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 396 | microcode_file = intel_microcode_find(); |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 397 | |
Selma Bensaid | 291294d | 2021-10-11 16:37:36 -0700 | [diff] [blame] | 398 | if (microcode_file != NULL) { |
| 399 | microcode_len = get_microcode_size(microcode_file); |
| 400 | if (microcode_len != 0) { |
| 401 | /* Update CPU Microcode patch base address/size */ |
| 402 | s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; |
| 403 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
| 404 | } |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 405 | } |
| 406 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 407 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 408 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 409 | s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 410 | } |
| 411 | |
| 412 | static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, |
| 413 | const struct soc_intel_alderlake_config *config) |
| 414 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 415 | /* Load VBT before devicetree-specific config. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 416 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 417 | |
| 418 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 419 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
| 420 | s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); |
Lean Sheng Tan | e8df93a | 2022-04-01 19:07:53 +0200 | [diff] [blame] | 421 | s_cfg->PavpEnable = CONFIG(PAVP); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 422 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 423 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 424 | static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, |
| 425 | const struct soc_intel_alderlake_config *config) |
| 426 | { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 427 | const struct device *tcss_port_arr[] = { |
| 428 | DEV_PTR(tcss_usb3_port1), |
| 429 | DEV_PTR(tcss_usb3_port2), |
| 430 | DEV_PTR(tcss_usb3_port3), |
| 431 | DEV_PTR(tcss_usb3_port4), |
| 432 | }; |
| 433 | |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 434 | s_cfg->TcssAuxOri = config->tcss_aux_ori; |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 435 | |
| 436 | /* Explicitly clear this field to avoid using defaults */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 437 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 438 | |
| 439 | /* |
| 440 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 441 | * evaluate this UPD value and skip sending command. There will be no |
| 442 | * delay for command completion. |
| 443 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 444 | s_cfg->ITbtConnectTopologyTimeoutInMs = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 445 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 446 | /* D3Hot and D3Cold for TCSS */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 447 | s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; |
| 448 | s_cfg->D3ColdEnable = !config->tcss_d3_cold_disable; |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 449 | |
| 450 | s_cfg->UsbTcPortEn = 0; |
| 451 | for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 452 | if (is_dev_enabled(tcss_port_arr[i])) |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 453 | s_cfg->UsbTcPortEn |= BIT(i); |
| 454 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 455 | } |
| 456 | |
| 457 | static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |
| 458 | const struct soc_intel_alderlake_config *config) |
| 459 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 460 | /* Chipset Lockdown */ |
Felix Singer | f9d7dc7 | 2021-05-03 02:33:15 +0200 | [diff] [blame] | 461 | const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |
| 462 | s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp; |
| 463 | s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; |
Subrata Banik | 393b093 | 2022-01-11 11:59:39 +0530 | [diff] [blame] | 464 | s_cfg->PchUnlockGpioPads = lockdown_by_fsp; |
Felix Singer | f9d7dc7 | 2021-05-03 02:33:15 +0200 | [diff] [blame] | 465 | s_cfg->RtcMemoryLock = lockdown_by_fsp; |
Tim Wawrzynczak | 091dfa1 | 2021-08-24 09:32:09 -0600 | [diff] [blame] | 466 | s_cfg->SkipPamLock = !lockdown_by_fsp; |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 467 | |
| 468 | /* coreboot will send EOP before loading payload */ |
| 469 | s_cfg->EndOfPostMessage = EOP_DISABLE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 470 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 471 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 472 | static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, |
| 473 | const struct soc_intel_alderlake_config *config) |
| 474 | { |
| 475 | int i; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 476 | /* USB */ |
| 477 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 478 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 479 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 480 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 481 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 482 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 483 | |
| 484 | if (config->usb2_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 485 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 486 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 487 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
Anil Kumar | c6b65c1 | 2022-02-01 12:59:03 -0800 | [diff] [blame] | 488 | |
| 489 | if (config->usb2_ports[i].type_c) |
| 490 | s_cfg->PortResetMessageEnable[i] = 1; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 491 | } |
| 492 | |
| 493 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 494 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 495 | if (config->usb3_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 496 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 497 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 498 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 499 | |
| 500 | if (config->usb3_ports[i].tx_de_emp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 501 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 502 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 503 | } |
| 504 | if (config->usb3_ports[i].tx_downscale_amp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 505 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 506 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 507 | config->usb3_ports[i].tx_downscale_amp; |
| 508 | } |
| 509 | } |
| 510 | |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 511 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 512 | if (config->tcss_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 513 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 514 | } |
Sridhar Siricilla | 37c3305 | 2022-04-02 10:33:00 +0530 | [diff] [blame] | 515 | |
| 516 | s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 517 | } |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 518 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 519 | static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, |
| 520 | const struct soc_intel_alderlake_config *config) |
| 521 | { |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 522 | s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 523 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 524 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 525 | static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |
| 526 | const struct soc_intel_alderlake_config *config) |
| 527 | { |
Subrata Banik | 88381c9 | 2022-03-29 11:26:11 +0530 | [diff] [blame] | 528 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && |
| 529 | CONFIG(FSP_ENABLE_SERIAL_DEBUG)) |
| 530 | s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) |
| 531 | fsp_debug_event_handler); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 532 | /* PCH UART selection for FSP Debug */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 533 | s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 534 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 535 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 536 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 537 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 538 | static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, |
| 539 | const struct soc_intel_alderlake_config *config) |
| 540 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 541 | /* SATA */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 542 | s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
| 543 | if (s_cfg->SataEnable) { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 544 | s_cfg->SataMode = config->sata_mode; |
| 545 | s_cfg->SataSalpSupport = config->sata_salp_support; |
| 546 | memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable, |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 547 | sizeof(s_cfg->SataPortsEnable)); |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 548 | memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp, |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 549 | sizeof(s_cfg->SataPortsDevSlp)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 550 | } |
| 551 | |
| 552 | /* |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 553 | * Power Optimizer for SATA. |
| 554 | * SataPwrOptimizeDisable is default to 0. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 555 | * Boards not needing the optimizers explicitly disables them by setting |
| 556 | * these disable variables to 1 in devicetree overrides. |
| 557 | */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 558 | s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 559 | /* |
| 560 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 561 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 562 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 563 | * The default values can be changed from devicetree. |
| 564 | */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 565 | for (size_t i = 0; i < ARRAY_SIZE(config->sata_ports_enable_dito_config); i++) { |
| 566 | if (config->sata_ports_enable_dito_config[i]) { |
| 567 | s_cfg->SataPortsDmVal[i] = config->sata_ports_dm_val[i]; |
| 568 | s_cfg->SataPortsDitoVal[i] = config->sata_ports_dito_val[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 569 | } |
| 570 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 571 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 572 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 573 | static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, |
| 574 | const struct soc_intel_alderlake_config *config) |
| 575 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 576 | /* Enable TCPU for processor thermal control */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 577 | s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 578 | |
| 579 | /* Set TccActivationOffset */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 580 | s_cfg->TccActivationOffset = config->tcc_offset; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 581 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 582 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 583 | static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, |
| 584 | const struct soc_intel_alderlake_config *config) |
| 585 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 586 | /* LAN */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 587 | s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 588 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 589 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 590 | static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, |
| 591 | const struct soc_intel_alderlake_config *config) |
| 592 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 593 | /* CNVi */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 594 | s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 595 | s_cfg->CnviBtCore = config->cnvi_bt_core; |
| 596 | s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 597 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 598 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 599 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 600 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 601 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 602 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 603 | static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, |
| 604 | const struct soc_intel_alderlake_config *config) |
| 605 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 606 | /* VMD */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 607 | s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 608 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 609 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 610 | static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, |
| 611 | const struct soc_intel_alderlake_config *config) |
| 612 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 613 | /* THC */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 614 | s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; |
| 615 | s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 616 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 617 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 618 | static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, |
| 619 | const struct soc_intel_alderlake_config *config) |
| 620 | { |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 621 | /* USB4/TBT */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 622 | for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 623 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i)); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 624 | } |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 625 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 626 | static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, |
| 627 | const struct soc_intel_alderlake_config *config) |
| 628 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 629 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 630 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 631 | s_cfg->Enable8254ClockGating = !use_8254; |
| 632 | s_cfg->Enable8254ClockGatingOnS3 = !use_8254; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 633 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 634 | |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 635 | static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, |
| 636 | const struct soc_intel_alderlake_config *config) |
| 637 | { |
| 638 | /* |
| 639 | * Legacy PM ACPI Timer (and TCO Timer) |
| 640 | * This *must* be 1 in any case to keep FSP from |
| 641 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 642 | * 2) disabling the PM ACPI Timer. |
| 643 | * We handle both by ourself! |
| 644 | */ |
| 645 | s_cfg->EnableTcoTimer = 1; |
| 646 | } |
| 647 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 648 | static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, |
| 649 | const struct soc_intel_alderlake_config *config) |
| 650 | { |
Krishna Prasad Bhat | a6d642f | 2022-01-16 23:16:24 +0530 | [diff] [blame] | 651 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 652 | /* eMMC Configuration */ |
| 653 | s_cfg->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); |
| 654 | if (s_cfg->ScsEmmcEnabled) |
| 655 | s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode; |
| 656 | #endif |
Meera Ravindranath | d8ea360 | 2022-03-16 15:27:00 +0530 | [diff] [blame] | 657 | |
| 658 | /* UFS Configuration */ |
| 659 | s_cfg->UfsEnable[0] = 0; /* UFS Controller 0 is fuse disabled */ |
| 660 | s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS); |
| 661 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 662 | /* Enable Hybrid storage auto detection */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 663 | s_cfg->HybridStorageMode = config->hybrid_storage_mode; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 664 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 665 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 666 | static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, |
| 667 | const struct soc_intel_alderlake_config *config) |
| 668 | { |
| 669 | uint32_t enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
| 670 | for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 671 | if (!(enable_mask & BIT(i))) |
| 672 | continue; |
| 673 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 674 | s_cfg->PcieRpL1Substates[i] = |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 675 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 676 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 677 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
| 678 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); |
| 679 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Kevin Chang | 6e52c1d | 2022-03-18 21:04:07 +0800 | [diff] [blame] | 680 | if (rp_cfg->pcie_rp_aspm) |
| 681 | s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); |
Cliff Huang | 61a442ec | 2022-04-28 18:06:54 -0700 | [diff] [blame] | 682 | /* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */ |
| 683 | if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN)) |
| 684 | s_cfg->PcieRpSlotImplemented[i] = 0; |
| 685 | s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 686 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 687 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 688 | |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 689 | static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg, |
| 690 | const struct soc_intel_alderlake_config *config) |
| 691 | { |
| 692 | if (!CONFIG_MAX_CPU_ROOT_PORTS) |
| 693 | return; |
| 694 | |
| 695 | const uint32_t enable_mask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); |
| 696 | for (int i = 0; i < CONFIG_MAX_CPU_ROOT_PORTS; i++) { |
| 697 | if (!(enable_mask & BIT(i))) |
| 698 | continue; |
| 699 | |
| 700 | const struct pcie_rp_config *rp_cfg = &config->cpu_pcie_rp[i]; |
| 701 | s_cfg->CpuPcieRpL1Substates[i] = |
| 702 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
| 703 | s_cfg->CpuPcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 704 | s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
| 705 | s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); |
| 706 | s_cfg->PtmEnabled[i] = 0; |
| 707 | } |
| 708 | } |
| 709 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 710 | static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, |
| 711 | const struct soc_intel_alderlake_config *config) |
| 712 | { |
Subrata Banik | d6da4ef | 2021-10-07 00:39:31 +0530 | [diff] [blame] | 713 | /* Skip setting D0I3 bit for all HECI devices */ |
| 714 | s_cfg->DisableD0I3SettingForHeci = 1; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 715 | /* |
| 716 | * Power Optimizer for DMI |
| 717 | * DmiPwrOptimizeDisable is default to 0. |
| 718 | * Boards not needing the optimizers explicitly disables them by setting |
| 719 | * these disable variables to 1 in devicetree overrides. |
| 720 | */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 721 | s_cfg->PchPwrOptEnable = !(config->dmi_power_optimize_disable); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 722 | s_cfg->PmSupport = 1; |
| 723 | s_cfg->Hwp = 1; |
| 724 | s_cfg->Cx = 1; |
| 725 | s_cfg->PsOnEnable = 1; |
V Sowmya | 844dcb3 | 2021-06-21 10:03:53 +0530 | [diff] [blame] | 726 | /* Enable the energy efficient turbo mode */ |
| 727 | s_cfg->EnergyEfficientTurbo = 1; |
V Sowmya | af42906 | 2021-06-21 10:23:33 +0530 | [diff] [blame] | 728 | s_cfg->PkgCStateLimit = LIMIT_AUTO; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 729 | |
| 730 | /* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */ |
| 731 | s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax() * 4 / MILLIAMPS_TO_AMPS; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 732 | |
| 733 | /* VrConfig Settings for IA and GT domains */ |
| 734 | for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 735 | fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 736 | |
Nick Vaccaro | 577afe6 | 2022-01-12 12:03:41 -0800 | [diff] [blame] | 737 | s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 738 | |
| 739 | /* Apply minimum assertion width settings */ |
| 740 | if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT) |
| 741 | s_cfg->PchPmSlpS3MinAssert = SLP_S3_ASSERTION_50_MS; |
| 742 | else |
| 743 | s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width; |
| 744 | |
| 745 | if (config->pch_slp_s4_min_assertion_width == SLP_S4_ASSERTION_DEFAULT) |
| 746 | s_cfg->PchPmSlpS4MinAssert = SLP_S4_ASSERTION_1S; |
| 747 | else |
| 748 | s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width; |
| 749 | |
| 750 | if (config->pch_slp_sus_min_assertion_width == SLP_SUS_ASSERTION_DEFAULT) |
| 751 | s_cfg->PchPmSlpSusMinAssert = SLP_SUS_ASSERTION_4_S; |
| 752 | else |
| 753 | s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width; |
| 754 | |
| 755 | if (config->pch_slp_a_min_assertion_width == SLP_A_ASSERTION_DEFAULT) |
| 756 | s_cfg->PchPmSlpAMinAssert = SLP_A_ASSERTION_2_S; |
| 757 | else |
| 758 | s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width; |
| 759 | |
| 760 | unsigned int power_cycle_duration = config->pch_reset_power_cycle_duration; |
| 761 | if (power_cycle_duration == POWER_CYCLE_DURATION_DEFAULT) |
| 762 | power_cycle_duration = POWER_CYCLE_DURATION_4S; |
| 763 | |
| 764 | s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(s_cfg->PchPmSlpS4MinAssert, |
| 765 | s_cfg->PchPmSlpS3MinAssert, |
| 766 | s_cfg->PchPmSlpAMinAssert, |
| 767 | power_cycle_duration); |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 768 | |
| 769 | /* Set PsysPmax if it is available from DT */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 770 | if (config->platform_pmax) { |
| 771 | printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->platform_pmax); |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 772 | /* PsysPmax is in unit of 1/8 Watt */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 773 | s_cfg->PsysPmax = config->platform_pmax * 8; |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 774 | } |
MAULIK V VAGHELA | 9935638 | 2022-03-03 13:07:57 +0530 | [diff] [blame] | 775 | |
| 776 | s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion; |
Lean Sheng Tan | 4b45d4c | 2022-04-01 19:01:59 +0200 | [diff] [blame] | 777 | |
| 778 | s_cfg->VrPowerDeliveryDesign = config->vr_power_delivery_design; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 779 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 780 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 781 | static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |
| 782 | const struct soc_intel_alderlake_config *config) |
| 783 | { |
| 784 | if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) |
| 785 | die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); |
| 786 | |
| 787 | size_t pch_count = 0; |
| 788 | const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); |
| 789 | |
| 790 | s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); |
| 791 | s_cfg->NumOfDevIntConfig = pch_count; |
| 792 | printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); |
| 793 | } |
| 794 | |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 795 | static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, |
| 796 | const struct soc_intel_alderlake_config *config) |
| 797 | { |
| 798 | /* PCH FIVR settings override */ |
| 799 | if (!config->ext_fivr_settings.configure_ext_fivr) |
| 800 | return; |
| 801 | |
| 802 | s_cfg->PchFivrExtV1p05RailEnabledStates = |
| 803 | config->ext_fivr_settings.v1p05_enable_bitmap; |
| 804 | |
| 805 | s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = |
| 806 | config->ext_fivr_settings.v1p05_supported_voltage_bitmap; |
| 807 | |
| 808 | s_cfg->PchFivrExtVnnRailEnabledStates = |
| 809 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 810 | |
| 811 | s_cfg->PchFivrExtVnnRailSupportedVoltageStates = |
| 812 | config->ext_fivr_settings.vnn_supported_voltage_bitmap; |
| 813 | |
| 814 | s_cfg->PchFivrExtVnnRailSxEnabledStates = |
Bora Guvendik | fbf874f | 2021-10-18 14:17:41 -0700 | [diff] [blame] | 815 | config->ext_fivr_settings.vnn_sx_enable_bitmap; |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 816 | |
| 817 | /* Convert the voltages to increments of 2.5mv */ |
| 818 | s_cfg->PchFivrExtV1p05RailVoltage = |
| 819 | (config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25; |
| 820 | |
| 821 | s_cfg->PchFivrExtVnnRailVoltage = |
| 822 | (config->ext_fivr_settings.vnn_voltage_mv * 10) / 25; |
| 823 | |
| 824 | s_cfg->PchFivrExtVnnRailSxVoltage = |
| 825 | (config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25); |
| 826 | |
| 827 | s_cfg->PchFivrExtV1p05RailIccMaximum = |
| 828 | config->ext_fivr_settings.v1p05_icc_max_ma; |
| 829 | |
| 830 | s_cfg->PchFivrExtVnnRailIccMaximum = |
| 831 | config->ext_fivr_settings.vnn_icc_max_ma; |
| 832 | } |
| 833 | |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 834 | static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg, |
| 835 | const struct soc_intel_alderlake_config *config) |
| 836 | { |
| 837 | /* transform from Hz to 100 KHz */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 838 | s_cfg->FivrRfiFrequency = config->fivr_rfi_frequency / (100 * KHz); |
| 839 | s_cfg->FivrSpreadSpectrum = config->fivr_spread_spectrum; |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 840 | } |
| 841 | |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 842 | static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg, |
| 843 | const struct soc_intel_alderlake_config *config) |
| 844 | { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 845 | s_cfg->AcousticNoiseMitigation = config->acoustic_noise_mitigation; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 846 | |
| 847 | if (s_cfg->AcousticNoiseMitigation) { |
leo.chou | aef916a | 2022-05-13 10:41:03 +0800 | [diff] [blame] | 848 | s_cfg->PreWake = config->PreWake; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 849 | for (int i = 0; i < NUM_VR_DOMAINS; i++) { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 850 | s_cfg->FastPkgCRampDisable[i] = config->fast_pkg_c_ramp_disable[i]; |
| 851 | s_cfg->SlowSlewRate[i] = config->slow_slew_rate[i]; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 852 | } |
| 853 | } |
| 854 | } |
| 855 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 856 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
| 857 | struct soc_intel_alderlake_config *config) |
| 858 | { |
| 859 | /* Override settings per board if required. */ |
| 860 | mainboard_update_soc_chip_config(config); |
| 861 | |
Arthur Heymans | 02967e6 | 2022-02-18 13:22:25 +0100 | [diff] [blame] | 862 | void (*const fill_fsps_params[])(FSP_S_CONFIG *s_cfg, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 863 | const struct soc_intel_alderlake_config *config) = { |
| 864 | fill_fsps_lpss_params, |
| 865 | fill_fsps_cpu_params, |
| 866 | fill_fsps_igd_params, |
| 867 | fill_fsps_tcss_params, |
| 868 | fill_fsps_chipset_lockdown_params, |
| 869 | fill_fsps_xhci_params, |
| 870 | fill_fsps_xdci_params, |
| 871 | fill_fsps_uart_params, |
| 872 | fill_fsps_sata_params, |
| 873 | fill_fsps_thermal_params, |
| 874 | fill_fsps_lan_params, |
| 875 | fill_fsps_cnvi_params, |
| 876 | fill_fsps_vmd_params, |
| 877 | fill_fsps_thc_params, |
| 878 | fill_fsps_tbt_params, |
| 879 | fill_fsps_8254_params, |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 880 | fill_fsps_pm_timer_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 881 | fill_fsps_storage_params, |
| 882 | fill_fsps_pcie_params, |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 883 | fill_fsps_cpu_pcie_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 884 | fill_fsps_misc_power_params, |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 885 | fill_fsps_irq_params, |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 886 | fill_fsps_fivr_params, |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 887 | fill_fsps_fivr_rfi_params, |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 888 | fill_fsps_acoustic_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 889 | }; |
| 890 | |
| 891 | for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |
| 892 | fill_fsps_params[i](s_cfg, config); |
| 893 | } |
| 894 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 895 | /* UPD parameters to be initialized before SiliconInit */ |
| 896 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 897 | { |
| 898 | struct soc_intel_alderlake_config *config; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 899 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 900 | |
| 901 | config = config_of_soc(); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 902 | soc_silicon_init_params(s_cfg, config); |
| 903 | mainboard_silicon_init_params(s_cfg); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 904 | } |
| 905 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 906 | /* |
| 907 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 908 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 909 | * Phase | FSP return point | Purpose |
| 910 | * ------- + ------------------------------------------------ + ------------------------------- |
| 911 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 912 | */ |
| 913 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 914 | { |
| 915 | switch (phase_index) { |
| 916 | case 1: |
| 917 | /* TCSS specific initialization here */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 918 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 919 | __FILE__, __func__); |
| 920 | |
| 921 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 922 | const config_t *config = config_of_soc(); |
| 923 | tcss_configure(config->typec_aux_bias_pads); |
| 924 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 925 | break; |
| 926 | default: |
| 927 | break; |
| 928 | } |
| 929 | } |
| 930 | |
| 931 | /* Mainboard GPIO Configuration */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 932 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 933 | { |
| 934 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 935 | } |