soc/intel/alderlake: Add USB TCSS enablement
In order to detect USB Type C device port as Super Speed, we need to set
corresponding bit in UPD UsbTcPortEn. This patch will use device path
to determine which port should be enabled.
BUG=b:184324979
Test=Boot board, USB Type C must be functional and operate at Super Speed.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I7da63f21d51889a888699540f780cb26b480c26d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 783d2a9..e29133e 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -304,6 +304,20 @@
/* D3Hot and D3Cold for TCSS */
s_cfg->D3HotEnable = !config->TcssD3HotDisable;
s_cfg->D3ColdEnable = !config->TcssD3ColdDisable;
+
+ s_cfg->UsbTcPortEn = 0;
+ for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {
+ /* TCSS xHCI --> Root Hub --> Type-C Port */
+ const struct device_path port_path[] = {
+ {.type = DEVICE_PATH_PCI, .pci.devfn = SA_DEVFN_TCSS_XHCI},
+ {.type = DEVICE_PATH_USB, .usb.port_type = 0, .usb.port_id = 0},
+ {.type = DEVICE_PATH_USB, .usb.port_type = 3, .usb.port_id = i} };
+ const struct device *port = find_dev_nested_path(pci_root_bus(), port_path,
+ ARRAY_SIZE(port_path));
+
+ if (is_dev_enabled(port))
+ s_cfg->UsbTcPortEn |= BIT(i);
+ }
}
static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,