soc/intel/alderlake: Send End-of-Post message to CSE
This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command. Verified EOP and error recovery sequence
from Intel doc#627331.
TEST=on brya, autotest firmware_CheckEOPState confirms ME is in
post-boot state
Change-Id: Iee8c29f81d5d04852ae3f16dc8a9ff0fa59f056a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 612bc4e..c814d8c 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -32,6 +32,18 @@
#define DEF_DMVAL 15
#define DEF_DITOVAL 625
+/*
+ * ME End of Post configuration
+ * 0 - Disable EOP.
+ * 1 - Send in PEI (Applicable for FSP in API mode)
+ * 2 - Send in DXE (Not applicable for FSP in API mode)
+ */
+enum fsp_end_of_post {
+ EOP_DISABLE = 0,
+ EOP_PEI = 1,
+ EOP_DXE = 2,
+};
+
static const struct slot_irq_constraints irq_constraints[] = {
{
.slot = SA_DEV_SLOT_IGD,
@@ -309,6 +321,9 @@
s_cfg->PchUnlockGpioPads = 0;
s_cfg->RtcMemoryLock = 1;
}
+
+ /* coreboot will send EOP before loading payload */
+ s_cfg->EndOfPostMessage = EOP_DISABLE;
}
static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
@@ -569,7 +584,6 @@
FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
config = config_of_soc();
-
arch_silicon_init_params(s_arch_cfg);
soc_silicon_init_params(s_cfg, config);
mainboard_silicon_init_params(s_cfg);