Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
| 7 | #include <fsp/api.h> |
| 8 | #include <fsp/ppi/mp_service_ppi.h> |
| 9 | #include <fsp/util.h> |
| 10 | #include <intelblocks/lpss.h> |
| 11 | #include <intelblocks/xdci.h> |
| 12 | #include <intelpch/lockdown.h> |
| 13 | #include <intelblocks/mp_init.h> |
| 14 | #include <soc/gpio_soc_defs.h> |
| 15 | #include <soc/intel/common/vbt.h> |
| 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/ramstage.h> |
| 18 | #include <soc/soc_chip.h> |
| 19 | #include <string.h> |
| 20 | |
| 21 | /* THC assignment definition */ |
| 22 | #define THC_NONE 0 |
| 23 | #define THC_0 1 |
| 24 | #define THC_1 2 |
| 25 | |
| 26 | /* SATA DEVSLP idle timeout default values */ |
| 27 | #define DEF_DMVAL 15 |
| 28 | #define DEF_DITOVAL 625 |
| 29 | |
| 30 | /* |
| 31 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 32 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 33 | * In order to ensure that mainboard setting does not disable L1 substates |
| 34 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 35 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 36 | * value is set in fsp_params. |
| 37 | * 0: Use FSP UPD default |
| 38 | * 1: Disable L1 substates |
| 39 | * 2: Use L1.1 |
| 40 | * 3: Use L1.2 (FSP UPD default) |
| 41 | */ |
| 42 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 43 | { |
| 44 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 45 | ctl = L1_SS_L1_2; |
| 46 | return ctl - 1; |
| 47 | } |
| 48 | |
| 49 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 50 | { |
| 51 | const struct soc_intel_alderlake_config *config; |
| 52 | config = config_of_soc(); |
| 53 | |
| 54 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
| 55 | params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
| 56 | |
| 57 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
| 58 | params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 59 | params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 60 | params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
| 61 | } |
| 62 | |
| 63 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
| 64 | params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
| 65 | } |
| 66 | |
| 67 | static const pci_devfn_t serial_io_dev[] = { |
| 68 | PCH_DEVFN_I2C0, |
| 69 | PCH_DEVFN_I2C1, |
| 70 | PCH_DEVFN_I2C2, |
| 71 | PCH_DEVFN_I2C3, |
| 72 | PCH_DEVFN_I2C4, |
| 73 | PCH_DEVFN_I2C5, |
| 74 | PCH_DEVFN_GSPI0, |
| 75 | PCH_DEVFN_GSPI1, |
| 76 | PCH_DEVFN_GSPI2, |
| 77 | PCH_DEVFN_GSPI3, |
| 78 | PCH_DEVFN_UART0, |
| 79 | PCH_DEVFN_UART1, |
| 80 | PCH_DEVFN_UART2 |
| 81 | }; |
| 82 | |
| 83 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
| 84 | { |
| 85 | /* Override settings per board. */ |
| 86 | } |
| 87 | |
| 88 | /* UPD parameters to be initialized before SiliconInit */ |
| 89 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 90 | { |
| 91 | int i; |
| 92 | FSP_S_CONFIG *params = &supd->FspsConfig; |
| 93 | |
| 94 | struct device *dev; |
| 95 | struct soc_intel_alderlake_config *config; |
| 96 | config = config_of_soc(); |
| 97 | mainboard_update_soc_chip_config(config); |
| 98 | |
| 99 | /* Parse device tree and enable/disable Serial I/O devices */ |
| 100 | parse_devicetree(params); |
| 101 | |
| 102 | /* Load VBT before devicetree-specific config. */ |
| 103 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 104 | |
| 105 | /* Check if IGD is present and fill Graphics init param accordingly */ |
| 106 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
| 107 | params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); |
| 108 | |
| 109 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 110 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 111 | params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 112 | |
| 113 | /* D3Hot and D3Cold for TCSS */ |
| 114 | params->D3HotEnable = !config->TcssD3HotDisable; |
| 115 | params->D3ColdEnable = !config->TcssD3ColdDisable; |
| 116 | |
| 117 | params->TcssAuxOri = config->TcssAuxOri; |
| 118 | for (i = 0; i < 8; i++) |
| 119 | params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; |
| 120 | |
| 121 | /* |
| 122 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 123 | * evaluate this UPD value and skip sending command. There will be no |
| 124 | * delay for command completion. |
| 125 | */ |
| 126 | params->ITbtConnectTopologyTimeoutInMs = 0; |
| 127 | |
| 128 | /* Chipset Lockdown */ |
| 129 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
| 130 | params->PchLockDownGlobalSmi = 0; |
| 131 | params->PchLockDownBiosInterface = 0; |
| 132 | params->PchUnlockGpioPads = 1; |
| 133 | params->RtcMemoryLock = 0; |
| 134 | } else { |
| 135 | params->PchLockDownGlobalSmi = 1; |
| 136 | params->PchLockDownBiosInterface = 1; |
| 137 | params->PchUnlockGpioPads = 0; |
| 138 | params->RtcMemoryLock = 1; |
| 139 | } |
| 140 | |
| 141 | /* USB */ |
| 142 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 143 | params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 144 | params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 145 | params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 146 | params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 147 | params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| 148 | |
| 149 | if (config->usb2_ports[i].enable) |
| 150 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 151 | else |
| 152 | params->Usb2OverCurrentPin[i] = OC_SKIP; |
| 153 | } |
| 154 | |
| 155 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 156 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 157 | if (config->usb3_ports[i].enable) |
| 158 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 159 | else |
| 160 | params->Usb3OverCurrentPin[i] = OC_SKIP; |
| 161 | |
| 162 | if (config->usb3_ports[i].tx_de_emp) { |
| 163 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 164 | params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 165 | } |
| 166 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 167 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 168 | params->Usb3HsioTxDownscaleAmp[i] = |
| 169 | config->usb3_ports[i].tx_downscale_amp; |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
| 174 | dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); |
| 175 | if (dev) { |
| 176 | if (!xdci_can_enable()) |
| 177 | dev->enabled = 0; |
| 178 | params->XdciEnable = dev->enabled; |
| 179 | } else { |
| 180 | params->XdciEnable = 0; |
| 181 | } |
| 182 | |
| 183 | /* PCH UART selection for FSP Debug */ |
| 184 | params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 185 | ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 186 | params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
| 187 | |
| 188 | /* SATA */ |
| 189 | dev = pcidev_path_on_root(PCH_DEVFN_SATA); |
| 190 | params->SataEnable = is_dev_enabled(dev); |
| 191 | if (params->SataEnable) { |
| 192 | params->SataMode = config->SataMode; |
| 193 | params->SataSalpSupport = config->SataSalpSupport; |
| 194 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 195 | sizeof(params->SataPortsEnable)); |
| 196 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 197 | sizeof(params->SataPortsDevSlp)); |
| 198 | } |
| 199 | |
| 200 | /* |
| 201 | * Power Optimizer for DMI and SATA. |
| 202 | * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. |
| 203 | * Boards not needing the optimizers explicitly disables them by setting |
| 204 | * these disable variables to 1 in devicetree overrides. |
| 205 | */ |
| 206 | params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); |
| 207 | params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
| 208 | |
| 209 | /* |
| 210 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 211 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 212 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 213 | * The default values can be changed from devicetree. |
| 214 | */ |
| 215 | for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { |
| 216 | if (config->SataPortsEnableDitoConfig[i]) { |
| 217 | params->SataPortsDmVal[i] = config->SataPortsDmVal[i]; |
| 218 | params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | /* Enable TCPU for processor thermal control */ |
| 223 | dev = pcidev_path_on_root(SA_DEVFN_DPTF); |
| 224 | params->Device4Enable = is_dev_enabled(dev); |
| 225 | |
| 226 | /* Set TccActivationOffset */ |
| 227 | params->TccActivationOffset = config->tcc_offset; |
| 228 | |
| 229 | /* LAN */ |
| 230 | dev = pcidev_path_on_root(PCH_DEVFN_GBE); |
| 231 | params->PchLanEnable = is_dev_enabled(dev); |
| 232 | |
| 233 | /* CNVi */ |
| 234 | dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI); |
| 235 | params->CnviMode = is_dev_enabled(dev); |
| 236 | |
| 237 | /* CNVi BT Core */ |
| 238 | dev = pcidev_path_on_root(PCH_DEVFN_CNVI_BT); |
| 239 | params->CnviBtCore = is_dev_enabled(dev); |
| 240 | |
| 241 | /* CNVi BT Audio Offload */ |
| 242 | params->CnviBtAudioOffload = config->CnviBtAudioOffload; |
| 243 | |
| 244 | /* VMD */ |
| 245 | dev = pcidev_path_on_root(SA_DEVFN_VMD); |
| 246 | params->VmdEnable = is_dev_enabled(dev); |
| 247 | |
| 248 | /* THC */ |
| 249 | dev = pcidev_path_on_root(PCH_DEVFN_THC0); |
| 250 | params->ThcPort0Assignment = is_dev_enabled(dev) ? THC_0 : THC_NONE; |
| 251 | |
| 252 | dev = pcidev_path_on_root(PCH_DEVFN_THC1); |
| 253 | params->ThcPort1Assignment = is_dev_enabled(dev) ? THC_1 : THC_NONE; |
| 254 | |
| 255 | /* Legacy 8254 timer support */ |
| 256 | params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); |
| 257 | params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); |
| 258 | |
| 259 | /* Enable Hybrid storage auto detection */ |
| 260 | params->HybridStorageMode = config->HybridStorageMode; |
| 261 | |
| 262 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
| 263 | params->PcieRpL1Substates[i] = |
| 264 | get_l1_substate_control(config->PcieRpL1Substates[i]); |
| 265 | params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; |
| 266 | params->PcieRpAdvancedErrorReporting[i] = |
| 267 | config->PcieRpAdvancedErrorReporting[i]; |
| 268 | params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; |
| 269 | } |
| 270 | |
| 271 | /* Enable ClkReqDetect for enabled port */ |
| 272 | memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, |
| 273 | sizeof(config->PcieRpClkReqDetect)); |
| 274 | |
| 275 | params->PmSupport = 1; |
| 276 | params->Hwp = 1; |
| 277 | params->Cx = 1; |
| 278 | params->PsOnEnable = 1; |
| 279 | |
| 280 | mainboard_silicon_init_params(params); |
| 281 | } |
| 282 | |
| 283 | int soc_fsp_multi_phase_init_is_enable(void) |
| 284 | { |
| 285 | return 0; |
| 286 | } |
| 287 | |
| 288 | /* |
| 289 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 290 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 291 | * Phase | FSP return point | Purpose |
| 292 | * ------- + ------------------------------------------------ + ------------------------------- |
| 293 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 294 | */ |
| 295 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 296 | { |
| 297 | switch (phase_index) { |
| 298 | case 1: |
| 299 | /* TCSS specific initialization here */ |
| 300 | break; |
| 301 | default: |
| 302 | break; |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | /* Mainboard GPIO Configuration */ |
| 307 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 308 | { |
| 309 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 310 | } |
| 311 | |
| 312 | /* Return list of SOC LPSS controllers */ |
| 313 | const pci_devfn_t *soc_lpss_controllers_list(size_t *size) |
| 314 | { |
| 315 | *size = ARRAY_SIZE(serial_io_dev); |
| 316 | return serial_io_dev; |
| 317 | } |