Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 4 | #include <cbfs.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <fsp/api.h> |
| 9 | #include <fsp/ppi/mp_service_ppi.h> |
| 10 | #include <fsp/util.h> |
| 11 | #include <intelblocks/lpss.h> |
| 12 | #include <intelblocks/xdci.h> |
| 13 | #include <intelpch/lockdown.h> |
| 14 | #include <intelblocks/mp_init.h> |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 15 | #include <intelblocks/tcss.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 16 | #include <soc/gpio_soc_defs.h> |
| 17 | #include <soc/intel/common/vbt.h> |
| 18 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 19 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 20 | #include <soc/ramstage.h> |
| 21 | #include <soc/soc_chip.h> |
| 22 | #include <string.h> |
| 23 | |
| 24 | /* THC assignment definition */ |
| 25 | #define THC_NONE 0 |
| 26 | #define THC_0 1 |
| 27 | #define THC_1 2 |
| 28 | |
| 29 | /* SATA DEVSLP idle timeout default values */ |
| 30 | #define DEF_DMVAL 15 |
| 31 | #define DEF_DITOVAL 625 |
| 32 | |
| 33 | /* |
| 34 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 35 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 36 | * In order to ensure that mainboard setting does not disable L1 substates |
| 37 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 38 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 39 | * value is set in fsp_params. |
| 40 | * 0: Use FSP UPD default |
| 41 | * 1: Disable L1 substates |
| 42 | * 2: Use L1.1 |
| 43 | * 3: Use L1.2 (FSP UPD default) |
| 44 | */ |
| 45 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 46 | { |
| 47 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 48 | ctl = L1_SS_L1_2; |
| 49 | return ctl - 1; |
| 50 | } |
| 51 | |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 52 | static void parse_devicetree(FSP_S_CONFIG *s_cfg) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 53 | { |
| 54 | const struct soc_intel_alderlake_config *config; |
| 55 | config = config_of_soc(); |
| 56 | |
| 57 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 58 | s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 59 | |
| 60 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 61 | s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 62 | s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 63 | s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 67 | s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 68 | } |
| 69 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 70 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
| 71 | { |
| 72 | /* Override settings per board. */ |
| 73 | } |
| 74 | |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 75 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 76 | struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 77 | { |
| 78 | int i; |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 79 | const struct microcode *microcode_file; |
| 80 | size_t microcode_len; |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 81 | uint32_t enable_mask; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 82 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 83 | mainboard_update_soc_chip_config(config); |
| 84 | |
| 85 | /* Parse device tree and enable/disable Serial I/O devices */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 86 | parse_devicetree(s_cfg); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 87 | |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 88 | microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len); |
| 89 | |
| 90 | if ((microcode_file != NULL) && (microcode_len != 0)) { |
| 91 | /* Update CPU Microcode patch base address/size */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 92 | s_cfg->MicrocodeRegionBase = (uint32_t)microcode_file; |
| 93 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 94 | } |
| 95 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 96 | /* Load VBT before devicetree-specific config. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 97 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 98 | |
| 99 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 100 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
| 101 | s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 102 | |
| 103 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 104 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 105 | s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 106 | |
| 107 | /* D3Hot and D3Cold for TCSS */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 108 | s_cfg->D3HotEnable = !config->TcssD3HotDisable; |
| 109 | s_cfg->D3ColdEnable = !config->TcssD3ColdDisable; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 110 | |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 111 | s_cfg->TcssAuxOri = config->TcssAuxOri; |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 112 | |
| 113 | /* Explicitly clear this field to avoid using defaults */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 114 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 118 | * evaluate this UPD value and skip sending command. There will be no |
| 119 | * delay for command completion. |
| 120 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 121 | s_cfg->ITbtConnectTopologyTimeoutInMs = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 122 | |
| 123 | /* Chipset Lockdown */ |
| 124 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 125 | s_cfg->PchLockDownGlobalSmi = 0; |
| 126 | s_cfg->PchLockDownBiosInterface = 0; |
| 127 | s_cfg->PchUnlockGpioPads = 1; |
| 128 | s_cfg->RtcMemoryLock = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 129 | } else { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 130 | s_cfg->PchLockDownGlobalSmi = 1; |
| 131 | s_cfg->PchLockDownBiosInterface = 1; |
| 132 | s_cfg->PchUnlockGpioPads = 0; |
| 133 | s_cfg->RtcMemoryLock = 1; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 134 | } |
| 135 | |
| 136 | /* USB */ |
| 137 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 138 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 139 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 140 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 141 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 142 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 143 | |
| 144 | if (config->usb2_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 145 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 146 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 147 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 151 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 152 | if (config->usb3_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 153 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 154 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 155 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 156 | |
| 157 | if (config->usb3_ports[i].tx_de_emp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 158 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 159 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 160 | } |
| 161 | if (config->usb3_ports[i].tx_downscale_amp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 162 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 163 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 164 | config->usb3_ports[i].tx_downscale_amp; |
| 165 | } |
| 166 | } |
| 167 | |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 168 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 169 | if (config->tcss_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 170 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 171 | } |
| 172 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 173 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
Subrata Banik | e633804 | 2021-06-21 19:26:10 +0530 | [diff] [blame] | 174 | if (!xdci_can_enable()) |
| 175 | devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 176 | s_cfg->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 177 | |
| 178 | /* PCH UART selection for FSP Debug */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 179 | s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 180 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 181 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 182 | |
| 183 | /* SATA */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 184 | s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
| 185 | if (s_cfg->SataEnable) { |
| 186 | s_cfg->SataMode = config->SataMode; |
| 187 | s_cfg->SataSalpSupport = config->SataSalpSupport; |
| 188 | memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable, |
| 189 | sizeof(s_cfg->SataPortsEnable)); |
| 190 | memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp, |
| 191 | sizeof(s_cfg->SataPortsDevSlp)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | /* |
| 195 | * Power Optimizer for DMI and SATA. |
| 196 | * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. |
| 197 | * Boards not needing the optimizers explicitly disables them by setting |
| 198 | * these disable variables to 1 in devicetree overrides. |
| 199 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 200 | s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); |
| 201 | s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 202 | |
| 203 | /* |
| 204 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 205 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 206 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 207 | * The default values can be changed from devicetree. |
| 208 | */ |
| 209 | for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { |
| 210 | if (config->SataPortsEnableDitoConfig[i]) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 211 | s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i]; |
| 212 | s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 213 | } |
| 214 | } |
| 215 | |
| 216 | /* Enable TCPU for processor thermal control */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 217 | s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 218 | |
| 219 | /* Set TccActivationOffset */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 220 | s_cfg->TccActivationOffset = config->tcc_offset; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 221 | |
| 222 | /* LAN */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 223 | s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 224 | |
| 225 | /* CNVi */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 226 | s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
| 227 | s_cfg->CnviBtCore = config->CnviBtCore; |
| 228 | s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload; |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 229 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 230 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 231 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 232 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 233 | |
| 234 | /* VMD */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 235 | s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 236 | |
| 237 | /* THC */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 238 | s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; |
| 239 | s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 240 | |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 241 | /* USB4/TBT */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 242 | for (i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
| 243 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i)); |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 244 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 245 | /* Legacy 8254 timer support */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 246 | s_cfg->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); |
| 247 | s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 248 | |
| 249 | /* Enable Hybrid storage auto detection */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 250 | s_cfg->HybridStorageMode = config->HybridStorageMode; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 251 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 252 | enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
Subrata Banik | 85144d9 | 2021-01-09 16:17:45 +0530 | [diff] [blame] | 253 | for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 254 | if (!(enable_mask & BIT(i))) |
| 255 | continue; |
| 256 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 257 | s_cfg->PcieRpL1Substates[i] = |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 258 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 259 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 260 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
| 261 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); |
| 262 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 263 | } |
| 264 | |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 265 | s_cfg->PmSupport = 1; |
| 266 | s_cfg->Hwp = 1; |
| 267 | s_cfg->Cx = 1; |
| 268 | s_cfg->PsOnEnable = 1; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 269 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 270 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 271 | static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) |
| 272 | { |
| 273 | /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ |
| 274 | s_arch_cfg->EnableMultiPhaseSiliconInit = 1; |
| 275 | } |
| 276 | |
| 277 | /* UPD parameters to be initialized before SiliconInit */ |
| 278 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 279 | { |
| 280 | struct soc_intel_alderlake_config *config; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 281 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 282 | FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd; |
| 283 | |
| 284 | config = config_of_soc(); |
| 285 | |
| 286 | arch_silicon_init_params(s_arch_cfg); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 287 | soc_silicon_init_params(s_cfg, config); |
| 288 | mainboard_silicon_init_params(s_cfg); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 289 | } |
| 290 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 291 | /* |
| 292 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 293 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 294 | * Phase | FSP return point | Purpose |
| 295 | * ------- + ------------------------------------------------ + ------------------------------- |
| 296 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 297 | */ |
| 298 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 299 | { |
| 300 | switch (phase_index) { |
| 301 | case 1: |
| 302 | /* TCSS specific initialization here */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 303 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 304 | __FILE__, __func__); |
| 305 | |
| 306 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 307 | const config_t *config = config_of_soc(); |
| 308 | tcss_configure(config->typec_aux_bias_pads); |
| 309 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 310 | break; |
| 311 | default: |
| 312 | break; |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | /* Mainboard GPIO Configuration */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame^] | 317 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 318 | { |
| 319 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 320 | } |