Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 4 | * Copyright (C) 2015 - 2017 Intel Corp. |
Werner Zeh | de3ace0 | 2019-01-15 08:03:43 +0100 | [diff] [blame] | 5 | * Copyright (C) 2017 - 2019 Siemens AG |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 6 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 7 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 18 | */ |
| 19 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 21 | #include <bootstate.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 22 | #include <cbmem.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 23 | #include <console/console.h> |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 24 | #include <cpu/x86/mp.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 25 | #include <cpu/x86/msr.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 26 | #include <device/mmio.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 27 | #include <device/device.h> |
| 28 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 29 | #include <device/pci_ops.h> |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 30 | #include <intelblocks/acpi.h> |
Subrata Banik | f699c14 | 2018-06-08 17:57:37 +0530 | [diff] [blame] | 31 | #include <intelblocks/chip.h> |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 32 | #include <intelblocks/fast_spi.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 33 | #include <intelblocks/msr.h> |
Subrata Banik | f699c14 | 2018-06-08 17:57:37 +0530 | [diff] [blame] | 34 | #include <intelblocks/p2sb.h> |
Duncan Laurie | 4c8fbc0 | 2018-03-26 02:19:58 -0700 | [diff] [blame] | 35 | #include <intelblocks/xdci.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 36 | #include <fsp/api.h> |
| 37 | #include <fsp/util.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 38 | #include <intelblocks/cpulib.h> |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 39 | #include <intelblocks/itss.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 40 | #include <intelblocks/pmclib.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 41 | #include <romstage_handoff.h> |
Furquan Shaikh | d2c2f83 | 2018-11-07 10:24:31 -0800 | [diff] [blame] | 42 | #include <soc/cpu.h> |
| 43 | #include <soc/heci.h> |
| 44 | #include <soc/intel/common/vbt.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 45 | #include <soc/iomap.h> |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 46 | #include <soc/itss.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 47 | #include <soc/nvs.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 48 | #include <soc/pci_devs.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 49 | #include <soc/pm.h> |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 50 | #include <soc/systemagent.h> |
Furquan Shaikh | d2c2f83 | 2018-11-07 10:24:31 -0800 | [diff] [blame] | 51 | #include <spi-generic.h> |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 52 | #include <timer.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 53 | |
| 54 | #include "chip.h" |
| 55 | |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 56 | #define DUAL_ROLE_CFG0 0x80d8 |
| 57 | #define SW_VBUS_VALID_MASK (1 << 24) |
| 58 | #define SW_IDPIN_EN_MASK (1 << 21) |
| 59 | #define SW_IDPIN_MASK (1 << 20) |
| 60 | #define SW_IDPIN_HOST (0 << 20) |
| 61 | #define DUAL_ROLE_CFG1 0x80dc |
| 62 | #define DRD_MODE_MASK (1 << 29) |
| 63 | #define DRD_MODE_HOST (1 << 29) |
| 64 | |
John Zhao | 57aa8b6 | 2019-01-14 09:15:50 -0800 | [diff] [blame] | 65 | #define CFG_XHCLKGTEN 0x8650 |
| 66 | /* Naking USB2.0 EPs for Backbone Clock Gating and PLL Shutdown */ |
| 67 | #define NUEFBCGPS (1 << 28) |
| 68 | /* SRAM Power Gate Enable */ |
| 69 | #define SRAMPGTEN (1 << 27) |
| 70 | /* SS Link PLL Shutdown Enable */ |
| 71 | #define SSLSE (1 << 26) |
| 72 | /* USB2 PLL Shutdown Enable */ |
| 73 | #define USB2PLLSE (1 << 25) |
| 74 | /* IOSF Sideband Trunk Clock Gating Enable */ |
| 75 | #define IOSFSTCGE (1 << 24) |
| 76 | /* BIT[23:20] HS Backbone PXP Trunk Clock Gate Enable */ |
| 77 | #define HSTCGE (1 << 23 | 1 << 22) |
| 78 | /* BIT[19:16] SS Backbone PXP Trunk Clock Gate Enable */ |
| 79 | #define SSTCGE (1 << 19 | 1 << 18 | 1 << 17) |
| 80 | /* XHC Ignore_EU3S */ |
| 81 | #define XHCIGEU3S (1 << 15) |
| 82 | /* XHC Frame Timer Clock Shutdown Enable */ |
| 83 | #define XHCFTCLKSE (1 << 14) |
| 84 | /* XHC Backbone PXP Trunk Clock Gate In Presence of ISOCH EP */ |
| 85 | #define XHCBBTCGIPISO (1 << 13) |
| 86 | /* XHC HS Backbone PXP Trunk Clock Gate U2 non RWE */ |
| 87 | #define XHCHSTCGU2NRWE (1 << 12) |
| 88 | /* BIT[11:10] XHC USB2 PLL Shutdown Lx Enable */ |
| 89 | #define XHCUSB2PLLSDLE (1 << 11 | 1 << 10) |
| 90 | /* BIT[9:8] HS Backbone PXP PLL Shutdown Ux Enable */ |
| 91 | #define HSUXDMIPLLSE (1 << 9) |
| 92 | /* BIT[7:5] SS Backbone PXP PLL shutdown Ux Enable */ |
| 93 | #define SSPLLSUE (1 << 6) |
| 94 | /* XHC Backbone Local Clock Gating Enable */ |
| 95 | #define XHCBLCGE (1 << 4) |
| 96 | /* HS Link Trunk Clock Gating Enable */ |
| 97 | #define HSLTCGE (1 << 3) |
| 98 | /* SS Link Trunk Clock Gating Enable */ |
| 99 | #define SSLTCGE (1 << 2) |
| 100 | /* IOSF Backbone Trunk Clock Gating Enable */ |
| 101 | #define IOSFBTCGE (1 << 1) |
| 102 | /* IOSF Gasket Backbone Local Clock Gating Enable */ |
| 103 | #define IOSFGBLCGE (1 << 0) |
| 104 | |
Duncan Laurie | bf713b0 | 2018-05-07 15:33:18 -0700 | [diff] [blame] | 105 | const char *soc_acpi_name(const struct device *dev) |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 106 | { |
| 107 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 108 | return "PCI0"; |
| 109 | |
Duncan Laurie | bf713b0 | 2018-05-07 15:33:18 -0700 | [diff] [blame] | 110 | if (dev->path.type == DEVICE_PATH_USB) { |
| 111 | switch (dev->path.usb.port_type) { |
| 112 | case 0: |
| 113 | /* Root Hub */ |
| 114 | return "RHUB"; |
| 115 | case 2: |
| 116 | /* USB2 ports */ |
| 117 | switch (dev->path.usb.port_id) { |
| 118 | case 0: return "HS01"; |
| 119 | case 1: return "HS02"; |
| 120 | case 2: return "HS03"; |
| 121 | case 3: return "HS04"; |
| 122 | case 4: return "HS05"; |
| 123 | case 5: return "HS06"; |
| 124 | case 6: return "HS07"; |
| 125 | case 7: return "HS08"; |
Furquan Shaikh | ad62b9a | 2019-01-30 22:47:17 -0800 | [diff] [blame] | 126 | case 8: |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 127 | if (CONFIG(SOC_INTEL_GLK)) |
Furquan Shaikh | ad62b9a | 2019-01-30 22:47:17 -0800 | [diff] [blame] | 128 | return "HS09"; |
Duncan Laurie | bf713b0 | 2018-05-07 15:33:18 -0700 | [diff] [blame] | 129 | } |
| 130 | break; |
| 131 | case 3: |
| 132 | /* USB3 ports */ |
| 133 | switch (dev->path.usb.port_id) { |
| 134 | case 0: return "SS01"; |
| 135 | case 1: return "SS02"; |
| 136 | case 2: return "SS03"; |
| 137 | case 3: return "SS04"; |
| 138 | case 4: return "SS05"; |
| 139 | case 5: return "SS06"; |
| 140 | } |
| 141 | break; |
| 142 | } |
| 143 | return NULL; |
| 144 | } |
| 145 | |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 146 | if (dev->path.type != DEVICE_PATH_PCI) |
| 147 | return NULL; |
| 148 | |
| 149 | switch (dev->path.pci.devfn) { |
| 150 | /* DSDT: acpi/northbridge.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 151 | case SA_DEVFN_ROOT: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 152 | return "MCHC"; |
| 153 | /* DSDT: acpi/lpc.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 154 | case PCH_DEVFN_LPC: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 155 | return "LPCB"; |
| 156 | /* DSDT: acpi/xhci.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 157 | case PCH_DEVFN_XHCI: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 158 | return "XHCI"; |
| 159 | /* DSDT: acpi/pch_hda.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 160 | case PCH_DEVFN_HDA: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 161 | return "HDAS"; |
| 162 | /* DSDT: acpi/lpss.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 163 | case PCH_DEVFN_UART0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 164 | return "URT1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 165 | case PCH_DEVFN_UART1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 166 | return "URT2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 167 | case PCH_DEVFN_UART2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 168 | return "URT3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 169 | case PCH_DEVFN_UART3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 170 | return "URT4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 171 | case PCH_DEVFN_SPI0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 172 | return "SPI1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 173 | case PCH_DEVFN_SPI1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 174 | return "SPI2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 175 | case PCH_DEVFN_SPI2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 176 | return "SPI3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 177 | case PCH_DEVFN_PWM: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 178 | return "PWM"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 179 | case PCH_DEVFN_I2C0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 180 | return "I2C0"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 181 | case PCH_DEVFN_I2C1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 182 | return "I2C1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 183 | case PCH_DEVFN_I2C2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 184 | return "I2C2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 185 | case PCH_DEVFN_I2C3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 186 | return "I2C3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 187 | case PCH_DEVFN_I2C4: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 188 | return "I2C4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 189 | case PCH_DEVFN_I2C5: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 190 | return "I2C5"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 191 | case PCH_DEVFN_I2C6: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 192 | return "I2C6"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 193 | case PCH_DEVFN_I2C7: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 194 | return "I2C7"; |
| 195 | /* Storage */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 196 | case PCH_DEVFN_SDCARD: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 197 | return "SDCD"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 198 | case PCH_DEVFN_EMMC: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 199 | return "EMMC"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 200 | case PCH_DEVFN_SDIO: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 201 | return "SDIO"; |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 202 | /* PCIe */ |
Venkateswarlu Vinjamuri | f03c63e | 2018-04-12 10:13:43 -0700 | [diff] [blame] | 203 | case PCH_DEVFN_PCIE1: |
| 204 | return "RP03"; |
Venkateswarlu Vinjamuri | efeb690 | 2018-04-09 11:14:42 -0700 | [diff] [blame] | 205 | case PCH_DEVFN_PCIE5: |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 206 | return "RP01"; |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | return NULL; |
| 210 | } |
| 211 | |
Elyes HAOUAS | 06e8315 | 2018-05-24 22:48:14 +0200 | [diff] [blame] | 212 | static void pci_domain_set_resources(struct device *dev) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 213 | { |
Lee Leahy | 1d20fe7 | 2017-03-09 09:50:28 -0800 | [diff] [blame] | 214 | assign_resources(dev->link_list); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | static struct device_operations pci_domain_ops = { |
| 218 | .read_resources = pci_domain_read_resources, |
| 219 | .set_resources = pci_domain_set_resources, |
| 220 | .enable_resources = NULL, |
| 221 | .init = NULL, |
| 222 | .scan_bus = pci_domain_scan_bus, |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 223 | .acpi_name = &soc_acpi_name, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 224 | }; |
| 225 | |
| 226 | static struct device_operations cpu_bus_ops = { |
| 227 | .read_resources = DEVICE_NOOP, |
| 228 | .set_resources = DEVICE_NOOP, |
| 229 | .enable_resources = DEVICE_NOOP, |
Aaron Durbin | ac3e482 | 2017-06-14 13:21:00 -0500 | [diff] [blame] | 230 | .init = apollolake_init_cpus, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 231 | .scan_bus = NULL, |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 232 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 233 | }; |
| 234 | |
Elyes HAOUAS | 06e8315 | 2018-05-24 22:48:14 +0200 | [diff] [blame] | 235 | static void enable_dev(struct device *dev) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 236 | { |
| 237 | /* Set the operations if it is a special bus type */ |
Lee Leahy | 4430f9f | 2017-03-09 10:00:30 -0800 | [diff] [blame] | 238 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 239 | dev->ops = &pci_domain_ops; |
Lee Leahy | 4430f9f | 2017-03-09 10:00:30 -0800 | [diff] [blame] | 240 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 241 | dev->ops = &cpu_bus_ops; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 242 | } |
| 243 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 244 | /* |
| 245 | * If the PCIe root port at function 0 is disabled, |
| 246 | * the PCIe root ports might be coalesced after FSP silicon init. |
| 247 | * The below function will swap the devfn of the first enabled device |
| 248 | * in devicetree and function 0 resides a pci device |
| 249 | * so that it won't confuse coreboot. |
| 250 | */ |
| 251 | static void pcie_update_device_tree(unsigned int devfn0, int num_funcs) |
| 252 | { |
Elyes HAOUAS | 06e8315 | 2018-05-24 22:48:14 +0200 | [diff] [blame] | 253 | struct device *func0; |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 254 | unsigned int devfn; |
| 255 | int i; |
| 256 | unsigned int inc = PCI_DEVFN(0, 1); |
| 257 | |
| 258 | func0 = dev_find_slot(0, devfn0); |
| 259 | if (func0 == NULL) |
| 260 | return; |
| 261 | |
| 262 | /* No more functions if function 0 is disabled. */ |
| 263 | if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) |
| 264 | return; |
| 265 | |
| 266 | devfn = devfn0 + inc; |
| 267 | |
| 268 | /* |
| 269 | * Increase funtion by 1. |
| 270 | * Then find first enabled device to replace func0 |
| 271 | * as that port was move to func0. |
| 272 | */ |
| 273 | for (i = 1; i < num_funcs; i++, devfn += inc) { |
Elyes HAOUAS | 06e8315 | 2018-05-24 22:48:14 +0200 | [diff] [blame] | 274 | struct device *dev = dev_find_slot(0, devfn); |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 275 | if (dev == NULL) |
| 276 | continue; |
| 277 | |
| 278 | if (!dev->enabled) |
| 279 | continue; |
| 280 | /* Found the first enabled device in given dev number */ |
| 281 | func0->path.pci.devfn = dev->path.pci.devfn; |
| 282 | dev->path.pci.devfn = devfn0; |
| 283 | break; |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | static void pcie_override_devicetree_after_silicon_init(void) |
| 288 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 289 | pcie_update_device_tree(PCH_DEVFN_PCIE1, 4); |
| 290 | pcie_update_device_tree(PCH_DEVFN_PCIE5, 2); |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 291 | } |
| 292 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 293 | /* Configure package power limits */ |
| 294 | static void set_power_limits(void) |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 295 | { |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 296 | static struct soc_intel_apollolake_config *cfg; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 297 | struct device *dev = SA_DEV_ROOT; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 298 | msr_t rapl_msr_reg, limit; |
| 299 | uint32_t power_unit; |
| 300 | uint32_t tdp, min_power, max_power; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 301 | uint32_t pl2_val; |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 302 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 303 | if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { |
Mario Scheithauer | 38b6100 | 2017-07-25 10:52:41 +0200 | [diff] [blame] | 304 | printk(BIOS_INFO, "Skip the RAPL settings.\n"); |
| 305 | return; |
| 306 | } |
| 307 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 308 | if (!dev || !dev->chip_info) { |
| 309 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 310 | return; |
| 311 | } |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 312 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 313 | cfg = dev->chip_info; |
| 314 | |
| 315 | /* Get units */ |
| 316 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 317 | power_unit = 1 << (rapl_msr_reg.lo & 0xf); |
| 318 | |
| 319 | /* Get power defaults for this SKU */ |
| 320 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); |
| 321 | tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 322 | pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 323 | min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; |
| 324 | max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
| 325 | |
| 326 | if (min_power > 0 && tdp < min_power) |
| 327 | tdp = min_power; |
| 328 | |
| 329 | if (max_power > 0 && tdp > max_power) |
| 330 | tdp = max_power; |
| 331 | |
| 332 | /* Set PL1 override value */ |
| 333 | tdp = (cfg->tdp_pl1_override_mw == 0) ? |
| 334 | tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 335 | /* Set PL2 override value */ |
| 336 | pl2_val = (cfg->tdp_pl2_override_mw == 0) ? |
| 337 | pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 338 | |
| 339 | /* Set long term power limit to TDP */ |
| 340 | limit.lo = tdp & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 341 | /* Set PL1 Pkg Power clamp bit */ |
| 342 | limit.lo |= PKG_POWER_LIMIT_CLAMP; |
| 343 | |
| 344 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 345 | limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & |
| 346 | PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; |
| 347 | |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 348 | /* Set short term power limit PL2 */ |
| 349 | limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; |
| 350 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 351 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 352 | /* Program package power limits in RAPL MSR */ |
| 353 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 354 | printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, |
| 355 | 100 * (tdp % power_unit) / power_unit); |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 356 | printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, |
| 357 | 100 * (pl2_val % power_unit) / power_unit); |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 358 | |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 359 | /* Setting RAPL MMIO register for Power limits. |
| 360 | * RAPL driver is using MSR instead of MMIO. |
| 361 | * So, disabled LIMIT_EN bit for MMIO. */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 362 | MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~PKG_POWER_LIMIT_EN; |
| 363 | MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN; |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 364 | } |
| 365 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 366 | /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */ |
| 367 | static void set_sci_irq(void) |
| 368 | { |
| 369 | static struct soc_intel_apollolake_config *cfg; |
| 370 | struct device *dev = SA_DEV_ROOT; |
| 371 | uint32_t scis; |
| 372 | |
| 373 | if (!dev || !dev->chip_info) { |
| 374 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 375 | return; |
| 376 | } |
| 377 | |
| 378 | cfg = dev->chip_info; |
| 379 | |
| 380 | /* Change only if a device tree entry exists. */ |
| 381 | if (cfg->sci_irq) { |
| 382 | scis = soc_read_sci_irq_select(); |
| 383 | scis &= ~SCI_IRQ_SEL; |
| 384 | scis |= (cfg->sci_irq << SCI_IRQ_ADJUST) & SCI_IRQ_SEL; |
| 385 | soc_write_sci_irq_select(scis); |
| 386 | } |
| 387 | } |
| 388 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 389 | static void soc_init(void *data) |
| 390 | { |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 391 | struct global_nvs_t *gnvs; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 392 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 393 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 394 | * default policy that doesn't honor boards' requirements. */ |
| 395 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 396 | |
Aaron Durbin | 6c191d8 | 2016-11-29 21:22:42 -0600 | [diff] [blame] | 397 | fsp_silicon_init(romstage_handoff_is_resume()); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 398 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 399 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 400 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 401 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 402 | /* override 'enabled' setting in device tree if needed */ |
| 403 | pcie_override_devicetree_after_silicon_init(); |
| 404 | |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 405 | /* |
| 406 | * Keep the P2SB device visible so it and the other devices are |
| 407 | * visible in coreboot for driver support and PCI resource allocation. |
| 408 | * There is a UPD setting for this, but it's more consistent to use |
| 409 | * hide and unhide symmetrically. |
| 410 | */ |
| 411 | p2sb_unhide(); |
| 412 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 413 | /* Allocate ACPI NVS in CBMEM */ |
| 414 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 415 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 416 | /* Set RAPL MSR for Package power limits*/ |
| 417 | set_power_limits(); |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 418 | |
| 419 | /* |
| 420 | * FSP-S routes SCI to IRQ 9. With the help of this function you can |
| 421 | * select another IRQ for SCI. |
| 422 | */ |
| 423 | set_sci_irq(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 424 | } |
| 425 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 426 | static void soc_final(void *data) |
| 427 | { |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 428 | /* Disable global reset, just in case */ |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 429 | pmc_global_reset_enable(0); |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 430 | /* Make sure payload/OS can't trigger global reset */ |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 431 | pmc_global_reset_lock(); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 432 | } |
| 433 | |
Lee Leahy | bab8be2 | 2017-03-09 09:53:58 -0800 | [diff] [blame] | 434 | static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) |
| 435 | { |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 436 | switch (dev->path.pci.devfn) { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 437 | case PCH_DEVFN_ISH: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 438 | silconfig->IshEnable = 0; |
| 439 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 440 | case PCH_DEVFN_SATA: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 441 | silconfig->EnableSata = 0; |
| 442 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 443 | case PCH_DEVFN_PCIE5: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 444 | silconfig->PcieRootPortEn[0] = 0; |
| 445 | silconfig->PcieRpHotPlug[0] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 446 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 447 | case PCH_DEVFN_PCIE6: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 448 | silconfig->PcieRootPortEn[1] = 0; |
| 449 | silconfig->PcieRpHotPlug[1] = 0; |
| 450 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 451 | case PCH_DEVFN_PCIE1: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 452 | silconfig->PcieRootPortEn[2] = 0; |
| 453 | silconfig->PcieRpHotPlug[2] = 0; |
| 454 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 455 | case PCH_DEVFN_PCIE2: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 456 | silconfig->PcieRootPortEn[3] = 0; |
| 457 | silconfig->PcieRpHotPlug[3] = 0; |
| 458 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 459 | case PCH_DEVFN_PCIE3: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 460 | silconfig->PcieRootPortEn[4] = 0; |
| 461 | silconfig->PcieRpHotPlug[4] = 0; |
| 462 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 463 | case PCH_DEVFN_PCIE4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 464 | silconfig->PcieRootPortEn[5] = 0; |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 465 | silconfig->PcieRpHotPlug[5] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 466 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 467 | case PCH_DEVFN_XHCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 468 | silconfig->Usb30Mode = 0; |
| 469 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 470 | case PCH_DEVFN_XDCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 471 | silconfig->UsbOtg = 0; |
| 472 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 473 | case PCH_DEVFN_I2C0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 474 | silconfig->I2c0Enable = 0; |
| 475 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 476 | case PCH_DEVFN_I2C1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 477 | silconfig->I2c1Enable = 0; |
| 478 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 479 | case PCH_DEVFN_I2C2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 480 | silconfig->I2c2Enable = 0; |
| 481 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 482 | case PCH_DEVFN_I2C3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 483 | silconfig->I2c3Enable = 0; |
| 484 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 485 | case PCH_DEVFN_I2C4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 486 | silconfig->I2c4Enable = 0; |
| 487 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 488 | case PCH_DEVFN_I2C5: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 489 | silconfig->I2c5Enable = 0; |
| 490 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 491 | case PCH_DEVFN_I2C6: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 492 | silconfig->I2c6Enable = 0; |
| 493 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 494 | case PCH_DEVFN_I2C7: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 495 | silconfig->I2c7Enable = 0; |
| 496 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 497 | case PCH_DEVFN_UART0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 498 | silconfig->Hsuart0Enable = 0; |
| 499 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 500 | case PCH_DEVFN_UART1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 501 | silconfig->Hsuart1Enable = 0; |
| 502 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 503 | case PCH_DEVFN_UART2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 504 | silconfig->Hsuart2Enable = 0; |
| 505 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 506 | case PCH_DEVFN_UART3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 507 | silconfig->Hsuart3Enable = 0; |
| 508 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 509 | case PCH_DEVFN_SPI0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 510 | silconfig->Spi0Enable = 0; |
| 511 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 512 | case PCH_DEVFN_SPI1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 513 | silconfig->Spi1Enable = 0; |
| 514 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 515 | case PCH_DEVFN_SPI2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 516 | silconfig->Spi2Enable = 0; |
| 517 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 518 | case PCH_DEVFN_SDCARD: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 519 | silconfig->SdcardEnabled = 0; |
| 520 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 521 | case PCH_DEVFN_EMMC: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 522 | silconfig->eMMCEnabled = 0; |
| 523 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 524 | case PCH_DEVFN_SDIO: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 525 | silconfig->SdioEnabled = 0; |
| 526 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 527 | case PCH_DEVFN_SMBUS: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 528 | silconfig->SmbusEnable = 0; |
| 529 | break; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 530 | #if !CONFIG(SOC_INTEL_GLK) |
Werner Zeh | de3ace0 | 2019-01-15 08:03:43 +0100 | [diff] [blame] | 531 | case SA_DEVFN_IPU: |
| 532 | silconfig->IpuEn = 0; |
| 533 | break; |
| 534 | #endif |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 535 | default: |
| 536 | printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", |
| 537 | PCI_SLOT(dev->path.pci.devfn), |
| 538 | PCI_FUNC(dev->path.pci.devfn)); |
| 539 | break; |
| 540 | } |
| 541 | } |
| 542 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 543 | static void parse_devicetree(FSP_S_CONFIG *silconfig) |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 544 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 545 | struct device *dev = SA_DEV_ROOT; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 546 | |
| 547 | if (!dev) { |
| 548 | printk(BIOS_ERR, "Could not find root device\n"); |
| 549 | return; |
| 550 | } |
| 551 | /* Only disable bus 0 devices. */ |
| 552 | for (dev = dev->bus->children; dev; dev = dev->sibling) { |
| 553 | if (!dev->enabled) |
| 554 | disable_dev(dev, silconfig); |
| 555 | } |
| 556 | } |
| 557 | |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 558 | static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config |
| 559 | *cfg, FSP_S_CONFIG *silconfig) |
| 560 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 561 | #if !CONFIG(SOC_INTEL_GLK) /* GLK FSP does not have these |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 562 | fields in FspsUpd.h yet */ |
| 563 | uint8_t port; |
| 564 | |
| 565 | for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { |
| 566 | if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0) |
| 567 | silconfig->PortUsb20PerPortTxPeHalf[port] = |
| 568 | cfg->usb2eye[port].Usb20PerPortTxPeHalf; |
| 569 | |
| 570 | if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0) |
| 571 | silconfig->PortUsb20PerPortPeTxiSet[port] = |
| 572 | cfg->usb2eye[port].Usb20PerPortPeTxiSet; |
| 573 | |
| 574 | if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0) |
| 575 | silconfig->PortUsb20PerPortTxiSet[port] = |
| 576 | cfg->usb2eye[port].Usb20PerPortTxiSet; |
| 577 | |
| 578 | if (cfg->usb2eye[port].Usb20HsSkewSel != 0) |
| 579 | silconfig->PortUsb20HsSkewSel[port] = |
| 580 | cfg->usb2eye[port].Usb20HsSkewSel; |
| 581 | |
| 582 | if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0) |
| 583 | silconfig->PortUsb20IUsbTxEmphasisEn[port] = |
| 584 | cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; |
| 585 | |
| 586 | if (cfg->usb2eye[port].Usb20PerPortRXISet != 0) |
| 587 | silconfig->PortUsb20PerPortRXISet[port] = |
| 588 | cfg->usb2eye[port].Usb20PerPortRXISet; |
| 589 | |
| 590 | if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0) |
| 591 | silconfig->PortUsb20HsNpreDrvSel[port] = |
| 592 | cfg->usb2eye[port].Usb20HsNpreDrvSel; |
| 593 | } |
| 594 | #endif |
| 595 | } |
| 596 | |
| 597 | static void glk_fsp_silicon_init_params_cb( |
| 598 | struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) |
| 599 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 600 | #if CONFIG(SOC_INTEL_GLK) |
Seunghwan Kim | f7fd9b1 | 2019-01-24 16:17:44 +0900 | [diff] [blame] | 601 | uint8_t port; |
| 602 | |
| 603 | for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { |
| 604 | if (!cfg->usb2eye[port].Usb20OverrideEn) |
| 605 | continue; |
| 606 | |
| 607 | silconfig->Usb2AfePehalfbit[port] = |
| 608 | cfg->usb2eye[port].Usb20PerPortTxPeHalf; |
| 609 | silconfig->Usb2AfePetxiset[port] = |
| 610 | cfg->usb2eye[port].Usb20PerPortPeTxiSet; |
| 611 | silconfig->Usb2AfeTxiset[port] = |
| 612 | cfg->usb2eye[port].Usb20PerPortTxiSet; |
| 613 | silconfig->Usb2AfePredeemp[port] = |
| 614 | cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; |
| 615 | } |
| 616 | |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 617 | silconfig->Gmm = 0; |
Shamile Khan | c4276a3 | 2018-03-14 18:09:19 -0700 | [diff] [blame] | 618 | |
| 619 | /* On Geminilake, we need to override the default FSP PCIe de-emphasis |
| 620 | * settings using the device tree settings. This is because PCIe |
| 621 | * de-emphasis is enabled by default and Thunderpeak PCIe WiFi detection |
| 622 | * requires de-emphasis disabled. If we make this change common to both |
| 623 | * Apollolake and Geminilake, then we need to add mainboard device tree |
| 624 | * de-emphasis settings of 1 to Apollolake systems. |
| 625 | */ |
| 626 | memcpy(silconfig->PcieRpSelectableDeemphasis, |
| 627 | cfg->pcie_rp_deemphasis_enable, |
| 628 | sizeof(silconfig->PcieRpSelectableDeemphasis)); |
Srinidhi N Kaushik | 5af546c | 2018-05-14 23:33:55 -0700 | [diff] [blame] | 629 | /* |
| 630 | * FSP does not know what the clock requirements are for the |
| 631 | * device on SPI bus, hence it should not modify what coreboot |
| 632 | * has set up. Hence skipping in FSP. |
| 633 | */ |
| 634 | silconfig->SkipSpiPCP = 1; |
John Zhao | e673e5c | 2018-10-30 15:12:11 -0700 | [diff] [blame] | 635 | |
| 636 | /* |
| 637 | * FSP provides UPD interface to execute IPC command. In order to |
| 638 | * improve boot performance, configure PmicPmcIpcCtrl for PMC to program |
| 639 | * PMIC PCH_PWROK delay. |
John Zhao | 91600a3 | 2019-01-10 12:13:38 -0800 | [diff] [blame] | 640 | */ |
John Zhao | e673e5c | 2018-10-30 15:12:11 -0700 | [diff] [blame] | 641 | silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl; |
John Zhao | 91600a3 | 2019-01-10 12:13:38 -0800 | [diff] [blame] | 642 | |
| 643 | /* |
| 644 | * Options to disable XHCI Link Compliance Mode. |
| 645 | */ |
| 646 | silconfig->DisableComplianceMode = cfg->DisableComplianceMode; |
John Zhao | 9a4beb4 | 2019-01-28 16:04:35 -0800 | [diff] [blame] | 647 | |
| 648 | /* |
| 649 | * Options to change USB3 ModPhy setting for Integrated Filter value. |
| 650 | */ |
| 651 | silconfig->ModPhyIfValue = cfg->ModPhyIfValue; |
| 652 | |
| 653 | /* |
| 654 | * Options to bump USB3 LDO voltage with 40mv. |
| 655 | */ |
| 656 | silconfig->ModPhyVoltageBump = cfg->ModPhyVoltageBump; |
| 657 | |
| 658 | /* |
| 659 | * Options to adjust PMIC Vdd2 voltage. |
| 660 | */ |
| 661 | silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage; |
Srinidhi N Kaushik | 5af546c | 2018-05-14 23:33:55 -0700 | [diff] [blame] | 662 | #endif |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 663 | } |
| 664 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 665 | void __weak mainboard_devtree_update(struct device *dev) |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 666 | { |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 667 | /* Override dev tree settings per board */ |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 668 | } |
| 669 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 670 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 671 | { |
Lee Leahy | 1d20fe7 | 2017-03-09 09:50:28 -0800 | [diff] [blame] | 672 | FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 673 | static struct soc_intel_apollolake_config *cfg; |
| 674 | |
| 675 | /* Load VBT before devicetree-specific config. */ |
Patrick Georgi | 2257959 | 2017-10-06 17:36:09 +0200 | [diff] [blame] | 676 | silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 677 | |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 678 | struct device *dev = SA_DEV_ROOT; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 679 | |
Patrick Georgi | 831d65d | 2016-04-14 11:53:48 +0200 | [diff] [blame] | 680 | if (!dev || !dev->chip_info) { |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 681 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 682 | return; |
| 683 | } |
| 684 | |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 685 | mainboard_devtree_update(dev); |
| 686 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 687 | cfg = dev->chip_info; |
| 688 | |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 689 | /* Parse device tree and disable unused device*/ |
| 690 | parse_devicetree(silconfig); |
| 691 | |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 692 | memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin, |
| 693 | sizeof(silconfig->PcieRpClkReqNumber)); |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 694 | |
Furquan Shaikh | 2cfc862 | 2018-03-14 21:43:04 -0700 | [diff] [blame] | 695 | memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, |
| 696 | sizeof(silconfig->PcieRpHotPlug)); |
| 697 | |
Nico Huber | 8885529 | 2018-11-27 15:13:22 +0100 | [diff] [blame] | 698 | switch (cfg->serirq_mode) { |
| 699 | case SERIRQ_QUIET: |
| 700 | silconfig->SirqEnable = 1; |
| 701 | silconfig->SirqMode = 0; |
| 702 | break; |
| 703 | case SERIRQ_CONTINUOUS: |
| 704 | silconfig->SirqEnable = 1; |
| 705 | silconfig->SirqMode = 1; |
| 706 | break; |
| 707 | case SERIRQ_OFF: |
| 708 | default: |
| 709 | silconfig->SirqEnable = 0; |
| 710 | break; |
| 711 | } |
| 712 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 713 | if (cfg->emmc_tx_cmd_cntl != 0) |
| 714 | silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; |
| 715 | if (cfg->emmc_tx_data_cntl1 != 0) |
| 716 | silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; |
| 717 | if (cfg->emmc_tx_data_cntl2 != 0) |
| 718 | silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2; |
| 719 | if (cfg->emmc_rx_cmd_data_cntl1 != 0) |
| 720 | silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1; |
| 721 | if (cfg->emmc_rx_strobe_cntl != 0) |
| 722 | silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; |
| 723 | if (cfg->emmc_rx_cmd_data_cntl2 != 0) |
| 724 | silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; |
Mario Scheithauer | 9116eb6 | 2018-08-23 11:39:19 +0200 | [diff] [blame] | 725 | if (cfg->emmc_host_max_speed != 0) |
| 726 | silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed; |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 727 | |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 728 | silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; |
| 729 | |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 730 | /* Disable monitor mwait since it is broken due to a hardware bug |
Cole Nelson | f357c25 | 2017-05-16 11:38:59 -0700 | [diff] [blame] | 731 | * without a fix. Specific to Apollolake. |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 732 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 733 | if (!CONFIG(SOC_INTEL_GLK)) |
Cole Nelson | f357c25 | 2017-05-16 11:38:59 -0700 | [diff] [blame] | 734 | silconfig->MonitorMwaitEnable = 0; |
Bora Guvendik | 60cc75d | 2016-07-25 14:44:51 -0700 | [diff] [blame] | 735 | |
Subrata Banik | f699c14 | 2018-06-08 17:57:37 +0530 | [diff] [blame] | 736 | silconfig->SkipMpInit = !chip_get_fsp_mp_init(); |
Venkateswarlu Vinjamuri | 1a5e32c | 2016-10-31 17:15:30 -0700 | [diff] [blame] | 737 | |
Furquan Shaikh | cad9b63 | 2016-06-20 16:08:42 -0700 | [diff] [blame] | 738 | /* Disable setting of EISS bit in FSP. */ |
| 739 | silconfig->SpiEiss = 0; |
Ravi Sarawadi | 3a21d0f | 2016-08-10 11:33:56 -0700 | [diff] [blame] | 740 | |
| 741 | /* Disable FSP from locking access to the RTC NVRAM */ |
| 742 | silconfig->RtcLock = 0; |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 743 | |
| 744 | /* Enable Audio clk gate and power gate */ |
| 745 | silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; |
| 746 | silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; |
| 747 | /* Bios config lockdown Audio clk and power gate */ |
| 748 | silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 749 | if (CONFIG(SOC_INTEL_GLK)) |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 750 | glk_fsp_silicon_init_params_cb(cfg, silconfig); |
| 751 | else |
| 752 | apl_fsp_silicon_init_params_cb(cfg, silconfig); |
Duncan Laurie | 4c8fbc0 | 2018-03-26 02:19:58 -0700 | [diff] [blame] | 753 | |
| 754 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
| 755 | dev = dev_find_slot(0, PCH_DEVFN_XDCI); |
| 756 | if (!xdci_can_enable()) |
| 757 | dev->enabled = 0; |
| 758 | silconfig->UsbOtg = dev->enabled; |
Werner Zeh | 279afdc | 2019-02-01 12:32:51 +0100 | [diff] [blame] | 759 | |
| 760 | /* Set VTD feature according to devicetree */ |
| 761 | silconfig->VtdEnable = cfg->enable_vtd; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 762 | } |
| 763 | |
| 764 | struct chip_operations soc_intel_apollolake_ops = { |
| 765 | CHIP_NAME("Intel Apollolake SOC") |
John Zhao | 57aa8b6 | 2019-01-14 09:15:50 -0800 | [diff] [blame] | 766 | .enable_dev = &enable_dev, |
| 767 | .init = &soc_init, |
| 768 | .final = &soc_final |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 769 | }; |
| 770 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 771 | static void drop_privilege_all(void) |
| 772 | { |
| 773 | /* Drop privilege level on all the CPUs */ |
Subrata Banik | 3337497 | 2018-04-24 13:45:30 +0530 | [diff] [blame] | 774 | if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, NULL, 1000) < 0) |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 775 | printk(BIOS_ERR, "failed to enable untrusted mode\n"); |
| 776 | } |
| 777 | |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 778 | static void configure_xhci_host_mode_port0(void) |
| 779 | { |
| 780 | uint32_t *cfg0; |
| 781 | uint32_t *cfg1; |
| 782 | const struct resource *res; |
| 783 | uint32_t reg; |
| 784 | struct stopwatch sw; |
| 785 | struct device *xhci_dev = PCH_DEV_XHCI; |
| 786 | |
| 787 | printk(BIOS_INFO, "Putting xHCI port 0 into host mode.\n"); |
| 788 | res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); |
| 789 | cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); |
| 790 | cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); |
| 791 | reg = read32(cfg0); |
John Zhao | db2f91b | 2018-08-21 15:02:54 -0700 | [diff] [blame] | 792 | if (!(reg & SW_IDPIN_EN_MASK)) |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 793 | return; |
| 794 | |
| 795 | reg &= ~(SW_IDPIN_MASK | SW_VBUS_VALID_MASK); |
| 796 | write32(cfg0, reg); |
| 797 | |
| 798 | stopwatch_init_msecs_expire(&sw, 10); |
| 799 | /* Wait for the host mode status bit. */ |
| 800 | while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { |
| 801 | if (stopwatch_expired(&sw)) { |
| 802 | printk(BIOS_ERR, "Timed out waiting for host mode.\n"); |
| 803 | return; |
| 804 | } |
| 805 | } |
| 806 | |
| 807 | printk(BIOS_INFO, "xHCI port 0 host switch over took %lu ms\n", |
| 808 | stopwatch_duration_msecs(&sw)); |
| 809 | } |
| 810 | |
| 811 | static int check_xdci_enable(void) |
| 812 | { |
| 813 | struct device *dev = PCH_DEV_XDCI; |
| 814 | |
| 815 | return !!dev->enabled; |
| 816 | } |
| 817 | |
Lee Leahy | 806fa24 | 2016-08-01 13:55:02 -0700 | [diff] [blame] | 818 | void platform_fsp_notify_status(enum fsp_notify_phase phase) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 819 | { |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 820 | if (phase == END_OF_FIRMWARE) { |
Furquan Shaikh | d2c2f83 | 2018-11-07 10:24:31 -0800 | [diff] [blame] | 821 | |
| 822 | /* |
| 823 | * Before hiding P2SB device and dropping privilege level, |
| 824 | * dump CSE status and disable HECI1 interface. |
| 825 | */ |
| 826 | heci_cse_lockdown(); |
| 827 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 828 | /* Hide the P2SB device to align with previous behavior. */ |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 829 | p2sb_hide(); |
Furquan Shaikh | d2c2f83 | 2018-11-07 10:24:31 -0800 | [diff] [blame] | 830 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 831 | /* |
| 832 | * As per guidelines BIOS is recommended to drop CPU privilege |
| 833 | * level to IA_UNTRUSTED. After that certain device registers |
| 834 | * and MSRs become inaccessible supposedly increasing system |
| 835 | * security. |
| 836 | */ |
| 837 | drop_privilege_all(); |
John Zhao | 7dff726 | 2018-07-30 13:54:25 -0700 | [diff] [blame] | 838 | |
| 839 | /* |
| 840 | * When USB OTG is set, GLK FSP enables xHCI SW ID pin and |
| 841 | * configures USB-C as device mode. Force USB-C into host mode. |
| 842 | */ |
| 843 | if (check_xdci_enable()) |
| 844 | configure_xhci_host_mode_port0(); |
John Zhao | 57aa8b6 | 2019-01-14 09:15:50 -0800 | [diff] [blame] | 845 | |
| 846 | /* |
| 847 | * Override GLK xhci clock gating register(XHCLKGTEN) to |
| 848 | * mitigate usb device suspend and resume failure. |
| 849 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 850 | if (CONFIG(SOC_INTEL_GLK)) { |
John Zhao | 57aa8b6 | 2019-01-14 09:15:50 -0800 | [diff] [blame] | 851 | uint32_t *cfg; |
| 852 | const struct resource *res; |
| 853 | uint32_t reg; |
| 854 | struct device *xhci_dev = PCH_DEV_XHCI; |
| 855 | |
| 856 | res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); |
| 857 | cfg = (void *)(uintptr_t)(res->base + CFG_XHCLKGTEN); |
| 858 | reg = SRAMPGTEN | SSLSE | USB2PLLSE | IOSFSTCGE | |
| 859 | HSTCGE | HSUXDMIPLLSE | SSTCGE | XHCFTCLKSE | |
| 860 | XHCBBTCGIPISO | XHCUSB2PLLSDLE | SSPLLSUE | |
| 861 | XHCBLCGE | HSLTCGE | SSLTCGE | IOSFBTCGE | |
| 862 | IOSFGBLCGE; |
| 863 | write32(cfg, reg); |
| 864 | } |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 865 | } |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 866 | } |
| 867 | |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 868 | /* |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 869 | * spi_flash init() needs to run unconditionally on every boot (including |
| 870 | * resume) to allow write protect to be disabled for eventlog and nvram |
| 871 | * updates. This needs to be done as early as possible in ramstage. Thus, add a |
| 872 | * callback for entry into BS_PRE_DEVICE. |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 873 | */ |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 874 | static void spi_flash_init_cb(void *unused) |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 875 | { |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 876 | fast_spi_init(); |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 877 | } |
| 878 | |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 879 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); |