Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame^] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <bootstate.h> |
| 20 | #include <console/console.h> |
| 21 | #include <cpu/cpu.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <fsp/api.h> |
| 25 | #include <fsp/util.h> |
| 26 | #include <memrange.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 27 | #include <soc/iomap.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 28 | #include <soc/cpu.h> |
| 29 | #include <soc/pci_devs.h> |
| 30 | |
| 31 | #include "chip.h" |
| 32 | |
| 33 | static void pci_domain_set_resources(device_t dev) |
| 34 | { |
| 35 | assign_resources(dev->link_list); |
| 36 | } |
| 37 | |
| 38 | static struct device_operations pci_domain_ops = { |
| 39 | .read_resources = pci_domain_read_resources, |
| 40 | .set_resources = pci_domain_set_resources, |
| 41 | .enable_resources = NULL, |
| 42 | .init = NULL, |
| 43 | .scan_bus = pci_domain_scan_bus, |
| 44 | .ops_pci_bus = pci_bus_default_ops, |
| 45 | }; |
| 46 | |
| 47 | static struct device_operations cpu_bus_ops = { |
| 48 | .read_resources = DEVICE_NOOP, |
| 49 | .set_resources = DEVICE_NOOP, |
| 50 | .enable_resources = DEVICE_NOOP, |
| 51 | .init = apollolake_init_cpus, |
| 52 | .scan_bus = NULL, |
| 53 | }; |
| 54 | |
| 55 | static void enable_dev(device_t dev) |
| 56 | { |
| 57 | /* Set the operations if it is a special bus type */ |
| 58 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 59 | dev->ops = &pci_domain_ops; |
| 60 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 61 | dev->ops = &cpu_bus_ops; |
| 62 | } |
| 63 | } |
| 64 | |
| 65 | static void soc_init(void *data) |
| 66 | { |
| 67 | struct range_entry range; |
| 68 | |
| 69 | /* TODO: tigten this resource range */ |
| 70 | /* TODO: fix for S3 resume, as this would corrupt OS memory */ |
| 71 | range_entry_init(&range, 0x200000, 4ULL*GiB, 0); |
| 72 | fsp_silicon_init(&range); |
| 73 | } |
| 74 | |
| 75 | void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) |
| 76 | { |
| 77 | struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
| 78 | static struct soc_intel_apollolake_config *cfg; |
| 79 | |
| 80 | /* Load VBT before devicetree-specific config. */ |
| 81 | silconfig->GraphicsConfigPtr = fsp_load_vbt(); |
| 82 | |
| 83 | struct device *dev = NB_DEV_ROOT; |
| 84 | if (!dev && !dev->chip_info) { |
| 85 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 86 | return; |
| 87 | } |
| 88 | |
| 89 | cfg = dev->chip_info; |
| 90 | |
| 91 | silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; |
| 92 | silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; |
| 93 | silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; |
| 94 | silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; |
| 95 | silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; |
| 96 | silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 97 | |
| 98 | /* Our defaults may not match FSP defaults, so set them explicitly */ |
| 99 | silconfig->AcpiBase = ACPI_PMIO_BASE; |
| 100 | /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ |
| 101 | silconfig->PmcBase = PMC_BAR0 + 0x1000; |
| 102 | silconfig->P2sbBase = P2SB_BAR; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | struct chip_operations soc_intel_apollolake_ops = { |
| 106 | CHIP_NAME("Intel Apollolake SOC") |
| 107 | .enable_dev = &enable_dev, |
| 108 | .init = &soc_init |
| 109 | }; |
| 110 | |
| 111 | static void fsp_notify_dummy(void *arg) |
| 112 | { |
| 113 | |
| 114 | enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; |
| 115 | |
| 116 | if (fsp_notify(ph) != FSP_SUCCESS) |
| 117 | printk(BIOS_CRIT, "FspNotify failed!\n"); |
| 118 | } |
| 119 | |
| 120 | BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, |
| 121 | (void *) AFTER_PCI_ENUM); |
| 122 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, |
| 123 | (void *) READY_TO_BOOT); |
| 124 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, |
| 125 | (void *) READY_TO_BOOT); |