src/soc/intel/skylake/Kconfig

config SOC_INTEL_COMMON_SKYLAKE_BASE
	bool

config SOC_INTEL_SKYLAKE
	bool
	select SOC_INTEL_COMMON_SKYLAKE_BASE

config SOC_INTEL_KABYLAKE
	bool
	select SOC_INTEL_COMMON_SKYLAKE_BASE

config SOC_INTEL_SKYLAKE_LGA1151_V2
	bool
	select PLATFORM_USES_FSP2_1
	select SOC_INTEL_COMMON_SKYLAKE_BASE
	select SKYLAKE_SOC_PCH_H
	help
	  Selected by mainboards with a LGA1151 v2 socket and a Z370, H310C or B365 PCH

if SOC_INTEL_COMMON_SKYLAKE_BASE

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select ACPI_NHLT
	select ARCH_X86
	select BOOT_DEVICE_SUPPORTS_WRITES
	select CACHE_MRC_SETTINGS
	select CPU_INTEL_COMMON
	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
	select CPU_SUPPORTS_PM_TIMER_EMULATION
	select FSP_COMPRESS_FSP_S_LZ4
	select FSP_M_XIP
	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
	select GENERIC_GPIO_LIB
	select HAVE_FSP_GOP
	select HAVE_FSP_LOGO_SUPPORT
	select HAVE_INTEL_FSP_REPO
	select INTEL_CAR_NEM_ENHANCED
	select HAVE_SMI_HANDLER
	select INTEL_DESCRIPTOR_MODE_CAPABLE
	select INTEL_GMA_ACPI
	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
	select MRC_SETTINGS_PROTECT
	select PARALLEL_MP_AP_WORK
	select PLATFORM_USES_FSP2_0
	select PMC_GLOBAL_RESET_ENABLE_LOCK
	select SA_ENABLE_DPR
	select SOC_INTEL_COMMON
	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
	select SOC_INTEL_COMMON_BLOCK
	select SOC_INTEL_COMMON_BLOCK_ACPI
	select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
	select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
	select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
	select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
	select SOC_INTEL_COMMON_BLOCK_CAR
	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
	select SOC_INTEL_COMMON_BLOCK_CPU
	select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
	select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
	select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
	select SOC_INTEL_COMMON_BLOCK_GSPI
	select SOC_INTEL_COMMON_BLOCK_HDA
	select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
	select SOC_INTEL_COMMON_BLOCK_SA
	select SOC_INTEL_COMMON_BLOCK_SCS
	select SOC_INTEL_COMMON_BLOCK_SGX
	select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
	select SOC_INTEL_COMMON_BLOCK_SMM
	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
	select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV
	select SOC_INTEL_COMMON_BLOCK_UART
	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
	select SOC_INTEL_COMMON_FSP_RESET
	select SOC_INTEL_COMMON_PCH_BASE
	select SOC_INTEL_COMMON_NHLT
	select SOC_INTEL_COMMON_RESET
	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
	select SSE2
	select SUPPORT_CPU_UCODE_IN_CBFS
	select TSC_MONOTONIC_TIMER
	select TSC_SYNC_MFENCE
	select UDELAY_TSC
	select UDK_2015_BINDING

config MAX_CPUS
	int
	default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU
	default 8

config FSP_HYPERTHREADING
	bool "Enable Hyper-Threading"
	default y

config ENABLE_SATA_TEST_MODE
	bool "Enable SATA test mode"
	default n
	help
	  Enable SATA test mode in FSP-S.

config CPU_INTEL_NUM_FIT_ENTRIES
	int
	default 10

config VBOOT
	select VBOOT_SEPARATE_VERSTAGE
	select VBOOT_MUST_REQUEST_DISPLAY
	select VBOOT_STARTS_IN_BOOTBLOCK
	select VBOOT_VBNV_CMOS
	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH

config CBFS_SIZE
	default 0x200000

config DCACHE_RAM_BASE
	hex
	default 0xfef00000

config DCACHE_RAM_SIZE
	hex
	default 0x40000
	help
	  The size of the cache-as-ram region required during bootblock
	  and/or romstage.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0x20400 if FSP_USES_CB_STACK
	default 0x4000
	help
	  The amount of anticipated stack usage in CAR by bootblock and
	  other stages.

config FSP_TEMP_RAM_SIZE
	hex
	depends on FSP_USES_CB_STACK
	default 0x10000
	help
	  The amount of anticipated heap usage in CAR by FSP.
	  Refer to Platform FSP integration guide document to know
	  the exact FSP requirement for Heap setup.

config EXCLUDE_NATIVE_SD_INTERFACE
	bool
	default n
	help
	  If you set this option to n, will not use native SD controller.

config HEAP_SIZE
	hex
	default 0x80000

config IED_REGION_SIZE
	hex
	default 0x400000

config PCR_BASE_ADDRESS
	hex
	default 0xfd000000
	help
	  This option allows you to select MMIO Base Address of sideband bus.

config SMM_RESERVED_SIZE
	hex
	default 0x200000

config SMM_TSEG_SIZE
	hex
	default 0x800000

config VGA_BIOS_ID
	string
	default "8086,0406"

config SKYLAKE_SOC_PCH_H
	bool
	default n

config NHLT_DMIC_1CH
	bool
	default n
	help
	  Include DSP firmware settings for 1 channel DMIC array.

config NHLT_DMIC_2CH
	bool
	default n
	help
	  Include DSP firmware settings for 2 channel DMIC array.

config NHLT_DMIC_4CH
	bool
	default n
	help
	  Include DSP firmware settings for 4 channel DMIC array.

config NHLT_NAU88L25
	bool
	default n
	help
	  Include DSP firmware settings for nau88l25 headset codec.

config NHLT_MAX98357
	bool
	default n
	help
	  Include DSP firmware settings for max98357 amplifier.

config NHLT_MAX98373
	bool
	default n
	help
	  Include DSP firmware settings for max98373 amplifier.

config NHLT_SSM4567
	bool
	default n
	help
	  Include DSP firmware settings for ssm4567 smart amplifier.

config NHLT_RT5514
	bool
	default n
	help
	  Include DSP firmware settings for rt5514 DSP.

config NHLT_RT5663
	bool
	default n
	help
	  Include DSP firmware settings for rt5663 headset codec.

config NHLT_MAX98927
	bool
	default n
	help
	  Include DSP firmware settings for max98927 amplifier.

config NHLT_DA7219
	bool
	default n
	help
	  Include DSP firmware settings for DA7219 headset codec.

# Use KabylakeFsp for both Skylake and Kabylake as it supports both.
# SkylakeFsp is FSP 1.1 and therefore incompatible.
config FSP_HEADER_PATH
	default "3rdparty/fsp/AmberLakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE_LGA1151_V2
	default "3rdparty/fsp/KabylakeFspBinPkg/Include/"

config FSP_FD_PATH
	default "3rdparty/fsp/AmberLakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE_LGA1151_V2
	default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"

config MAX_ROOT_PORTS
	int
	default 24

config NO_FADT_8042
	bool
	default n
	help
	  Choose this option if you want to disable 8042 Keyboard

config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
	int
	default 120

config CPU_XTAL_HZ
	default 24000000

config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
	int
	default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ

config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
	int
	default 2

config SOC_INTEL_I2C_DEV_MAX
	int
	default 6

config CPU_BCLK_MHZ
	int
	default 100

config CONSOLE_UART_BASE_ADDRESS
	hex
	default 0xfe030000
	depends on INTEL_LPSS_UART_FOR_CONSOLE

# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
	hex
	default 0x30

config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
	hex
	default 0xc35

config CHIPSET_DEVICETREE
	string
	default "soc/intel/skylake/chipset.cb"

config IFD_CHIPSET
	string
	default "sklkbl"

config INTEL_TXT_BIOSACM_ALIGNMENT
	hex
	default 0x40000 # 256KB

config MAINBOARD_SUPPORTS_SKYLAKE_CPU
	bool "Board can contain Skylake CPU"
	default !SOC_INTEL_SKYLAKE_LGA1151_V2

if SKYLAKE_SOC_PCH_H

config MAINBOARD_SUPPORTS_KABYLAKE_CPU
	bool "Board can contain Kaby Lake CPU"
	default !SOC_INTEL_SKYLAKE_LGA1151_V2 && SOC_INTEL_KABYLAKE

config MAINBOARD_SUPPORTS_COFFEELAKE_CPU
	bool "Board can contain Coffee Lake CPU"
	default y if SOC_INTEL_SKYLAKE_LGA1151_V2

endif

if !SKYLAKE_SOC_PCH_H

config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
	bool "Board can contain Kaby Lake DUAL core"
	default y

config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
	bool "Board can contain Kaby Lake QUAD core"
	default y

endif

endif