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review.coreboot.org / coreboot / 756f51b66257a5af7789c06156217d6f0319b457 / . / src / soc / intel / skylake / Kconfig
blob: bd4c13e0a74510a83130cf5cebadbee0c0f5e87d [file] [log] [blame]
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]1config SOC_INTEL_COMMON_SKYLAKE_BASE
2 bool
3
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]4config SOC_INTEL_SKYLAKE
5 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]6 select SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]7 help
8 Intel Skylake support
9
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]10config SOC_INTEL_KABYLAKE
11 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]12 select SOC_INTEL_COMMON_SKYLAKE_BASE
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]13 help
14 Intel Kabylake support
15
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]16config SOC_INTEL_SKYLAKE_LGA1151_V2
17 bool
18 select PLATFORM_USES_FSP2_1
19 select SOC_INTEL_COMMON_SKYLAKE_BASE
20 select SKYLAKE_SOC_PCH_H
21 help
22 Selected by mainboards with a LGA1151 v2 socket and a Z370, H310C or B365 PCH
23
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]24if SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]25
26config CPU_SPECIFIC_OPTIONS
27 def_bool y
Aaron Durbine0a49142016-07-13 23:20:51 -0500[diff] [blame]28 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]29 select ACPI_NHLT
Angel Ponsa32df262020-09-25 10:20:11 +0200[diff] [blame]30 select ARCH_ALL_STAGES_X86_32
Aaron Durbine8e118d2016-08-12 15:00:10 -0500[diff] [blame]31 select BOOT_DEVICE_SUPPORTS_WRITES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]32 select CACHE_MRC_SETTINGS
Nico Huber6275e342018-11-21 00:11:35 +0100[diff] [blame]33 select CPU_INTEL_COMMON
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]34 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhnerfe6070f2020-10-04 15:16:04 +0200[diff] [blame]35 select CPU_SUPPORTS_PM_TIMER_EMULATION
Benjamin Doron27af8da2021-02-26 04:36:05 +0000[diff] [blame]36 select FSP_COMPRESS_FSP_S_LZ4
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]37 select FSP_M_XIP
Subrata Banik4ed9f9a2020-10-31 22:01:55 +0530[diff] [blame]38 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
Aaron Durbinffdf9012015-07-24 13:00:36 -0500[diff] [blame]39 select GENERIC_GPIO_LIB
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]40 select HAVE_FSP_GOP
Wim Vervoornd1371502019-12-17 14:10:16 +0100[diff] [blame]41 select HAVE_FSP_LOGO_SUPPORT
Felix Singerbd7020d2020-12-06 11:32:25 +0100[diff] [blame]42 select HAVE_INTEL_FSP_REPO
Shreesh Chhabbi87c7ec72020-12-03 14:07:15 -0800[diff] [blame]43 select INTEL_CAR_NEM_ENHANCED
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]44 select HAVE_SMI_HANDLER
Felix Singerbd7020d2020-12-06 11:32:25 +0100[diff] [blame]45 select INTEL_DESCRIPTOR_MODE_CAPABLE
Patrick Rudolphc7edf182017-09-26 19:34:35 +0200[diff] [blame]46 select INTEL_GMA_ACPI
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]47 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]48 select IOAPIC
Duncan Laurie205ed2d2016-06-02 15:23:42 -0700[diff] [blame]49 select MRC_SETTINGS_PROTECT
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]50 select PARALLEL_MP
Furquan Shaikha5853582017-05-06 12:40:15 -0700[diff] [blame]51 select PARALLEL_MP_AP_WORK
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]52 select PLATFORM_USES_FSP2_0
Michael Niewöhnera1843d82020-10-02 18:28:22 +0200[diff] [blame]53 select PM_ACPI_TIMER_OPTIONAL
Julien Viard de Galbert2912e8e2018-08-14 16:15:26 +0200[diff] [blame]54 select PMC_GLOBAL_RESET_ENABLE_LOCK
Felix Singerbd7020d2020-12-06 11:32:25 +0100[diff] [blame]55 select REG_SCRIPT
56 select SA_ENABLE_DPR
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]57 select SOC_INTEL_COMMON
Duncan Lauriea1c8b34d2015-09-08 16:12:44 -0700[diff] [blame]58 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banike074d622017-02-16 16:16:37 +0530[diff] [blame]59 select SOC_INTEL_COMMON_BLOCK
Angel Pons98f672a2021-02-19 19:42:10 +0100[diff] [blame]60 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
Michael Niewöhner11fae4f2021-01-01 21:23:52 +0100[diff] [blame]61 select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
Nico Huber2f1ef982018-11-07 16:24:50 +0100[diff] [blame]62 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]63 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Barnali Sarkar0a203d12017-05-04 18:02:17 +0530[diff] [blame]64 select SOC_INTEL_COMMON_BLOCK_CPU
Barnali Sarkar73273862017-06-13 20:22:33 +0530[diff] [blame]65 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Angel Ponsa4cd9112021-02-19 19:23:38 +0100[diff] [blame]66 select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
Furquan Shaikh2c368892018-10-18 16:22:37 -0700[diff] [blame]67 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]68 select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]69 select SOC_INTEL_COMMON_BLOCK_GSPI
Furquan Shaikh31bff012018-09-29 23:31:04 -0700[diff] [blame]70 select SOC_INTEL_COMMON_BLOCK_HDA
Arthur Heymans1ae8cd12020-11-19 13:59:53 +0100[diff] [blame]71 select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
Subrata Banik93ebe492017-03-14 18:24:47 +0530[diff] [blame]72 select SOC_INTEL_COMMON_BLOCK_SA
Duncan Laurie1e066112020-04-08 11:35:52 -0700[diff] [blame]73 select SOC_INTEL_COMMON_BLOCK_SCS
Pratik Prajapatia04aa3d2017-06-12 23:02:36 -0700[diff] [blame]74 select SOC_INTEL_COMMON_BLOCK_SGX
Michael Niewöhnerc169a472019-10-31 19:01:23 +0100[diff] [blame]75 select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
Subrata Banikece173c2017-12-14 18:18:34 +0530[diff] [blame]76 select SOC_INTEL_COMMON_BLOCK_SMM
77 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banik2fff3912020-01-16 10:13:28 +0530[diff] [blame]78 select SOC_INTEL_COMMON_BLOCK_THERMAL
Subrata Banikafa07f72018-05-24 12:21:06 +0530[diff] [blame]79 select SOC_INTEL_COMMON_BLOCK_UART
Karthikeyan Ramasubramaniancc7cdb12019-03-20 11:38:01 -0600[diff] [blame]80 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Subrata Banik4ed9f9a2020-10-31 22:01:55 +0530[diff] [blame]81 select SOC_INTEL_COMMON_FSP_RESET
Subrata Banikf513ceb2018-05-17 15:57:43 +0530[diff] [blame]82 select SOC_INTEL_COMMON_PCH_BASE
Aaron Durbinc14a1a92016-06-28 15:41:07 -0500[diff] [blame]83 select SOC_INTEL_COMMON_NHLT
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]84 select SOC_INTEL_COMMON_RESET
Sumeet R Pawnikar97c54642020-05-10 01:24:11 +0530[diff] [blame]85 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
Nico Huberdd274e22020-04-26 20:37:32 +0200[diff] [blame]86 select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]87 select SSE2
88 select SUPPORT_CPU_UCODE_IN_CBFS
Aamir Bohra842776e2017-05-25 14:12:01 +0530[diff] [blame]89 select TSC_MONOTONIC_TIMER
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]90 select TSC_SYNC_MFENCE
91 select UDELAY_TSC
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]92 select UDK_2015_BINDING
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]93
Felix Singer9a6a18e2021-01-04 22:10:26 +0000[diff] [blame]94config MAX_CPUS
95 int
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]96 default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU
Felix Singer9a6a18e2021-01-04 22:10:26 +0000[diff] [blame]97 default 8
98
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]99config FSP_HYPERTHREADING
100 bool "Enable Hyper-Threading"
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]101 default y
102
Angel Pons8f3e1192021-04-04 16:20:54 +0200[diff] [blame]103config ENABLE_SATA_TEST_MODE
104 bool "Enable SATA test mode"
105 default n
106 help
107 Enable SATA test mode in FSP-S.
108
Arthur Heymans27d3f712018-01-05 17:51:46 +0100[diff] [blame]109config CPU_INTEL_NUM_FIT_ENTRIES
110 int
111 default 10
112
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]113config VBOOT
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]114 select VBOOT_SEPARATE_VERSTAGE
Joel Kitching6672bd82019-04-10 16:06:21 +0800[diff] [blame]115 select VBOOT_MUST_REQUEST_DISPLAY
Aaron Durbina6914d22016-08-24 08:49:29 -0500[diff] [blame]116 select VBOOT_STARTS_IN_BOOTBLOCK
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -0700[diff] [blame]117 select VBOOT_VBNV_CMOS
118 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]119
Martin Roth59ff3402016-02-09 09:06:46 -0700[diff] [blame]120config CBFS_SIZE
121 hex
122 default 0x200000
123
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]124config DCACHE_RAM_BASE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]125 hex
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]126 default 0xfef00000
127
128config DCACHE_RAM_SIZE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]129 hex
Rizwan Qureshi3ad63562016-08-14 15:48:33 +0530[diff] [blame]130 default 0x40000
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]131 help
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]132 The size of the cache-as-ram region required during bootblock
133 and/or romstage.
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]134
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]135config DCACHE_BSP_STACK_SIZE
136 hex
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]137 default 0x20400 if FSP_USES_CB_STACK
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]138 default 0x4000
139 help
140 The amount of anticipated stack usage in CAR by bootblock and
141 other stages.
142
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]143config FSP_TEMP_RAM_SIZE
144 hex
145 depends on FSP_USES_CB_STACK
146 default 0x10000
147 help
148 The amount of anticipated heap usage in CAR by FSP.
149 Refer to Platform FSP integration guide document to know
150 the exact FSP requirement for Heap setup.
151
Subrata Banik086730b2015-12-02 11:42:04 +0530[diff] [blame]152config EXCLUDE_NATIVE_SD_INTERFACE
153 bool
154 default n
155 help
156 If you set this option to n, will not use native SD controller.
157
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]158config HEAP_SIZE
159 hex
160 default 0x80000
161
162config IED_REGION_SIZE
163 hex
164 default 0x400000
165
Subrata Banike7ceae72017-03-08 17:59:40 +0530[diff] [blame]166config PCR_BASE_ADDRESS
167 hex
168 default 0xfd000000
169 help
170 This option allows you to select MMIO Base Address of sideband bus.
171
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]172config SMM_RESERVED_SIZE
173 hex
174 default 0x200000
175
176config SMM_TSEG_SIZE
177 hex
178 default 0x800000
179
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]180config VGA_BIOS_ID
181 string
182 default "8086,0406"
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]183
Teo Boon Tiong2fc06c82016-09-15 11:11:45 +0800[diff] [blame]184config SKYLAKE_SOC_PCH_H
185 bool
186 default n
187 help
188 Choose this option if you have a PCH-H chipset.
189
Benjamin Doroneecaf362020-08-04 06:45:46 +0000[diff] [blame]190config NHLT_DMIC_1CH
191 bool
192 default n
193 help
194 Include DSP firmware settings for 1 channel DMIC array.
195
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]196config NHLT_DMIC_2CH
197 bool
198 default n
199 help
200 Include DSP firmware settings for 2 channel DMIC array.
201
202config NHLT_DMIC_4CH
203 bool
204 default n
205 help
206 Include DSP firmware settings for 4 channel DMIC array.
207
208config NHLT_NAU88L25
209 bool
210 default n
211 help
212 Include DSP firmware settings for nau88l25 headset codec.
213
214config NHLT_MAX98357
215 bool
216 default n
217 help
218 Include DSP firmware settings for max98357 amplifier.
219
Duncan Lauriee6c8a382018-03-26 02:45:02 -0700[diff] [blame]220config NHLT_MAX98373
221 bool
222 default n
223 help
224 Include DSP firmware settings for max98373 amplifier.
225
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]226config NHLT_SSM4567
227 bool
228 default n
229 help
230 Include DSP firmware settings for ssm4567 smart amplifier.
231
Duncan Laurie4a75a662017-03-02 10:13:51 -0800[diff] [blame]232config NHLT_RT5514
233 bool
234 default n
235 help
236 Include DSP firmware settings for rt5514 DSP.
237
Rizwan Qureshi17335fa2017-01-14 06:08:21 +0530[diff] [blame]238config NHLT_RT5663
239 bool
240 default n
241 help
242 Include DSP firmware settings for rt5663 headset codec.
243
244config NHLT_MAX98927
245 bool
246 default n
247 help
248 Include DSP firmware settings for max98927 amplifier.
249
Naveen Manohar83670c52017-11-04 02:55:09 +0530[diff] [blame]250config NHLT_DA7219
251 bool
252 default n
253 help
254 Include DSP firmware settings for DA7219 headset codec.
255
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]256# Use KabylakeFsp for both Skylake and Kabylake as it supports both.
257# SkylakeFsp is FSP 1.1 and therefore incompatible.
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]258config FSP_HEADER_PATH
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]259 default "3rdparty/fsp/AmberLakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE_LGA1151_V2
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]260 default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]261
262config FSP_FD_PATH
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]263 default "3rdparty/fsp/AmberLakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE_LGA1151_V2
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]264 default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]265
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]266config MAX_ROOT_PORTS
267 int
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]268 default 24
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]269
Jenny TC2864f852017-02-09 16:01:59 +0530[diff] [blame]270config NO_FADT_8042
271 bool
272 default n
273 help
274 Choose this option if you want to disable 8042 Keyboard
275
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]276config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Furquan Shaikh340908a2017-04-04 11:47:19 -0700[diff] [blame]277 int
278 default 120
279
Michael Niewöhnerdadcbfb2020-10-04 14:48:05 +0200[diff] [blame]280config CPU_XTAL_HZ
281 default 24000000
282
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]283config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
284 int
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]285 default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]286
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]287config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
288 int
289 default 2
290
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]291config SOC_INTEL_I2C_DEV_MAX
292 int
293 default 6
294
Aamir Bohra1041d392017-06-02 11:56:14 +0530[diff] [blame]295config CPU_BCLK_MHZ
296 int
297 default 100
298
Nico Huber99954182019-05-29 23:33:06 +0200[diff] [blame]299config CONSOLE_UART_BASE_ADDRESS
300 hex
301 default 0xfe030000
302 depends on INTEL_LPSS_UART_FOR_CONSOLE
303
Furquan Shaikh3406dd62017-08-04 15:58:26 -0700[diff] [blame]304# Clock divider parameters for 115200 baud rate
305config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
306 hex
307 default 0x30
308
309config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
310 hex
311 default 0xc35
312
Felix Singer424467c2020-10-12 19:51:02 +0000[diff] [blame]313config CHIPSET_DEVICETREE
314 string
315 default "soc/intel/skylake/chipset.cb"
316
Furquan Shaikha3ad9902018-03-21 10:45:08 -0700[diff] [blame]317config IFD_CHIPSET
318 string
319 default "sklkbl"
320
Patrick Rudolph5fffb5e2019-07-25 11:55:30 +0200[diff] [blame]321config INTEL_TXT_BIOSACM_ALIGNMENT
322 hex
323 default 0x40000 # 256KB
324
Wim Vervoorn2ab4f4b2019-10-23 10:22:06 +0200[diff] [blame]325config MAINBOARD_SUPPORTS_SKYLAKE_CPU
326 bool "Board can contain Skylake CPU"
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]327 default !SOC_INTEL_SKYLAKE_LGA1151_V2
Wim Vervoorn2ab4f4b2019-10-23 10:22:06 +0200[diff] [blame]328
329if SKYLAKE_SOC_PCH_H
330
331config MAINBOARD_SUPPORTS_KABYLAKE_CPU
332 bool "Board can contain Kaby Lake CPU"
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]333 default !SOC_INTEL_SKYLAKE_LGA1151_V2 && SOC_INTEL_KABYLAKE
Wim Vervoorn2ab4f4b2019-10-23 10:22:06 +0200[diff] [blame]334
Timofey Komarov7e7d27b2021-04-27 11:00:10 +0300[diff] [blame]335config MAINBOARD_SUPPORTS_COFFEELAKE_CPU
336 bool "Board can contain Coffee Lake CPU"
Timofey Komarov756f51b2021-04-27 10:54:34 +0300[diff] [blame^]337 default y if SOC_INTEL_SKYLAKE_LGA1151_V2
Timofey Komarov7e7d27b2021-04-27 11:00:10 +0300[diff] [blame]338
Wim Vervoorn2ab4f4b2019-10-23 10:22:06 +0200[diff] [blame]339endif
340
341if !SKYLAKE_SOC_PCH_H
342
343config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
344 bool "Board can contain Kaby Lake DUAL core"
345 default y
346
347config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
348 bool "Board can contain Kaby Lake QUAD core"
349 default y
350
351endif
352
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]353endif