Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 87c7ec7c0677ec5fda4a9cebb95c06edb23a96ba / . / src / soc / intel / skylake / Kconfig
blob: cfc7c5239c60a6f379c694e59354774789530928 [file] [log] [blame]
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]1config SOC_INTEL_COMMON_SKYLAKE_BASE
2 bool
3
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]4config SOC_INTEL_SKYLAKE
5 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]6 select SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]7 help
8 Intel Skylake support
9
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]10config SOC_INTEL_KABYLAKE
11 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]12 select SOC_INTEL_COMMON_SKYLAKE_BASE
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]13 help
14 Intel Kabylake support
15
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]16if SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]17
18config CPU_SPECIFIC_OPTIONS
19 def_bool y
Aaron Durbine0a49142016-07-13 23:20:51 -0500[diff] [blame]20 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]21 select ACPI_NHLT
Angel Ponsa32df262020-09-25 10:20:11 +0200[diff] [blame]22 select ARCH_ALL_STAGES_X86_32
Aaron Durbine8e118d2016-08-12 15:00:10 -0500[diff] [blame]23 select BOOT_DEVICE_SUPPORTS_WRITES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]24 select CACHE_MRC_SETTINGS
Nico Huber6275e342018-11-21 00:11:35 +0100[diff] [blame]25 select CPU_INTEL_COMMON
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]26 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhnerfe6070f2020-10-04 15:16:04 +0200[diff] [blame]27 select CPU_SUPPORTS_PM_TIMER_EMULATION
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]28 select FSP_M_XIP
Subrata Banik4ed9f9a2020-10-31 22:01:55 +0530[diff] [blame]29 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
Aaron Durbinffdf9012015-07-24 13:00:36 -0500[diff] [blame]30 select GENERIC_GPIO_LIB
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]31 select HAVE_FSP_GOP
Wim Vervoornd1371502019-12-17 14:10:16 +0100[diff] [blame]32 select HAVE_FSP_LOGO_SUPPORT
Felix Singerbd7020d2020-12-06 11:32:25 +0100[diff] [blame]33 select HAVE_INTEL_FSP_REPO
Shreesh Chhabbi87c7ec72020-12-03 14:07:15 -0800[diff] [blame^]34 select INTEL_CAR_NEM_ENHANCED
35 select INTEL_DESCRIPTOR_MODE_CAPABLE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]36 select HAVE_SMI_HANDLER
Felix Singerbd7020d2020-12-06 11:32:25 +0100[diff] [blame]37 select INTEL_DESCRIPTOR_MODE_CAPABLE
Patrick Rudolphc7edf182017-09-26 19:34:35 +0200[diff] [blame]38 select INTEL_GMA_ACPI
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]39 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]40 select IOAPIC
Duncan Laurie205ed2d2016-06-02 15:23:42 -0700[diff] [blame]41 select MRC_SETTINGS_PROTECT
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]42 select PARALLEL_MP
Furquan Shaikha5853582017-05-06 12:40:15 -0700[diff] [blame]43 select PARALLEL_MP_AP_WORK
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]44 select PLATFORM_USES_FSP2_0
Michael Niewöhnera1843d82020-10-02 18:28:22 +0200[diff] [blame]45 select PM_ACPI_TIMER_OPTIONAL
Julien Viard de Galbert2912e8e2018-08-14 16:15:26 +0200[diff] [blame]46 select PMC_GLOBAL_RESET_ENABLE_LOCK
Felix Singerbd7020d2020-12-06 11:32:25 +0100[diff] [blame]47 select REG_SCRIPT
48 select SA_ENABLE_DPR
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]49 select SOC_INTEL_COMMON
Duncan Lauriea1c8b34d2015-09-08 16:12:44 -0700[diff] [blame]50 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banike074d622017-02-16 16:16:37 +0530[diff] [blame]51 select SOC_INTEL_COMMON_BLOCK
Nico Huber2f1ef982018-11-07 16:24:50 +0100[diff] [blame]52 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]53 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Barnali Sarkar0a203d12017-05-04 18:02:17 +0530[diff] [blame]54 select SOC_INTEL_COMMON_BLOCK_CPU
Barnali Sarkar73273862017-06-13 20:22:33 +0530[diff] [blame]55 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Furquan Shaikh2c368892018-10-18 16:22:37 -0700[diff] [blame]56 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]57 select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]58 select SOC_INTEL_COMMON_BLOCK_GSPI
Furquan Shaikh31bff012018-09-29 23:31:04 -0700[diff] [blame]59 select SOC_INTEL_COMMON_BLOCK_HDA
Arthur Heymans1ae8cd12020-11-19 13:59:53 +0100[diff] [blame]60 select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
Subrata Banik93ebe492017-03-14 18:24:47 +0530[diff] [blame]61 select SOC_INTEL_COMMON_BLOCK_SA
Duncan Laurie1e066112020-04-08 11:35:52 -0700[diff] [blame]62 select SOC_INTEL_COMMON_BLOCK_SCS
Pratik Prajapatia04aa3d2017-06-12 23:02:36 -0700[diff] [blame]63 select SOC_INTEL_COMMON_BLOCK_SGX
Michael Niewöhnerc169a472019-10-31 19:01:23 +0100[diff] [blame]64 select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
Subrata Banikece173c2017-12-14 18:18:34 +0530[diff] [blame]65 select SOC_INTEL_COMMON_BLOCK_SMM
66 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banik2fff3912020-01-16 10:13:28 +0530[diff] [blame]67 select SOC_INTEL_COMMON_BLOCK_THERMAL
Subrata Banikafa07f72018-05-24 12:21:06 +0530[diff] [blame]68 select SOC_INTEL_COMMON_BLOCK_UART
Karthikeyan Ramasubramaniancc7cdb12019-03-20 11:38:01 -0600[diff] [blame]69 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Subrata Banik4ed9f9a2020-10-31 22:01:55 +0530[diff] [blame]70 select SOC_INTEL_COMMON_FSP_RESET
Subrata Banikf513ceb2018-05-17 15:57:43 +0530[diff] [blame]71 select SOC_INTEL_COMMON_PCH_BASE
Aaron Durbinc14a1a92016-06-28 15:41:07 -0500[diff] [blame]72 select SOC_INTEL_COMMON_NHLT
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]73 select SOC_INTEL_COMMON_RESET
Sumeet R Pawnikar97c54642020-05-10 01:24:11 +0530[diff] [blame]74 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
Nico Huberdd274e22020-04-26 20:37:32 +0200[diff] [blame]75 select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]76 select SSE2
77 select SUPPORT_CPU_UCODE_IN_CBFS
Aamir Bohra842776e2017-05-25 14:12:01 +0530[diff] [blame]78 select TSC_MONOTONIC_TIMER
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]79 select TSC_SYNC_MFENCE
80 select UDELAY_TSC
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]81 select UDK_2015_BINDING
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]82
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]83config FSP_HYPERTHREADING
84 bool "Enable Hyper-Threading"
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]85 default y
86
Arthur Heymans27d3f712018-01-05 17:51:46 +0100[diff] [blame]87config CPU_INTEL_NUM_FIT_ENTRIES
88 int
89 default 10
90
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]91config CHROMEOS
92 select CHROMEOS_RAMOOPS_DYNAMIC
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]93
94config VBOOT
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]95 select VBOOT_SEPARATE_VERSTAGE
Joel Kitching6672bd82019-04-10 16:06:21 +0800[diff] [blame]96 select VBOOT_MUST_REQUEST_DISPLAY
Aaron Durbina6914d22016-08-24 08:49:29 -0500[diff] [blame]97 select VBOOT_STARTS_IN_BOOTBLOCK
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -0700[diff] [blame]98 select VBOOT_VBNV_CMOS
99 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]100
Martin Roth59ff3402016-02-09 09:06:46 -0700[diff] [blame]101config CBFS_SIZE
102 hex
103 default 0x200000
104
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]105config DCACHE_RAM_BASE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]106 hex
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]107 default 0xfef00000
108
109config DCACHE_RAM_SIZE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]110 hex
Rizwan Qureshi3ad63562016-08-14 15:48:33 +0530[diff] [blame]111 default 0x40000
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]112 help
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]113 The size of the cache-as-ram region required during bootblock
114 and/or romstage.
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]115
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]116config DCACHE_BSP_STACK_SIZE
117 hex
118 default 0x4000
119 help
120 The amount of anticipated stack usage in CAR by bootblock and
121 other stages.
122
123config C_ENV_BOOTBLOCK_SIZE
124 hex
Furquan Shaikh70385962016-08-24 10:28:30 -0700[diff] [blame]125 default 0xC000
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]126
Subrata Banik086730b2015-12-02 11:42:04 +0530[diff] [blame]127config EXCLUDE_NATIVE_SD_INTERFACE
128 bool
129 default n
130 help
131 If you set this option to n, will not use native SD controller.
132
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]133config HEAP_SIZE
134 hex
135 default 0x80000
136
137config IED_REGION_SIZE
138 hex
139 default 0x400000
140
Subrata Banike7ceae72017-03-08 17:59:40 +0530[diff] [blame]141config PCR_BASE_ADDRESS
142 hex
143 default 0xfd000000
144 help
145 This option allows you to select MMIO Base Address of sideband bus.
146
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]147config SMM_RESERVED_SIZE
148 hex
149 default 0x200000
150
151config SMM_TSEG_SIZE
152 hex
153 default 0x800000
154
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]155config VGA_BIOS_ID
156 string
157 default "8086,0406"
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]158
Teo Boon Tiong2fc06c82016-09-15 11:11:45 +0800[diff] [blame]159config SKYLAKE_SOC_PCH_H
160 bool
161 default n
162 help
163 Choose this option if you have a PCH-H chipset.
164
Benjamin Doroneecaf362020-08-04 06:45:46 +0000[diff] [blame]165config NHLT_DMIC_1CH
166 bool
167 default n
168 help
169 Include DSP firmware settings for 1 channel DMIC array.
170
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]171config NHLT_DMIC_2CH
172 bool
173 default n
174 help
175 Include DSP firmware settings for 2 channel DMIC array.
176
177config NHLT_DMIC_4CH
178 bool
179 default n
180 help
181 Include DSP firmware settings for 4 channel DMIC array.
182
183config NHLT_NAU88L25
184 bool
185 default n
186 help
187 Include DSP firmware settings for nau88l25 headset codec.
188
189config NHLT_MAX98357
190 bool
191 default n
192 help
193 Include DSP firmware settings for max98357 amplifier.
194
Duncan Lauriee6c8a382018-03-26 02:45:02 -0700[diff] [blame]195config NHLT_MAX98373
196 bool
197 default n
198 help
199 Include DSP firmware settings for max98373 amplifier.
200
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]201config NHLT_SSM4567
202 bool
203 default n
204 help
205 Include DSP firmware settings for ssm4567 smart amplifier.
206
Duncan Laurie4a75a662017-03-02 10:13:51 -0800[diff] [blame]207config NHLT_RT5514
208 bool
209 default n
210 help
211 Include DSP firmware settings for rt5514 DSP.
212
Rizwan Qureshi17335fa2017-01-14 06:08:21 +0530[diff] [blame]213config NHLT_RT5663
214 bool
215 default n
216 help
217 Include DSP firmware settings for rt5663 headset codec.
218
219config NHLT_MAX98927
220 bool
221 default n
222 help
223 Include DSP firmware settings for max98927 amplifier.
224
Naveen Manohar83670c52017-11-04 02:55:09 +0530[diff] [blame]225config NHLT_DA7219
226 bool
227 default n
228 help
229 Include DSP firmware settings for DA7219 headset codec.
230
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]231config FSP_HEADER_PATH
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]232 # Use KabylakeFsp for both Skylake and Kabylake as it supports both.
233 # SkylakeFsp is FSP 1.1 and therefore incompatible.
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]234 default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]235
236config FSP_FD_PATH
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]237 default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]238
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]239config MAX_ROOT_PORTS
240 int
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]241 default 24
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]242
Jenny TC2864f852017-02-09 16:01:59 +0530[diff] [blame]243config NO_FADT_8042
244 bool
245 default n
246 help
247 Choose this option if you want to disable 8042 Keyboard
248
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]249config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Furquan Shaikh340908a2017-04-04 11:47:19 -0700[diff] [blame]250 int
251 default 120
252
Michael Niewöhnerdadcbfb2020-10-04 14:48:05 +0200[diff] [blame]253config CPU_XTAL_HZ
254 default 24000000
255
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]256config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
257 int
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]258 default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]259
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]260config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
261 int
262 default 2
263
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]264config SOC_INTEL_I2C_DEV_MAX
265 int
266 default 6
267
Aamir Bohra1041d392017-06-02 11:56:14 +0530[diff] [blame]268config CPU_BCLK_MHZ
269 int
270 default 100
271
Nico Huber99954182019-05-29 23:33:06 +0200[diff] [blame]272config CONSOLE_UART_BASE_ADDRESS
273 hex
274 default 0xfe030000
275 depends on INTEL_LPSS_UART_FOR_CONSOLE
276
Furquan Shaikh3406dd62017-08-04 15:58:26 -0700[diff] [blame]277# Clock divider parameters for 115200 baud rate
278config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
279 hex
280 default 0x30
281
282config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
283 hex
284 default 0xc35
285
Felix Singer424467c2020-10-12 19:51:02 +0000[diff] [blame]286config CHIPSET_DEVICETREE
287 string
288 default "soc/intel/skylake/chipset.cb"
289
Furquan Shaikha3ad9902018-03-21 10:45:08 -0700[diff] [blame]290config IFD_CHIPSET
291 string
292 default "sklkbl"
293
Patrick Rudolph5fffb5e2019-07-25 11:55:30 +0200[diff] [blame]294config INTEL_TXT_BIOSACM_ALIGNMENT
295 hex
296 default 0x40000 # 256KB
297
Wim Vervoorn2ab4f4b2019-10-23 10:22:06 +0200[diff] [blame]298config MAINBOARD_SUPPORTS_SKYLAKE_CPU
299 bool "Board can contain Skylake CPU"
300 default y
301
302if SKYLAKE_SOC_PCH_H
303
304config MAINBOARD_SUPPORTS_KABYLAKE_CPU
305 bool "Board can contain Kaby Lake CPU"
306 default y if SOC_INTEL_KABYLAKE
307
308endif
309
310if !SKYLAKE_SOC_PCH_H
311
312config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
313 bool "Board can contain Kaby Lake DUAL core"
314 default y
315
316config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
317 bool "Board can contain Kaby Lake QUAD core"
318 default y
319
320endif
321
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]322endif