Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 1 | config SOC_INTEL_COMMON_SKYLAKE_BASE |
2 | bool | ||||
3 | |||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 4 | config SOC_INTEL_SKYLAKE |
5 | bool | ||||
Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 6 | select SOC_INTEL_COMMON_SKYLAKE_BASE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 7 | help |
8 | Intel Skylake support | ||||
9 | |||||
Rizwan Qureshi | 0700dca | 2017-02-09 15:57:45 +0530 | [diff] [blame] | 10 | config SOC_INTEL_KABYLAKE |
11 | bool | ||||
Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 12 | select SOC_INTEL_COMMON_SKYLAKE_BASE |
Rizwan Qureshi | 0700dca | 2017-02-09 15:57:45 +0530 | [diff] [blame] | 13 | help |
14 | Intel Kabylake support | ||||
15 | |||||
Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 16 | if SOC_INTEL_COMMON_SKYLAKE_BASE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 17 | |
18 | config CPU_SPECIFIC_OPTIONS | ||||
19 | def_bool y | ||||
Aaron Durbin | e0a4914 | 2016-07-13 23:20:51 -0500 | [diff] [blame] | 20 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 21 | select ACPI_NHLT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 22 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 23 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 24 | select ARCH_ROMSTAGE_X86_32 |
25 | select ARCH_VERSTAGE_X86_32 | ||||
Aaron Durbin | e4cc8cd | 2016-08-11 23:55:39 -0500 | [diff] [blame] | 26 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 27 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 28 | select CACHE_MRC_SETTINGS |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 29 | select COLLECT_TIMESTAMPS |
Duncan Laurie | 135c2c4 | 2016-10-17 19:47:51 -0700 | [diff] [blame] | 30 | select COMMON_FADT |
Nico Huber | 6275e34 | 2018-11-21 00:11:35 +0100 | [diff] [blame] | 31 | select CPU_INTEL_COMMON |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 32 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | 7bdedcd | 2019-09-01 16:49:09 +0200 | [diff] [blame] | 33 | select CPU_INTEL_COMMON_HYPERTHREADING |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 34 | select C_ENVIRONMENT_BOOTBLOCK |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 35 | select FSP_M_XIP |
Matt DeVillier | 9e94607 | 2019-01-26 18:42:35 -0600 | [diff] [blame] | 36 | select FSP_T_XIP if FSP_CAR |
Aaron Durbin | ffdf901 | 2015-07-24 13:00:36 -0500 | [diff] [blame] | 37 | select GENERIC_GPIO_LIB |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 38 | select HAVE_FSP_GOP |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 39 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 40 | select HAVE_SMI_HANDLER |
Nico Huber | 2f1ef98 | 2018-11-07 16:24:50 +0100 | [diff] [blame] | 41 | select INTEL_CAR_NEM_ENHANCED |
Patrick Rudolph | c7edf18 | 2017-09-26 19:34:35 +0200 | [diff] [blame] | 42 | select INTEL_GMA_ACPI |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 43 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 44 | select IOAPIC |
Duncan Laurie | 205ed2d | 2016-06-02 15:23:42 -0700 | [diff] [blame] | 45 | select MRC_SETTINGS_PROTECT |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 46 | select NO_FIXED_XIP_ROM_SIZE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 47 | select PARALLEL_MP |
Furquan Shaikh | a585358 | 2017-05-06 12:40:15 -0700 | [diff] [blame] | 48 | select PARALLEL_MP_AP_WORK |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 49 | select PCIEX_LENGTH_64MB |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 50 | select PLATFORM_USES_FSP2_0 |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 51 | select REG_SCRIPT |
Subrata Banik | 46a7178 | 2017-06-02 18:52:24 +0530 | [diff] [blame] | 52 | select SA_ENABLE_DPR |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 53 | select SMP |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 54 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON |
Duncan Laurie | a1c8b34d | 2015-09-08 16:12:44 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | e074d62 | 2017-02-16 16:16:37 +0530 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK |
Nico Huber | 2f1ef98 | 2018-11-07 16:24:50 +0100 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Barnali Sarkar | 0a203d1 | 2017-05-04 18:02:17 +0530 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_CPU |
Barnali Sarkar | 7327386 | 2017-06-13 20:22:33 +0530 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Furquan Shaikh | 2c36889 | 2018-10-18 16:22:37 -0700 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Hannah Williams | 1760cd3 | 2017-04-06 20:54:11 -0700 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_GSPI |
Furquan Shaikh | 31bff01 | 2018-09-29 23:31:04 -0700 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_HDA |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_SA |
Pratik Prajapati | a04aa3d | 2017-06-12 23:02:36 -0700 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_SGX |
Michael Niewöhner | c169a47 | 2019-10-31 19:01:23 +0100 | [diff] [blame^] | 69 | select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_BLOCK_SMM |
71 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP | ||||
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_BLOCK_UART |
Karthikeyan Ramasubramanian | cc7cdb1 | 2019-03-20 11:38:01 -0600 | [diff] [blame] | 73 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | f513ceb | 2018-05-17 15:57:43 +0530 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_PCH_BASE |
Aaron Durbin | c14a1a9 | 2016-06-28 15:41:07 -0500 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_NHLT |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 76 | select SOC_INTEL_COMMON_RESET |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 77 | select SSE2 |
78 | select SUPPORT_CPU_UCODE_IN_CBFS | ||||
79 | select TSC_CONSTANT_RATE | ||||
Aamir Bohra | 842776e | 2017-05-25 14:12:01 +0530 | [diff] [blame] | 80 | select TSC_MONOTONIC_TIMER |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 81 | select TSC_SYNC_MFENCE |
82 | select UDELAY_TSC | ||||
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 83 | select UDK_2015_BINDING |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 84 | |
Patrick Rudolph | 203061c | 2019-09-02 09:35:21 +0200 | [diff] [blame] | 85 | config FSP_HYPERTHREADING |
86 | bool "Enable Hyper-Threading" | ||||
Patrick Rudolph | 203061c | 2019-09-02 09:35:21 +0200 | [diff] [blame] | 87 | default y |
88 | |||||
Arthur Heymans | 27d3f71 | 2018-01-05 17:51:46 +0100 | [diff] [blame] | 89 | config CPU_INTEL_NUM_FIT_ENTRIES |
90 | int | ||||
91 | default 10 | ||||
92 | |||||
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 93 | config CHROMEOS |
94 | select CHROMEOS_RAMOOPS_DYNAMIC | ||||
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 95 | |
96 | config VBOOT | ||||
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 97 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 98 | select VBOOT_MUST_REQUEST_DISPLAY |
Furquan Shaikh | b8257df | 2016-07-22 09:20:56 -0700 | [diff] [blame] | 99 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
Aaron Durbin | a6914d2 | 2016-08-24 08:49:29 -0500 | [diff] [blame] | 100 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 101 | select VBOOT_VBNV_CMOS |
102 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH | ||||
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 103 | |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 104 | config CBFS_SIZE |
105 | hex | ||||
106 | default 0x200000 | ||||
107 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 108 | config DCACHE_RAM_BASE |
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 109 | hex |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 110 | default 0xfef00000 |
111 | |||||
112 | config DCACHE_RAM_SIZE | ||||
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 113 | hex |
Rizwan Qureshi | 3ad6356 | 2016-08-14 15:48:33 +0530 | [diff] [blame] | 114 | default 0x40000 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 115 | help |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 116 | The size of the cache-as-ram region required during bootblock |
117 | and/or romstage. | ||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 118 | |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 119 | config DCACHE_BSP_STACK_SIZE |
120 | hex | ||||
121 | default 0x4000 | ||||
122 | help | ||||
123 | The amount of anticipated stack usage in CAR by bootblock and | ||||
124 | other stages. | ||||
125 | |||||
126 | config C_ENV_BOOTBLOCK_SIZE | ||||
127 | hex | ||||
Furquan Shaikh | 7038596 | 2016-08-24 10:28:30 -0700 | [diff] [blame] | 128 | default 0xC000 |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 129 | |
Subrata Banik | 086730b | 2015-12-02 11:42:04 +0530 | [diff] [blame] | 130 | config EXCLUDE_NATIVE_SD_INTERFACE |
131 | bool | ||||
132 | default n | ||||
133 | help | ||||
134 | If you set this option to n, will not use native SD controller. | ||||
135 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 136 | config HEAP_SIZE |
137 | hex | ||||
138 | default 0x80000 | ||||
139 | |||||
140 | config IED_REGION_SIZE | ||||
141 | hex | ||||
142 | default 0x400000 | ||||
143 | |||||
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 144 | config PCR_BASE_ADDRESS |
145 | hex | ||||
146 | default 0xfd000000 | ||||
147 | help | ||||
148 | This option allows you to select MMIO Base Address of sideband bus. | ||||
149 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 150 | config SMM_RESERVED_SIZE |
151 | hex | ||||
152 | default 0x200000 | ||||
153 | |||||
154 | config SMM_TSEG_SIZE | ||||
155 | hex | ||||
156 | default 0x800000 | ||||
157 | |||||
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 158 | config VGA_BIOS_ID |
159 | string | ||||
160 | default "8086,0406" | ||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 161 | |
Teo Boon Tiong | 2fc06c8 | 2016-09-15 11:11:45 +0800 | [diff] [blame] | 162 | config SKYLAKE_SOC_PCH_H |
163 | bool | ||||
164 | default n | ||||
165 | help | ||||
166 | Choose this option if you have a PCH-H chipset. | ||||
167 | |||||
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 168 | config NHLT_DMIC_2CH |
169 | bool | ||||
170 | default n | ||||
171 | help | ||||
172 | Include DSP firmware settings for 2 channel DMIC array. | ||||
173 | |||||
174 | config NHLT_DMIC_4CH | ||||
175 | bool | ||||
176 | default n | ||||
177 | help | ||||
178 | Include DSP firmware settings for 4 channel DMIC array. | ||||
179 | |||||
180 | config NHLT_NAU88L25 | ||||
181 | bool | ||||
182 | default n | ||||
183 | help | ||||
184 | Include DSP firmware settings for nau88l25 headset codec. | ||||
185 | |||||
186 | config NHLT_MAX98357 | ||||
187 | bool | ||||
188 | default n | ||||
189 | help | ||||
190 | Include DSP firmware settings for max98357 amplifier. | ||||
191 | |||||
Duncan Laurie | e6c8a38 | 2018-03-26 02:45:02 -0700 | [diff] [blame] | 192 | config NHLT_MAX98373 |
193 | bool | ||||
194 | default n | ||||
195 | help | ||||
196 | Include DSP firmware settings for max98373 amplifier. | ||||
197 | |||||
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 198 | config NHLT_SSM4567 |
199 | bool | ||||
200 | default n | ||||
201 | help | ||||
202 | Include DSP firmware settings for ssm4567 smart amplifier. | ||||
203 | |||||
Duncan Laurie | 4a75a66 | 2017-03-02 10:13:51 -0800 | [diff] [blame] | 204 | config NHLT_RT5514 |
205 | bool | ||||
206 | default n | ||||
207 | help | ||||
208 | Include DSP firmware settings for rt5514 DSP. | ||||
209 | |||||
Rizwan Qureshi | 17335fa | 2017-01-14 06:08:21 +0530 | [diff] [blame] | 210 | config NHLT_RT5663 |
211 | bool | ||||
212 | default n | ||||
213 | help | ||||
214 | Include DSP firmware settings for rt5663 headset codec. | ||||
215 | |||||
216 | config NHLT_MAX98927 | ||||
217 | bool | ||||
218 | default n | ||||
219 | help | ||||
220 | Include DSP firmware settings for max98927 amplifier. | ||||
221 | |||||
Naveen Manohar | 83670c5 | 2017-11-04 02:55:09 +0530 | [diff] [blame] | 222 | config NHLT_DA7219 |
223 | bool | ||||
224 | default n | ||||
225 | help | ||||
226 | Include DSP firmware settings for DA7219 headset codec. | ||||
227 | |||||
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 228 | config FSP_HEADER_PATH |
Patrick Georgi | c6382cd | 2018-10-26 22:03:17 +0200 | [diff] [blame] | 229 | string "Location of FSP headers" |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 230 | # Use KabylakeFsp for both Skylake and Kabylake as it supports both. |
231 | # SkylakeFsp is FSP 1.1 and therefore incompatible. | ||||
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 232 | default "3rdparty/fsp/KabylakeFspBinPkg/Include/" |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 233 | |
234 | config FSP_FD_PATH | ||||
235 | string | ||||
236 | depends on FSP_USE_REPO | ||||
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 237 | default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 238 | |
Aaron Durbin | e56191e | 2016-08-11 09:50:49 -0500 | [diff] [blame] | 239 | config SPI_FLASH_INCLUDE_ALL_DRIVERS |
240 | bool | ||||
241 | default n | ||||
242 | |||||
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 243 | config MAX_ROOT_PORTS |
244 | int | ||||
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 245 | default 24 |
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 246 | |
Jenny TC | 2864f85 | 2017-02-09 16:01:59 +0530 | [diff] [blame] | 247 | config NO_FADT_8042 |
248 | bool | ||||
249 | default n | ||||
250 | help | ||||
251 | Choose this option if you want to disable 8042 Keyboard | ||||
252 | |||||
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 253 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Furquan Shaikh | 340908a | 2017-04-04 11:47:19 -0700 | [diff] [blame] | 254 | int |
255 | default 120 | ||||
256 | |||||
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 257 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
258 | int | ||||
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 259 | default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 260 | |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 261 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
262 | int | ||||
263 | default 2 | ||||
264 | |||||
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 265 | config SOC_INTEL_I2C_DEV_MAX |
266 | int | ||||
267 | default 6 | ||||
268 | |||||
Aamir Bohra | 1041d39 | 2017-06-02 11:56:14 +0530 | [diff] [blame] | 269 | config CPU_BCLK_MHZ |
270 | int | ||||
271 | default 100 | ||||
272 | |||||
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 273 | config CONSOLE_UART_BASE_ADDRESS |
274 | hex | ||||
275 | default 0xfe030000 | ||||
276 | depends on INTEL_LPSS_UART_FOR_CONSOLE | ||||
277 | |||||
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 278 | # Clock divider parameters for 115200 baud rate |
279 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL | ||||
280 | hex | ||||
281 | default 0x30 | ||||
282 | |||||
283 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL | ||||
284 | hex | ||||
285 | default 0xc35 | ||||
286 | |||||
Furquan Shaikh | a3ad990 | 2018-03-21 10:45:08 -0700 | [diff] [blame] | 287 | config IFD_CHIPSET |
288 | string | ||||
289 | default "sklkbl" | ||||
290 | |||||
Patrick Rudolph | 5fffb5e | 2019-07-25 11:55:30 +0200 | [diff] [blame] | 291 | config INTEL_TXT_BIOSACM_ALIGNMENT |
292 | hex | ||||
293 | default 0x40000 # 256KB | ||||
294 | |||||
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 295 | endif |