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review.coreboot.org / coreboot / eecaf360de2ae3068f51746a64e943c8d18a4f6f / . / src / soc / intel / skylake / Kconfig
blob: ba3af84fc7ecaa3379babb001bda31a7cded1620 [file] [log] [blame]
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]1config SOC_INTEL_COMMON_SKYLAKE_BASE
2 bool
3
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]4config SOC_INTEL_SKYLAKE
5 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]6 select SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]7 help
8 Intel Skylake support
9
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]10config SOC_INTEL_KABYLAKE
11 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]12 select SOC_INTEL_COMMON_SKYLAKE_BASE
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]13 help
14 Intel Kabylake support
15
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]16if SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]17
18config CPU_SPECIFIC_OPTIONS
19 def_bool y
Aaron Durbine0a49142016-07-13 23:20:51 -0500[diff] [blame]20 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]21 select ACPI_NHLT
Angel Ponsa32df262020-09-25 10:20:11 +0200[diff] [blame]22 select ARCH_ALL_STAGES_X86_32
Aaron Durbine8e118d2016-08-12 15:00:10 -0500[diff] [blame]23 select BOOT_DEVICE_SUPPORTS_WRITES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]24 select CACHE_MRC_SETTINGS
Nico Huber6275e342018-11-21 00:11:35 +0100[diff] [blame]25 select CPU_INTEL_COMMON
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]26 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhnerfe6070f2020-10-04 15:16:04 +0200[diff] [blame]27 select CPU_SUPPORTS_PM_TIMER_EMULATION
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]28 select FSP_M_XIP
Subrata Banik4ed9f9a2020-10-31 22:01:55 +0530[diff] [blame]29 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
Aaron Durbinffdf9012015-07-24 13:00:36 -0500[diff] [blame]30 select GENERIC_GPIO_LIB
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]31 select HAVE_FSP_GOP
Wim Vervoornd1371502019-12-17 14:10:16 +0100[diff] [blame]32 select HAVE_FSP_LOGO_SUPPORT
Stefan Tauneref8b9572018-09-06 00:34:28 +0200[diff] [blame]33 select INTEL_DESCRIPTOR_MODE_CAPABLE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]34 select HAVE_SMI_HANDLER
Patrick Rudolphc7edf182017-09-26 19:34:35 +0200[diff] [blame]35 select INTEL_GMA_ACPI
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]36 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Johanna Schander8a6e0362019-12-08 15:54:09 +0100[diff] [blame]37 select HAVE_INTEL_FSP_REPO
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]38 select IOAPIC
Duncan Laurie205ed2d2016-06-02 15:23:42 -0700[diff] [blame]39 select MRC_SETTINGS_PROTECT
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]40 select PARALLEL_MP
Furquan Shaikha5853582017-05-06 12:40:15 -0700[diff] [blame]41 select PARALLEL_MP_AP_WORK
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]42 select PLATFORM_USES_FSP2_0
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]43 select REG_SCRIPT
Subrata Banik46a71782017-06-02 18:52:24 +0530[diff] [blame]44 select SA_ENABLE_DPR
Michael Niewöhnera1843d82020-10-02 18:28:22 +0200[diff] [blame]45 select PM_ACPI_TIMER_OPTIONAL
Julien Viard de Galbert2912e8e2018-08-14 16:15:26 +0200[diff] [blame]46 select PMC_GLOBAL_RESET_ENABLE_LOCK
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]47 select SOC_INTEL_COMMON
Duncan Lauriea1c8b34d2015-09-08 16:12:44 -0700[diff] [blame]48 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banike074d622017-02-16 16:16:37 +0530[diff] [blame]49 select SOC_INTEL_COMMON_BLOCK
Nico Huber2f1ef982018-11-07 16:24:50 +0100[diff] [blame]50 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]51 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Barnali Sarkar0a203d12017-05-04 18:02:17 +0530[diff] [blame]52 select SOC_INTEL_COMMON_BLOCK_CPU
Barnali Sarkar73273862017-06-13 20:22:33 +0530[diff] [blame]53 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Furquan Shaikh2c368892018-10-18 16:22:37 -0700[diff] [blame]54 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]55 select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]56 select SOC_INTEL_COMMON_BLOCK_GSPI
Furquan Shaikh31bff012018-09-29 23:31:04 -0700[diff] [blame]57 select SOC_INTEL_COMMON_BLOCK_HDA
Arthur Heymans1ae8cd12020-11-19 13:59:53 +0100[diff] [blame]58 select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
Subrata Banik93ebe492017-03-14 18:24:47 +0530[diff] [blame]59 select SOC_INTEL_COMMON_BLOCK_SA
Duncan Laurie1e066112020-04-08 11:35:52 -0700[diff] [blame]60 select SOC_INTEL_COMMON_BLOCK_SCS
Pratik Prajapatia04aa3d2017-06-12 23:02:36 -0700[diff] [blame]61 select SOC_INTEL_COMMON_BLOCK_SGX
Michael Niewöhnerc169a472019-10-31 19:01:23 +0100[diff] [blame]62 select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
Subrata Banikece173c2017-12-14 18:18:34 +0530[diff] [blame]63 select SOC_INTEL_COMMON_BLOCK_SMM
64 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banik2fff3912020-01-16 10:13:28 +0530[diff] [blame]65 select SOC_INTEL_COMMON_BLOCK_THERMAL
Subrata Banikafa07f72018-05-24 12:21:06 +0530[diff] [blame]66 select SOC_INTEL_COMMON_BLOCK_UART
Karthikeyan Ramasubramaniancc7cdb12019-03-20 11:38:01 -0600[diff] [blame]67 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Subrata Banik4ed9f9a2020-10-31 22:01:55 +0530[diff] [blame]68 select SOC_INTEL_COMMON_FSP_RESET
Subrata Banikf513ceb2018-05-17 15:57:43 +0530[diff] [blame]69 select SOC_INTEL_COMMON_PCH_BASE
Aaron Durbinc14a1a92016-06-28 15:41:07 -0500[diff] [blame]70 select SOC_INTEL_COMMON_NHLT
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]71 select SOC_INTEL_COMMON_RESET
Sumeet R Pawnikar97c54642020-05-10 01:24:11 +0530[diff] [blame]72 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
Nico Huberdd274e22020-04-26 20:37:32 +0200[diff] [blame]73 select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]74 select SSE2
75 select SUPPORT_CPU_UCODE_IN_CBFS
Aamir Bohra842776e2017-05-25 14:12:01 +0530[diff] [blame]76 select TSC_MONOTONIC_TIMER
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]77 select TSC_SYNC_MFENCE
78 select UDELAY_TSC
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]79 select UDK_2015_BINDING
Aamir Bohrac1d227d2020-07-16 09:03:06 +0530[diff] [blame]80 select USE_CAR_NEM_ENHANCED_V1
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]81
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]82config FSP_HYPERTHREADING
83 bool "Enable Hyper-Threading"
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]84 default y
85
Arthur Heymans27d3f712018-01-05 17:51:46 +0100[diff] [blame]86config CPU_INTEL_NUM_FIT_ENTRIES
87 int
88 default 10
89
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]90config CHROMEOS
91 select CHROMEOS_RAMOOPS_DYNAMIC
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]92
93config VBOOT
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]94 select VBOOT_SEPARATE_VERSTAGE
Joel Kitching6672bd82019-04-10 16:06:21 +0800[diff] [blame]95 select VBOOT_MUST_REQUEST_DISPLAY
Aaron Durbina6914d22016-08-24 08:49:29 -0500[diff] [blame]96 select VBOOT_STARTS_IN_BOOTBLOCK
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -0700[diff] [blame]97 select VBOOT_VBNV_CMOS
98 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]99
Martin Roth59ff3402016-02-09 09:06:46 -0700[diff] [blame]100config CBFS_SIZE
101 hex
102 default 0x200000
103
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]104config DCACHE_RAM_BASE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]105 hex
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]106 default 0xfef00000
107
108config DCACHE_RAM_SIZE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]109 hex
Rizwan Qureshi3ad63562016-08-14 15:48:33 +0530[diff] [blame]110 default 0x40000
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]111 help
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]112 The size of the cache-as-ram region required during bootblock
113 and/or romstage.
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]114
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]115config DCACHE_BSP_STACK_SIZE
116 hex
117 default 0x4000
118 help
119 The amount of anticipated stack usage in CAR by bootblock and
120 other stages.
121
122config C_ENV_BOOTBLOCK_SIZE
123 hex
Furquan Shaikh70385962016-08-24 10:28:30 -0700[diff] [blame]124 default 0xC000
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]125
Subrata Banik086730b2015-12-02 11:42:04 +0530[diff] [blame]126config EXCLUDE_NATIVE_SD_INTERFACE
127 bool
128 default n
129 help
130 If you set this option to n, will not use native SD controller.
131
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]132config HEAP_SIZE
133 hex
134 default 0x80000
135
136config IED_REGION_SIZE
137 hex
138 default 0x400000
139
Subrata Banike7ceae72017-03-08 17:59:40 +0530[diff] [blame]140config PCR_BASE_ADDRESS
141 hex
142 default 0xfd000000
143 help
144 This option allows you to select MMIO Base Address of sideband bus.
145
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]146config SMM_RESERVED_SIZE
147 hex
148 default 0x200000
149
150config SMM_TSEG_SIZE
151 hex
152 default 0x800000
153
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]154config VGA_BIOS_ID
155 string
156 default "8086,0406"
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]157
Teo Boon Tiong2fc06c82016-09-15 11:11:45 +0800[diff] [blame]158config SKYLAKE_SOC_PCH_H
159 bool
160 default n
161 help
162 Choose this option if you have a PCH-H chipset.
163
Benjamin Doroneecaf362020-08-04 06:45:46 +0000[diff] [blame^]164config NHLT_DMIC_1CH
165 bool
166 default n
167 help
168 Include DSP firmware settings for 1 channel DMIC array.
169
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]170config NHLT_DMIC_2CH
171 bool
172 default n
173 help
174 Include DSP firmware settings for 2 channel DMIC array.
175
176config NHLT_DMIC_4CH
177 bool
178 default n
179 help
180 Include DSP firmware settings for 4 channel DMIC array.
181
182config NHLT_NAU88L25
183 bool
184 default n
185 help
186 Include DSP firmware settings for nau88l25 headset codec.
187
188config NHLT_MAX98357
189 bool
190 default n
191 help
192 Include DSP firmware settings for max98357 amplifier.
193
Duncan Lauriee6c8a382018-03-26 02:45:02 -0700[diff] [blame]194config NHLT_MAX98373
195 bool
196 default n
197 help
198 Include DSP firmware settings for max98373 amplifier.
199
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]200config NHLT_SSM4567
201 bool
202 default n
203 help
204 Include DSP firmware settings for ssm4567 smart amplifier.
205
Duncan Laurie4a75a662017-03-02 10:13:51 -0800[diff] [blame]206config NHLT_RT5514
207 bool
208 default n
209 help
210 Include DSP firmware settings for rt5514 DSP.
211
Rizwan Qureshi17335fa2017-01-14 06:08:21 +0530[diff] [blame]212config NHLT_RT5663
213 bool
214 default n
215 help
216 Include DSP firmware settings for rt5663 headset codec.
217
218config NHLT_MAX98927
219 bool
220 default n
221 help
222 Include DSP firmware settings for max98927 amplifier.
223
Naveen Manohar83670c52017-11-04 02:55:09 +0530[diff] [blame]224config NHLT_DA7219
225 bool
226 default n
227 help
228 Include DSP firmware settings for DA7219 headset codec.
229
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]230config FSP_HEADER_PATH
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]231 # Use KabylakeFsp for both Skylake and Kabylake as it supports both.
232 # SkylakeFsp is FSP 1.1 and therefore incompatible.
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]233 default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]234
235config FSP_FD_PATH
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]236 default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]237
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]238config MAX_ROOT_PORTS
239 int
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]240 default 24
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]241
Jenny TC2864f852017-02-09 16:01:59 +0530[diff] [blame]242config NO_FADT_8042
243 bool
244 default n
245 help
246 Choose this option if you want to disable 8042 Keyboard
247
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]248config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Furquan Shaikh340908a2017-04-04 11:47:19 -0700[diff] [blame]249 int
250 default 120
251
Michael Niewöhnerdadcbfb2020-10-04 14:48:05 +0200[diff] [blame]252config CPU_XTAL_HZ
253 default 24000000
254
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]255config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
256 int
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]257 default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]258
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]259config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
260 int
261 default 2
262
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]263config SOC_INTEL_I2C_DEV_MAX
264 int
265 default 6
266
Aamir Bohra1041d392017-06-02 11:56:14 +0530[diff] [blame]267config CPU_BCLK_MHZ
268 int
269 default 100
270
Nico Huber99954182019-05-29 23:33:06 +0200[diff] [blame]271config CONSOLE_UART_BASE_ADDRESS
272 hex
273 default 0xfe030000
274 depends on INTEL_LPSS_UART_FOR_CONSOLE
275
Furquan Shaikh3406dd62017-08-04 15:58:26 -0700[diff] [blame]276# Clock divider parameters for 115200 baud rate
277config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
278 hex
279 default 0x30
280
281config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
282 hex
283 default 0xc35
284
Furquan Shaikha3ad9902018-03-21 10:45:08 -0700[diff] [blame]285config IFD_CHIPSET
286 string
287 default "sklkbl"
288
Patrick Rudolph5fffb5e2019-07-25 11:55:30 +0200[diff] [blame]289config INTEL_TXT_BIOSACM_ALIGNMENT
290 hex
291 default 0x40000 # 256KB
292
Wim Vervoorn2ab4f4b2019-10-23 10:22:06 +0200[diff] [blame]293config MAINBOARD_SUPPORTS_SKYLAKE_CPU
294 bool "Board can contain Skylake CPU"
295 default y
296
297if SKYLAKE_SOC_PCH_H
298
299config MAINBOARD_SUPPORTS_KABYLAKE_CPU
300 bool "Board can contain Kaby Lake CPU"
301 default y if SOC_INTEL_KABYLAKE
302
303endif
304
305if !SKYLAKE_SOC_PCH_H
306
307config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
308 bool "Board can contain Kaby Lake DUAL core"
309 default y
310
311config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
312 bool "Board can contain Kaby Lake QUAD core"
313 default y
314
315endif
316
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]317endif