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review.coreboot.org / coreboot / d1371508f525542f3b75de553dc338b9100bde20 / . / src / soc / intel / skylake / Kconfig
blob: d90fb6b9fb55f6f4e2e8dd238ea9cd949532f913 [file] [log] [blame]
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]1config SOC_INTEL_COMMON_SKYLAKE_BASE
2 bool
3
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]4config SOC_INTEL_SKYLAKE
5 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]6 select SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]7 help
8 Intel Skylake support
9
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]10config SOC_INTEL_KABYLAKE
11 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]12 select SOC_INTEL_COMMON_SKYLAKE_BASE
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]13 help
14 Intel Kabylake support
15
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]16if SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]17
18config CPU_SPECIFIC_OPTIONS
19 def_bool y
Aaron Durbine0a49142016-07-13 23:20:51 -0500[diff] [blame]20 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]21 select ACPI_NHLT
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]22 select ARCH_BOOTBLOCK_X86_32
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]23 select ARCH_RAMSTAGE_X86_32
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]24 select ARCH_ROMSTAGE_X86_32
25 select ARCH_VERSTAGE_X86_32
Aaron Durbine4cc8cd2016-08-11 23:55:39 -0500[diff] [blame]26 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
Aaron Durbine8e118d2016-08-12 15:00:10 -0500[diff] [blame]27 select BOOT_DEVICE_SUPPORTS_WRITES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]28 select CACHE_MRC_SETTINGS
Duncan Laurie135c2c42016-10-17 19:47:51 -0700[diff] [blame]29 select COMMON_FADT
Nico Huber6275e342018-11-21 00:11:35 +0100[diff] [blame]30 select CPU_INTEL_COMMON
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]31 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhner7bdedcd2019-09-01 16:49:09 +0200[diff] [blame]32 select CPU_INTEL_COMMON_HYPERTHREADING
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]33 select FSP_M_XIP
Aaron Durbinffdf9012015-07-24 13:00:36 -0500[diff] [blame]34 select GENERIC_GPIO_LIB
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]35 select HAVE_FSP_GOP
Wim Vervoornd1371502019-12-17 14:10:16 +0100[diff] [blame^]36 select HAVE_FSP_LOGO_SUPPORT
Stefan Tauneref8b9572018-09-06 00:34:28 +0200[diff] [blame]37 select INTEL_DESCRIPTOR_MODE_CAPABLE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]38 select HAVE_SMI_HANDLER
Nico Huber2f1ef982018-11-07 16:24:50 +0100[diff] [blame]39 select INTEL_CAR_NEM_ENHANCED
Patrick Rudolphc7edf182017-09-26 19:34:35 +0200[diff] [blame]40 select INTEL_GMA_ACPI
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]41 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]42 select IOAPIC
Duncan Laurie205ed2d2016-06-02 15:23:42 -0700[diff] [blame]43 select MRC_SETTINGS_PROTECT
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]44 select NO_FIXED_XIP_ROM_SIZE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]45 select PARALLEL_MP
Furquan Shaikha5853582017-05-06 12:40:15 -0700[diff] [blame]46 select PARALLEL_MP_AP_WORK
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]47 select PLATFORM_USES_FSP2_0
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]48 select REG_SCRIPT
Subrata Banik46a71782017-06-02 18:52:24 +0530[diff] [blame]49 select SA_ENABLE_DPR
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]50 select SMP
Julien Viard de Galbert2912e8e2018-08-14 16:15:26 +0200[diff] [blame]51 select PMC_GLOBAL_RESET_ENABLE_LOCK
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]52 select SOC_INTEL_COMMON
Duncan Lauriea1c8b34d2015-09-08 16:12:44 -0700[diff] [blame]53 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banike074d622017-02-16 16:16:37 +0530[diff] [blame]54 select SOC_INTEL_COMMON_BLOCK
Nico Huber2f1ef982018-11-07 16:24:50 +0100[diff] [blame]55 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]56 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Barnali Sarkar0a203d12017-05-04 18:02:17 +0530[diff] [blame]57 select SOC_INTEL_COMMON_BLOCK_CPU
Barnali Sarkar73273862017-06-13 20:22:33 +0530[diff] [blame]58 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Furquan Shaikh2c368892018-10-18 16:22:37 -0700[diff] [blame]59 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Hannah Williams1760cd32017-04-06 20:54:11 -0700[diff] [blame]60 select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]61 select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]62 select SOC_INTEL_COMMON_BLOCK_GSPI
Furquan Shaikh31bff012018-09-29 23:31:04 -0700[diff] [blame]63 select SOC_INTEL_COMMON_BLOCK_HDA
Subrata Banik93ebe492017-03-14 18:24:47 +0530[diff] [blame]64 select SOC_INTEL_COMMON_BLOCK_SA
Pratik Prajapatia04aa3d2017-06-12 23:02:36 -0700[diff] [blame]65 select SOC_INTEL_COMMON_BLOCK_SGX
Michael Niewöhnerc169a472019-10-31 19:01:23 +0100[diff] [blame]66 select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
Subrata Banikece173c2017-12-14 18:18:34 +0530[diff] [blame]67 select SOC_INTEL_COMMON_BLOCK_SMM
68 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banikafa07f72018-05-24 12:21:06 +0530[diff] [blame]69 select SOC_INTEL_COMMON_BLOCK_UART
Karthikeyan Ramasubramaniancc7cdb12019-03-20 11:38:01 -0600[diff] [blame]70 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Subrata Banikf513ceb2018-05-17 15:57:43 +0530[diff] [blame]71 select SOC_INTEL_COMMON_PCH_BASE
Aaron Durbinc14a1a92016-06-28 15:41:07 -0500[diff] [blame]72 select SOC_INTEL_COMMON_NHLT
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]73 select SOC_INTEL_COMMON_RESET
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]74 select SSE2
75 select SUPPORT_CPU_UCODE_IN_CBFS
Aamir Bohra842776e2017-05-25 14:12:01 +0530[diff] [blame]76 select TSC_MONOTONIC_TIMER
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]77 select TSC_SYNC_MFENCE
78 select UDELAY_TSC
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]79 select UDK_2015_BINDING
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]80
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]81config FSP_HYPERTHREADING
82 bool "Enable Hyper-Threading"
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]83 default y
84
Arthur Heymans27d3f712018-01-05 17:51:46 +0100[diff] [blame]85config CPU_INTEL_NUM_FIT_ENTRIES
86 int
87 default 10
88
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]89config CHROMEOS
90 select CHROMEOS_RAMOOPS_DYNAMIC
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]91
92config VBOOT
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]93 select VBOOT_SEPARATE_VERSTAGE
Joel Kitching6672bd82019-04-10 16:06:21 +0800[diff] [blame]94 select VBOOT_MUST_REQUEST_DISPLAY
Furquan Shaikhb8257df2016-07-22 09:20:56 -0700[diff] [blame]95 select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
Aaron Durbina6914d22016-08-24 08:49:29 -0500[diff] [blame]96 select VBOOT_STARTS_IN_BOOTBLOCK
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -0700[diff] [blame]97 select VBOOT_VBNV_CMOS
98 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]99
Martin Roth59ff3402016-02-09 09:06:46 -0700[diff] [blame]100config CBFS_SIZE
101 hex
102 default 0x200000
103
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]104config DCACHE_RAM_BASE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]105 hex
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]106 default 0xfef00000
107
108config DCACHE_RAM_SIZE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]109 hex
Rizwan Qureshi3ad63562016-08-14 15:48:33 +0530[diff] [blame]110 default 0x40000
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]111 help
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]112 The size of the cache-as-ram region required during bootblock
113 and/or romstage.
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]114
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]115config DCACHE_BSP_STACK_SIZE
116 hex
117 default 0x4000
118 help
119 The amount of anticipated stack usage in CAR by bootblock and
120 other stages.
121
122config C_ENV_BOOTBLOCK_SIZE
123 hex
Furquan Shaikh70385962016-08-24 10:28:30 -0700[diff] [blame]124 default 0xC000
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]125
Subrata Banik086730b2015-12-02 11:42:04 +0530[diff] [blame]126config EXCLUDE_NATIVE_SD_INTERFACE
127 bool
128 default n
129 help
130 If you set this option to n, will not use native SD controller.
131
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]132config HEAP_SIZE
133 hex
134 default 0x80000
135
136config IED_REGION_SIZE
137 hex
138 default 0x400000
139
Subrata Banike7ceae72017-03-08 17:59:40 +0530[diff] [blame]140config PCR_BASE_ADDRESS
141 hex
142 default 0xfd000000
143 help
144 This option allows you to select MMIO Base Address of sideband bus.
145
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]146config SMM_RESERVED_SIZE
147 hex
148 default 0x200000
149
150config SMM_TSEG_SIZE
151 hex
152 default 0x800000
153
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]154config VGA_BIOS_ID
155 string
156 default "8086,0406"
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]157
Teo Boon Tiong2fc06c82016-09-15 11:11:45 +0800[diff] [blame]158config SKYLAKE_SOC_PCH_H
159 bool
160 default n
161 help
162 Choose this option if you have a PCH-H chipset.
163
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]164config NHLT_DMIC_2CH
165 bool
166 default n
167 help
168 Include DSP firmware settings for 2 channel DMIC array.
169
170config NHLT_DMIC_4CH
171 bool
172 default n
173 help
174 Include DSP firmware settings for 4 channel DMIC array.
175
176config NHLT_NAU88L25
177 bool
178 default n
179 help
180 Include DSP firmware settings for nau88l25 headset codec.
181
182config NHLT_MAX98357
183 bool
184 default n
185 help
186 Include DSP firmware settings for max98357 amplifier.
187
Duncan Lauriee6c8a382018-03-26 02:45:02 -0700[diff] [blame]188config NHLT_MAX98373
189 bool
190 default n
191 help
192 Include DSP firmware settings for max98373 amplifier.
193
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]194config NHLT_SSM4567
195 bool
196 default n
197 help
198 Include DSP firmware settings for ssm4567 smart amplifier.
199
Duncan Laurie4a75a662017-03-02 10:13:51 -0800[diff] [blame]200config NHLT_RT5514
201 bool
202 default n
203 help
204 Include DSP firmware settings for rt5514 DSP.
205
Rizwan Qureshi17335fa2017-01-14 06:08:21 +0530[diff] [blame]206config NHLT_RT5663
207 bool
208 default n
209 help
210 Include DSP firmware settings for rt5663 headset codec.
211
212config NHLT_MAX98927
213 bool
214 default n
215 help
216 Include DSP firmware settings for max98927 amplifier.
217
Naveen Manohar83670c52017-11-04 02:55:09 +0530[diff] [blame]218config NHLT_DA7219
219 bool
220 default n
221 help
222 Include DSP firmware settings for DA7219 headset codec.
223
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]224config FSP_HEADER_PATH
Patrick Georgic6382cd2018-10-26 22:03:17 +0200[diff] [blame]225 string "Location of FSP headers"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]226 # Use KabylakeFsp for both Skylake and Kabylake as it supports both.
227 # SkylakeFsp is FSP 1.1 and therefore incompatible.
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]228 default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]229
230config FSP_FD_PATH
231 string
232 depends on FSP_USE_REPO
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]233 default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]234
Aaron Durbine56191e2016-08-11 09:50:49 -0500[diff] [blame]235config SPI_FLASH_INCLUDE_ALL_DRIVERS
236 bool
237 default n
238
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]239config MAX_ROOT_PORTS
240 int
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]241 default 24
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]242
Jenny TC2864f852017-02-09 16:01:59 +0530[diff] [blame]243config NO_FADT_8042
244 bool
245 default n
246 help
247 Choose this option if you want to disable 8042 Keyboard
248
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]249config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Furquan Shaikh340908a2017-04-04 11:47:19 -0700[diff] [blame]250 int
251 default 120
252
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]253config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
254 int
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]255 default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]256
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]257config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
258 int
259 default 2
260
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]261config SOC_INTEL_I2C_DEV_MAX
262 int
263 default 6
264
Aamir Bohra1041d392017-06-02 11:56:14 +0530[diff] [blame]265config CPU_BCLK_MHZ
266 int
267 default 100
268
Nico Huber99954182019-05-29 23:33:06 +0200[diff] [blame]269config CONSOLE_UART_BASE_ADDRESS
270 hex
271 default 0xfe030000
272 depends on INTEL_LPSS_UART_FOR_CONSOLE
273
Furquan Shaikh3406dd62017-08-04 15:58:26 -0700[diff] [blame]274# Clock divider parameters for 115200 baud rate
275config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
276 hex
277 default 0x30
278
279config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
280 hex
281 default 0xc35
282
Furquan Shaikha3ad9902018-03-21 10:45:08 -0700[diff] [blame]283config IFD_CHIPSET
284 string
285 default "sklkbl"
286
Patrick Rudolph5fffb5e2019-07-25 11:55:30 +0200[diff] [blame]287config INTEL_TXT_BIOSACM_ALIGNMENT
288 hex
289 default 0x40000 # 256KB
290
Wim Vervoorn2ab4f4b2019-10-23 10:22:06 +0200[diff] [blame]291config MAINBOARD_SUPPORTS_SKYLAKE_CPU
292 bool "Board can contain Skylake CPU"
293 default y
294
295if SKYLAKE_SOC_PCH_H
296
297config MAINBOARD_SUPPORTS_KABYLAKE_CPU
298 bool "Board can contain Kaby Lake CPU"
299 default y if SOC_INTEL_KABYLAKE
300
301endif
302
303if !SKYLAKE_SOC_PCH_H
304
305config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
306 bool "Board can contain Kaby Lake DUAL core"
307 default y
308
309config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
310 bool "Board can contain Kaby Lake QUAD core"
311 default y
312
313endif
314
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]315endif