Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame^] | 1 | config SOC_INTEL_SKYLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Skylake support |
| 5 | |
| 6 | if SOC_INTEL_SKYLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ARCH_BOOTBLOCK_X86_32 |
| 11 | select ARCH_VERSTAGE_X86_32 |
| 12 | select ARCH_ROMSTAGE_X86_32 |
| 13 | select ARCH_RAMSTAGE_X86_32 |
| 14 | select ALT_CBFS_LOAD_PAYLOAD |
| 15 | select ALWAYS_LOAD_OPROM |
| 16 | select BACKUP_DEFAULT_SMM_REGION |
| 17 | select CACHE_MRC_BIN |
| 18 | select CACHE_MRC_SETTINGS |
| 19 | select MRC_SETTINGS_PROTECT |
| 20 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
| 21 | select CACHE_ROM |
| 22 | select CAR_MIGRATION |
| 23 | select COLLECT_TIMESTAMPS |
| 24 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 25 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 26 | select HAVE_MONOTONIC_TIMER |
| 27 | select HAVE_SMI_HANDLER |
| 28 | select HAVE_HARD_RESET |
| 29 | select HAVE_USBDEBUG |
| 30 | select IOAPIC |
| 31 | select MMCONF_SUPPORT |
| 32 | select MMCONF_SUPPORT_DEFAULT |
| 33 | select RELOCATABLE_MODULES |
| 34 | select RELOCATABLE_RAMSTAGE |
| 35 | select REG_SCRIPT |
| 36 | select PARALLEL_MP |
| 37 | select PCIEXP_ASPM |
| 38 | select PCIEXP_COMMON_CLOCK |
| 39 | select PCIEXP_CLK_PM |
| 40 | select PCIEXP_L1_SUB_STATE |
| 41 | select SMM_MODULES |
| 42 | select SMM_TSEG |
| 43 | select SMP |
| 44 | select SPI_FLASH |
| 45 | select SSE2 |
| 46 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 47 | select TSC_CONSTANT_RATE |
| 48 | select TSC_SYNC_MFENCE |
| 49 | select UDELAY_TSC |
| 50 | select PER_DEVICE_ACPI_TABLES |
| 51 | select SOC_INTEL_COMMON |
| 52 | |
| 53 | config BOOTBLOCK_CPU_INIT |
| 54 | string |
| 55 | default "soc/intel/skylake/bootblock/cpu.c" |
| 56 | |
| 57 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 58 | string |
| 59 | default "soc/intel/skylake/bootblock/systemagent.c" |
| 60 | |
| 61 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 62 | string |
| 63 | default "soc/intel/skylake/bootblock/pch.c" |
| 64 | |
| 65 | |
| 66 | config MMCONF_BASE_ADDRESS |
| 67 | hex |
| 68 | default 0xf0000000 |
| 69 | |
| 70 | config SERIAL_CPU_INIT |
| 71 | bool |
| 72 | default n |
| 73 | |
| 74 | config SMM_TSEG_SIZE |
| 75 | hex |
| 76 | default 0x800000 |
| 77 | |
| 78 | config IED_REGION_SIZE |
| 79 | hex |
| 80 | default 0x400000 |
| 81 | |
| 82 | config SMM_RESERVED_SIZE |
| 83 | hex |
| 84 | default 0x100000 |
| 85 | |
| 86 | config VGA_BIOS_ID |
| 87 | string |
| 88 | default "8086,0406" |
| 89 | |
| 90 | config CACHE_MRC_SIZE_KB |
| 91 | int |
| 92 | default 512 |
| 93 | |
| 94 | config DCACHE_RAM_BASE |
| 95 | hex |
| 96 | default 0xff7c0000 |
| 97 | |
| 98 | config DCACHE_RAM_SIZE |
| 99 | hex |
| 100 | default 0x10000 |
| 101 | help |
| 102 | The size of the cache-as-ram region required during bootblock |
| 103 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 104 | must add up to a power of 2. |
| 105 | |
| 106 | config DCACHE_RAM_MRC_VAR_SIZE |
| 107 | hex |
| 108 | default 0x30000 |
| 109 | help |
| 110 | The amount of cache-as-ram region required by the reference code. |
| 111 | |
| 112 | config DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 113 | hex |
| 114 | default 0x2000 |
| 115 | help |
| 116 | The amount of anticipated stack usage from the data cache |
| 117 | during pre-ram rom stage execution. |
| 118 | |
| 119 | config HAVE_MRC |
| 120 | bool "Add a Memory Reference Code binary" |
| 121 | help |
| 122 | Select this option to add a Memory Reference Code binary to |
| 123 | the resulting coreboot image. |
| 124 | |
| 125 | Note: Without this binary coreboot will not work |
| 126 | |
| 127 | if HAVE_MRC |
| 128 | |
| 129 | config MRC_FILE |
| 130 | string "Intel Memory Reference Code path and filename" |
| 131 | depends on HAVE_MRC |
| 132 | default "mrc.bin" |
| 133 | help |
| 134 | The filename of the file to use as Memory Reference Code binary. |
| 135 | |
| 136 | config MRC_BIN_ADDRESS |
| 137 | hex |
| 138 | default 0xfffa0000 |
| 139 | |
| 140 | config CACHE_MRC_SETTINGS |
| 141 | bool "Save cached MRC settings" |
| 142 | default y |
| 143 | |
| 144 | endif # HAVE_MRC |
| 145 | |
| 146 | config CBFS_SIZE |
| 147 | hex "Size of CBFS filesystem in ROM" |
| 148 | default 0x100000 |
| 149 | help |
| 150 | The firmware image has to store more than just coreboot, including: |
| 151 | - a firmware descriptor |
| 152 | - Intel Management Engine firmware |
| 153 | - MRC cache information |
| 154 | This option allows to limit the size of the CBFS portion in the |
| 155 | firmware image. |
| 156 | |
| 157 | config PRE_GRAPHICS_DELAY |
| 158 | int "Graphics initialization delay in ms" |
| 159 | default 0 |
| 160 | help |
| 161 | On some systems, coreboot boots so fast that connected monitors |
| 162 | (mostly TVs) won't be able to wake up fast enough to talk to the |
| 163 | VBIOS. On those systems we need to wait for a bit before executing |
| 164 | the VBIOS. |
| 165 | |
| 166 | config RESET_ON_INVALID_RAMSTAGE_CACHE |
| 167 | bool "Reset the system on S3 wake when ramstage cache invalid." |
| 168 | default n |
| 169 | depends on RELOCATABLE_RAMSTAGE |
| 170 | help |
| 171 | The romstage code caches the loaded ramstage program in SMM space. |
| 172 | On S3 wake the romstage will copy over a fresh ramstage that was |
| 173 | cached in the SMM space. This option determines the action to take |
| 174 | when the ramstage cache is invalid. If selected the system will |
| 175 | reset otherwise the ramstage will be reloaded from cbfs. |
| 176 | |
| 177 | config INTEL_PCH_UART_CONSOLE |
| 178 | bool "Use Serial IO UART for console" |
| 179 | default n |
| 180 | select HAVE_UART_MEMORY_MAPPED |
| 181 | select CONSOLE_SERIAL8250MEM |
| 182 | depends on !CONFIG_DRIVERS_OXFORD_OXPCIE |
| 183 | |
| 184 | config INTEL_PCH_UART_CONSOLE_NUMBER |
| 185 | hex "Serial IO UART number to use for console" |
| 186 | default "0x0" |
| 187 | depends on INTEL_PCH_UART_CONSOLE |
| 188 | |
| 189 | config TTYS0_BASE |
| 190 | hex |
| 191 | default 0xd6000000 |
| 192 | depends on INTEL_PCH_UART_CONSOLE |
| 193 | |
| 194 | config EHCI_BAR |
| 195 | hex |
| 196 | default 0xd8000000 |
| 197 | |
| 198 | config EHCI_DEBUG_OFFSET |
| 199 | hex |
| 200 | default 0xa0 |
| 201 | |
| 202 | config SERIRQ_CONTINUOUS_MODE |
| 203 | bool |
| 204 | default y |
| 205 | help |
| 206 | If you set this option to y, the serial IRQ machine will be |
| 207 | operated in continuous mode. |
| 208 | config HAVE_ME_BIN |
| 209 | bool "Add Intel Management Engine firmware" |
| 210 | default y |
| 211 | help |
| 212 | The Intel processor in the selected system requires a special firmware |
| 213 | for an integrated controller called Management Engine (ME). The ME |
| 214 | firmware might be provided in coreboot's 3rdparty/blobs repository. If |
| 215 | not and if you don't have the firmware elsewhere, you can still |
| 216 | build coreboot without it. In this case however, you'll have to make |
| 217 | sure that you don't overwrite your ME firmware on your flash ROM. |
| 218 | |
| 219 | config ME_BIN_PATH |
| 220 | string "Path to management engine firmware" |
| 221 | depends on HAVE_ME_BIN |
| 222 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" |
| 223 | |
| 224 | config HAVE_IFD_BIN |
| 225 | bool "Use Intel Firmware Descriptor from existing binary" |
| 226 | default n |
| 227 | |
| 228 | config BUILD_WITH_FAKE_IFD |
| 229 | bool "Build with a fake IFD" |
| 230 | default y if !HAVE_IFD_BIN |
| 231 | help |
| 232 | If you don't have an Intel Firmware Descriptor (ifd.bin) for your |
| 233 | board, you can select this option and coreboot will build without it. |
| 234 | Though, the resulting coreboot.rom will not contain all parts required |
| 235 | to get coreboot running on your board. You can however write only the |
| 236 | BIOS section to your board's flash ROM and keep the other sections |
| 237 | untouched. Unfortunately the current version of flashrom doesn't |
| 238 | support this yet. But there is a patch pending [1]. |
| 239 | |
| 240 | WARNING: Never write a complete coreboot.rom to your flash ROM if it |
| 241 | was built with a fake IFD. It just won't work. |
| 242 | |
| 243 | [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html |
| 244 | |
| 245 | config IFD_BIOS_SECTION |
| 246 | depends on BUILD_WITH_FAKE_IFD |
| 247 | string |
| 248 | default "" |
| 249 | |
| 250 | config IFD_ME_SECTION |
| 251 | depends on BUILD_WITH_FAKE_IFD |
| 252 | string |
| 253 | default "" |
| 254 | |
| 255 | config IFD_PLATFORM_SECTION |
| 256 | depends on BUILD_WITH_FAKE_IFD |
| 257 | string |
| 258 | default "" |
| 259 | |
| 260 | config IFD_BIN_PATH |
| 261 | string "Path to intel firmware descriptor" |
| 262 | depends on !BUILD_WITH_FAKE_IFD |
| 263 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
| 264 | |
| 265 | config LOCK_MANAGEMENT_ENGINE |
| 266 | bool "Lock Management Engine section" |
| 267 | default n |
| 268 | help |
| 269 | The Intel Management Engine supports preventing write accesses |
| 270 | from the host to the Management Engine section in the firmware |
| 271 | descriptor. If the ME section is locked, it can only be overwritten |
| 272 | with an external SPI flash programmer. You will want this if you |
| 273 | want to increase security of your ROM image once you are sure |
| 274 | that the ME firmware is no longer going to change. |
| 275 | |
| 276 | If unsure, say N. |
| 277 | |
| 278 | endif |