soc/intel/lpss: Provide common LPSS clock config
Since there are multiple controllers in the LPSS and all use the same
frequency, provide a single Kconfig option for LPSS_CLOCK_MHZ.
BUG=b:35583330
Change-Id: I3c0cb62d56916e6e5f671fb5f40210f4cb33316f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 8ac7263..df8ae2b 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -109,10 +109,6 @@
int
default 36
-config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
- int
- default 120
-
config DCACHE_RAM_BASE
hex "Base address of cache-as-RAM"
default 0xfef00000
@@ -300,4 +296,8 @@
help
Choose this option if you want to disable 8042 Keyboard
+config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+ int
+ default 120
+
endif