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review.coreboot.org / coreboot / fce36e448dcb6346e270bcfa4ec97df09188808e / . / src / soc / intel / skylake / Kconfig
blob: a7e25b126cc7df1e02590c821dfc0d0d1f6a5b4c [file] [log] [blame]
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]1config SOC_INTEL_COMMON_SKYLAKE_BASE
2 bool
3
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]4config SOC_INTEL_SKYLAKE
5 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]6 select SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]7 help
8 Intel Skylake support
9
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]10config SOC_INTEL_KABYLAKE
11 bool
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]12 select SOC_INTEL_COMMON_SKYLAKE_BASE
Rizwan Qureshi0700dca2017-02-09 15:57:45 +0530[diff] [blame]13 help
14 Intel Kabylake support
15
Arthur Heymans4c7979a2019-06-17 14:30:10 +0200[diff] [blame]16if SOC_INTEL_COMMON_SKYLAKE_BASE
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]17
18config CPU_SPECIFIC_OPTIONS
19 def_bool y
Aaron Durbine0a49142016-07-13 23:20:51 -0500[diff] [blame]20 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]21 select ACPI_NHLT
Angel Ponsa32df262020-09-25 10:20:11 +0200[diff] [blame]22 select ARCH_ALL_STAGES_X86_32
Aaron Durbine8e118d2016-08-12 15:00:10 -0500[diff] [blame]23 select BOOT_DEVICE_SUPPORTS_WRITES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]24 select CACHE_MRC_SETTINGS
Nico Huber6275e342018-11-21 00:11:35 +0100[diff] [blame]25 select CPU_INTEL_COMMON
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]26 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
Michael Niewöhnerfe6070f2020-10-04 15:16:04 +0200[diff] [blame]27 select CPU_SUPPORTS_PM_TIMER_EMULATION
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]28 select FSP_M_XIP
Subrata Banik4ed9f9a2020-10-31 22:01:55 +0530[diff] [blame]29 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
Aaron Durbinffdf9012015-07-24 13:00:36 -0500[diff] [blame]30 select GENERIC_GPIO_LIB
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]31 select HAVE_FSP_GOP
Wim Vervoornd1371502019-12-17 14:10:16 +0100[diff] [blame]32 select HAVE_FSP_LOGO_SUPPORT
Felix Singerbd7020d2020-12-06 11:32:25 +0100[diff] [blame]33 select HAVE_INTEL_FSP_REPO
Shreesh Chhabbi87c7ec72020-12-03 14:07:15 -0800[diff] [blame]34 select INTEL_CAR_NEM_ENHANCED
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]35 select HAVE_SMI_HANDLER
Felix Singerbd7020d2020-12-06 11:32:25 +0100[diff] [blame]36 select INTEL_DESCRIPTOR_MODE_CAPABLE
Patrick Rudolphc7edf182017-09-26 19:34:35 +0200[diff] [blame]37 select INTEL_GMA_ACPI
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]38 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]39 select IOAPIC
Duncan Laurie205ed2d2016-06-02 15:23:42 -0700[diff] [blame]40 select MRC_SETTINGS_PROTECT
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]41 select PARALLEL_MP
Furquan Shaikha5853582017-05-06 12:40:15 -0700[diff] [blame]42 select PARALLEL_MP_AP_WORK
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]43 select PLATFORM_USES_FSP2_0
Michael Niewöhnera1843d82020-10-02 18:28:22 +0200[diff] [blame]44 select PM_ACPI_TIMER_OPTIONAL
Julien Viard de Galbert2912e8e2018-08-14 16:15:26 +0200[diff] [blame]45 select PMC_GLOBAL_RESET_ENABLE_LOCK
Felix Singerbd7020d2020-12-06 11:32:25 +0100[diff] [blame]46 select REG_SCRIPT
47 select SA_ENABLE_DPR
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]48 select SOC_INTEL_COMMON
Duncan Lauriea1c8b34d2015-09-08 16:12:44 -0700[diff] [blame]49 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banike074d622017-02-16 16:16:37 +0530[diff] [blame]50 select SOC_INTEL_COMMON_BLOCK
Michael Niewöhner11fae4f2021-01-01 21:23:52 +0100[diff] [blame]51 select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
Nico Huber2f1ef982018-11-07 16:24:50 +0100[diff] [blame]52 select SOC_INTEL_COMMON_BLOCK_CAR
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]53 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
Barnali Sarkar0a203d12017-05-04 18:02:17 +0530[diff] [blame]54 select SOC_INTEL_COMMON_BLOCK_CPU
Barnali Sarkar73273862017-06-13 20:22:33 +0530[diff] [blame]55 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
Furquan Shaikh2c368892018-10-18 16:22:37 -0700[diff] [blame]56 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
Vadim Bendebury5542bb62018-02-05 19:59:09 -0800[diff] [blame]57 select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]58 select SOC_INTEL_COMMON_BLOCK_GSPI
Furquan Shaikh31bff012018-09-29 23:31:04 -0700[diff] [blame]59 select SOC_INTEL_COMMON_BLOCK_HDA
Arthur Heymans1ae8cd12020-11-19 13:59:53 +0100[diff] [blame]60 select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
Subrata Banik93ebe492017-03-14 18:24:47 +0530[diff] [blame]61 select SOC_INTEL_COMMON_BLOCK_SA
Duncan Laurie1e066112020-04-08 11:35:52 -0700[diff] [blame]62 select SOC_INTEL_COMMON_BLOCK_SCS
Pratik Prajapatia04aa3d2017-06-12 23:02:36 -0700[diff] [blame]63 select SOC_INTEL_COMMON_BLOCK_SGX
Michael Niewöhnerc169a472019-10-31 19:01:23 +0100[diff] [blame]64 select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
Subrata Banikece173c2017-12-14 18:18:34 +0530[diff] [blame]65 select SOC_INTEL_COMMON_BLOCK_SMM
66 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
Subrata Banik2fff3912020-01-16 10:13:28 +0530[diff] [blame]67 select SOC_INTEL_COMMON_BLOCK_THERMAL
Subrata Banikafa07f72018-05-24 12:21:06 +0530[diff] [blame]68 select SOC_INTEL_COMMON_BLOCK_UART
Karthikeyan Ramasubramaniancc7cdb12019-03-20 11:38:01 -0600[diff] [blame]69 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
Subrata Banik4ed9f9a2020-10-31 22:01:55 +0530[diff] [blame]70 select SOC_INTEL_COMMON_FSP_RESET
Subrata Banikf513ceb2018-05-17 15:57:43 +0530[diff] [blame]71 select SOC_INTEL_COMMON_PCH_BASE
Aaron Durbinc14a1a92016-06-28 15:41:07 -0500[diff] [blame]72 select SOC_INTEL_COMMON_NHLT
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]73 select SOC_INTEL_COMMON_RESET
Sumeet R Pawnikar97c54642020-05-10 01:24:11 +0530[diff] [blame]74 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
Nico Huberdd274e22020-04-26 20:37:32 +0200[diff] [blame]75 select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]76 select SSE2
77 select SUPPORT_CPU_UCODE_IN_CBFS
Aamir Bohra842776e2017-05-25 14:12:01 +0530[diff] [blame]78 select TSC_MONOTONIC_TIMER
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]79 select TSC_SYNC_MFENCE
80 select UDELAY_TSC
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]81 select UDK_2015_BINDING
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]82
Felix Singer9a6a18e2021-01-04 22:10:26 +0000[diff] [blame]83config MAX_CPUS
84 int
85 default 8
86
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]87config FSP_HYPERTHREADING
88 bool "Enable Hyper-Threading"
Patrick Rudolph203061c2019-09-02 09:35:21 +0200[diff] [blame]89 default y
90
Arthur Heymans27d3f712018-01-05 17:51:46 +0100[diff] [blame]91config CPU_INTEL_NUM_FIT_ENTRIES
92 int
93 default 10
94
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]95config VBOOT
Julius Werner58c39382017-02-13 17:53:29 -0800[diff] [blame]96 select VBOOT_SEPARATE_VERSTAGE
Joel Kitching6672bd82019-04-10 16:06:21 +0800[diff] [blame]97 select VBOOT_MUST_REQUEST_DISPLAY
Aaron Durbina6914d22016-08-24 08:49:29 -0500[diff] [blame]98 select VBOOT_STARTS_IN_BOOTBLOCK
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -0700[diff] [blame]99 select VBOOT_VBNV_CMOS
100 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Furquan Shaikh610a33a2016-07-22 16:17:53 -0700[diff] [blame]101
Martin Roth59ff3402016-02-09 09:06:46 -0700[diff] [blame]102config CBFS_SIZE
103 hex
104 default 0x200000
105
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]106config DCACHE_RAM_BASE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]107 hex
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]108 default 0xfef00000
109
110config DCACHE_RAM_SIZE
Arthur Heymans432ac612017-06-13 14:17:05 +0200[diff] [blame]111 hex
Rizwan Qureshi3ad63562016-08-14 15:48:33 +0530[diff] [blame]112 default 0x40000
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]113 help
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]114 The size of the cache-as-ram region required during bootblock
115 and/or romstage.
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]116
Subrata Banik68d5d8b2016-07-18 14:13:52 +0530[diff] [blame]117config DCACHE_BSP_STACK_SIZE
118 hex
119 default 0x4000
120 help
121 The amount of anticipated stack usage in CAR by bootblock and
122 other stages.
123
Subrata Banik086730b2015-12-02 11:42:04 +0530[diff] [blame]124config EXCLUDE_NATIVE_SD_INTERFACE
125 bool
126 default n
127 help
128 If you set this option to n, will not use native SD controller.
129
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]130config HEAP_SIZE
131 hex
132 default 0x80000
133
134config IED_REGION_SIZE
135 hex
136 default 0x400000
137
Subrata Banike7ceae72017-03-08 17:59:40 +0530[diff] [blame]138config PCR_BASE_ADDRESS
139 hex
140 default 0xfd000000
141 help
142 This option allows you to select MMIO Base Address of sideband bus.
143
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]144config SMM_RESERVED_SIZE
145 hex
146 default 0x200000
147
148config SMM_TSEG_SIZE
149 hex
150 default 0x800000
151
Lee Leahy1d14b3e2015-05-12 18:23:27 -0700[diff] [blame]152config VGA_BIOS_ID
153 string
154 default "8086,0406"
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]155
Teo Boon Tiong2fc06c82016-09-15 11:11:45 +0800[diff] [blame]156config SKYLAKE_SOC_PCH_H
157 bool
158 default n
159 help
160 Choose this option if you have a PCH-H chipset.
161
Benjamin Doroneecaf362020-08-04 06:45:46 +0000[diff] [blame]162config NHLT_DMIC_1CH
163 bool
164 default n
165 help
166 Include DSP firmware settings for 1 channel DMIC array.
167
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]168config NHLT_DMIC_2CH
169 bool
170 default n
171 help
172 Include DSP firmware settings for 2 channel DMIC array.
173
174config NHLT_DMIC_4CH
175 bool
176 default n
177 help
178 Include DSP firmware settings for 4 channel DMIC array.
179
180config NHLT_NAU88L25
181 bool
182 default n
183 help
184 Include DSP firmware settings for nau88l25 headset codec.
185
186config NHLT_MAX98357
187 bool
188 default n
189 help
190 Include DSP firmware settings for max98357 amplifier.
191
Duncan Lauriee6c8a382018-03-26 02:45:02 -0700[diff] [blame]192config NHLT_MAX98373
193 bool
194 default n
195 help
196 Include DSP firmware settings for max98373 amplifier.
197
Aaron Durbined8a7232015-11-24 12:35:06 -0600[diff] [blame]198config NHLT_SSM4567
199 bool
200 default n
201 help
202 Include DSP firmware settings for ssm4567 smart amplifier.
203
Duncan Laurie4a75a662017-03-02 10:13:51 -0800[diff] [blame]204config NHLT_RT5514
205 bool
206 default n
207 help
208 Include DSP firmware settings for rt5514 DSP.
209
Rizwan Qureshi17335fa2017-01-14 06:08:21 +0530[diff] [blame]210config NHLT_RT5663
211 bool
212 default n
213 help
214 Include DSP firmware settings for rt5663 headset codec.
215
216config NHLT_MAX98927
217 bool
218 default n
219 help
220 Include DSP firmware settings for max98927 amplifier.
221
Naveen Manohar83670c52017-11-04 02:55:09 +0530[diff] [blame]222config NHLT_DA7219
223 bool
224 default n
225 help
226 Include DSP firmware settings for DA7219 headset codec.
227
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]228config FSP_HEADER_PATH
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]229 # Use KabylakeFsp for both Skylake and Kabylake as it supports both.
230 # SkylakeFsp is FSP 1.1 and therefore incompatible.
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]231 default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]232
233config FSP_FD_PATH
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]234 default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
Patrick Georgi6539e102018-09-13 11:48:43 -0400[diff] [blame]235
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]236config MAX_ROOT_PORTS
237 int
Michael Niewöhner0f91f792019-10-05 19:47:47 +0200[diff] [blame]238 default 24
Rizwan Qureshid8bb69a2016-11-08 21:01:09 +0530[diff] [blame]239
Jenny TC2864f852017-02-09 16:01:59 +0530[diff] [blame]240config NO_FADT_8042
241 bool
242 default n
243 help
244 Choose this option if you want to disable 8042 Keyboard
245
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]246config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Furquan Shaikh340908a2017-04-04 11:47:19 -0700[diff] [blame]247 int
248 default 120
249
Michael Niewöhnerdadcbfb2020-10-04 14:48:05 +0200[diff] [blame]250config CPU_XTAL_HZ
251 default 24000000
252
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]253config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
254 int
Aaron Durbin551e4be2018-04-10 09:24:54 -0600[diff] [blame]255 default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Chris Chingb8dc63b2017-12-06 14:26:15 -0700[diff] [blame]256
Furquan Shaikh05a6f292017-03-31 14:02:47 -0700[diff] [blame]257config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
258 int
259 default 2
260
Subrata Banikc4986eb2018-05-09 14:55:09 +0530[diff] [blame]261config SOC_INTEL_I2C_DEV_MAX
262 int
263 default 6
264
Aamir Bohra1041d392017-06-02 11:56:14 +0530[diff] [blame]265config CPU_BCLK_MHZ
266 int
267 default 100
268
Nico Huber99954182019-05-29 23:33:06 +0200[diff] [blame]269config CONSOLE_UART_BASE_ADDRESS
270 hex
271 default 0xfe030000
272 depends on INTEL_LPSS_UART_FOR_CONSOLE
273
Furquan Shaikh3406dd62017-08-04 15:58:26 -0700[diff] [blame]274# Clock divider parameters for 115200 baud rate
275config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
276 hex
277 default 0x30
278
279config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
280 hex
281 default 0xc35
282
Felix Singer424467c2020-10-12 19:51:02 +0000[diff] [blame]283config CHIPSET_DEVICETREE
284 string
285 default "soc/intel/skylake/chipset.cb"
286
Furquan Shaikha3ad9902018-03-21 10:45:08 -0700[diff] [blame]287config IFD_CHIPSET
288 string
289 default "sklkbl"
290
Patrick Rudolph5fffb5e2019-07-25 11:55:30 +0200[diff] [blame]291config INTEL_TXT_BIOSACM_ALIGNMENT
292 hex
293 default 0x40000 # 256KB
294
Wim Vervoorn2ab4f4b2019-10-23 10:22:06 +0200[diff] [blame]295config MAINBOARD_SUPPORTS_SKYLAKE_CPU
296 bool "Board can contain Skylake CPU"
297 default y
298
299if SKYLAKE_SOC_PCH_H
300
301config MAINBOARD_SUPPORTS_KABYLAKE_CPU
302 bool "Board can contain Kaby Lake CPU"
303 default y if SOC_INTEL_KABYLAKE
304
305endif
306
307if !SKYLAKE_SOC_PCH_H
308
309config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
310 bool "Board can contain Kaby Lake DUAL core"
311 default y
312
313config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
314 bool "Board can contain Kaby Lake QUAD core"
315 default y
316
317endif
318
Lee Leahyb0005132015-05-12 18:19:47 -0700[diff] [blame]319endif