Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 1 | config SOC_INTEL_COMMON_SKYLAKE_BASE |
| 2 | bool |
| 3 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 4 | config SOC_INTEL_SKYLAKE |
| 5 | bool |
Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 6 | select SOC_INTEL_COMMON_SKYLAKE_BASE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 7 | |
Rizwan Qureshi | 0700dca | 2017-02-09 15:57:45 +0530 | [diff] [blame] | 8 | config SOC_INTEL_KABYLAKE |
| 9 | bool |
Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 10 | select SOC_INTEL_COMMON_SKYLAKE_BASE |
Rizwan Qureshi | 0700dca | 2017-02-09 15:57:45 +0530 | [diff] [blame] | 11 | |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 12 | config SOC_INTEL_SKYLAKE_LGA1151_V2 |
| 13 | bool |
| 14 | select PLATFORM_USES_FSP2_1 |
| 15 | select SOC_INTEL_COMMON_SKYLAKE_BASE |
| 16 | select SKYLAKE_SOC_PCH_H |
| 17 | help |
| 18 | Selected by mainboards with a LGA1151 v2 socket and a Z370, H310C or B365 PCH |
| 19 | |
Arthur Heymans | 4c7979a | 2019-06-17 14:30:10 +0200 | [diff] [blame] | 20 | if SOC_INTEL_COMMON_SKYLAKE_BASE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 21 | |
| 22 | config CPU_SPECIFIC_OPTIONS |
| 23 | def_bool y |
Aaron Durbin | e0a4914 | 2016-07-13 23:20:51 -0500 | [diff] [blame] | 24 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 25 | select ACPI_NHLT |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 26 | select ARCH_X86 |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 27 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 28 | select CACHE_MRC_SETTINGS |
Nico Huber | 6275e34 | 2018-11-21 00:11:35 +0100 | [diff] [blame] | 29 | select CPU_INTEL_COMMON |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 30 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 31 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Benjamin Doron | 27af8da | 2021-02-26 04:36:05 +0000 | [diff] [blame] | 32 | select FSP_COMPRESS_FSP_S_LZ4 |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 33 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 34 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Aaron Durbin | ffdf901 | 2015-07-24 13:00:36 -0500 | [diff] [blame] | 35 | select GENERIC_GPIO_LIB |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 36 | select HAVE_FSP_GOP |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 37 | select HAVE_FSP_LOGO_SUPPORT |
Felix Singer | bd7020d | 2020-12-06 11:32:25 +0100 | [diff] [blame] | 38 | select HAVE_INTEL_FSP_REPO |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 39 | select INTEL_CAR_NEM_ENHANCED |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 40 | select HAVE_SMI_HANDLER |
Felix Singer | bd7020d | 2020-12-06 11:32:25 +0100 | [diff] [blame] | 41 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Patrick Rudolph | c7edf18 | 2017-09-26 19:34:35 +0200 | [diff] [blame] | 42 | select INTEL_GMA_ACPI |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 43 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 44 | select IOAPIC |
Duncan Laurie | 205ed2d | 2016-06-02 15:23:42 -0700 | [diff] [blame] | 45 | select MRC_SETTINGS_PROTECT |
Furquan Shaikh | a585358 | 2017-05-06 12:40:15 -0700 | [diff] [blame] | 46 | select PARALLEL_MP_AP_WORK |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 47 | select PLATFORM_USES_FSP2_0 |
Michael Niewöhner | a1843d8 | 2020-10-02 18:28:22 +0200 | [diff] [blame] | 48 | select PM_ACPI_TIMER_OPTIONAL |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 49 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Felix Singer | bd7020d | 2020-12-06 11:32:25 +0100 | [diff] [blame] | 50 | select SA_ENABLE_DPR |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 51 | select SOC_INTEL_COMMON |
Duncan Laurie | a1c8b34d | 2015-09-08 16:12:44 -0700 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | e074d62 | 2017-02-16 16:16:37 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Michael Niewöhner | 11fae4f | 2021-01-01 21:23:52 +0100 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Tim Wawrzynczak | 277334e | 2021-07-01 09:04:06 -0600 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
Nico Huber | 2f1ef98 | 2018-11-07 16:24:50 +0100 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Barnali Sarkar | 0a203d1 | 2017-05-04 18:02:17 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_CPU |
Barnali Sarkar | 7327386 | 2017-06-13 20:22:33 +0530 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Furquan Shaikh | 2c36889 | 2018-10-18 16:22:37 -0700 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Vadim Bendebury | 5542bb6 | 2018-02-05 19:59:09 -0800 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_GSPI |
Furquan Shaikh | 31bff01 | 2018-09-29 23:31:04 -0700 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_HDA |
Arthur Heymans | 1ae8cd1 | 2020-11-19 13:59:53 +0100 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_SA |
Duncan Laurie | 1e06611 | 2020-04-08 11:35:52 -0700 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_SCS |
Pratik Prajapati | a04aa3d | 2017-06-12 23:02:36 -0700 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_BLOCK_SGX |
Michael Niewöhner | c169a47 | 2019-10-31 19:01:23 +0100 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY |
Subrata Banik | ece173c | 2017-12-14 18:18:34 +0530 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 72 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | 2fff391 | 2020-01-16 10:13:28 +0530 | [diff] [blame] | 73 | select SOC_INTEL_COMMON_BLOCK_THERMAL |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_BLOCK_UART |
Karthikeyan Ramasubramanian | cc7cdb1 | 2019-03-20 11:38:01 -0600 | [diff] [blame] | 75 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 76 | select SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | f513ceb | 2018-05-17 15:57:43 +0530 | [diff] [blame] | 77 | select SOC_INTEL_COMMON_PCH_BASE |
Aaron Durbin | c14a1a9 | 2016-06-28 15:41:07 -0500 | [diff] [blame] | 78 | select SOC_INTEL_COMMON_NHLT |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 79 | select SOC_INTEL_COMMON_RESET |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 80 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Nico Huber | dd274e2 | 2020-04-26 20:37:32 +0200 | [diff] [blame] | 81 | select SOC_INTEL_CONFIGURE_DDI_A_4_LANES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 82 | select SSE2 |
| 83 | select SUPPORT_CPU_UCODE_IN_CBFS |
Aamir Bohra | 842776e | 2017-05-25 14:12:01 +0530 | [diff] [blame] | 84 | select TSC_MONOTONIC_TIMER |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 85 | select TSC_SYNC_MFENCE |
| 86 | select UDELAY_TSC |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 87 | select UDK_2015_BINDING |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 88 | |
Felix Singer | 9a6a18e | 2021-01-04 22:10:26 +0000 | [diff] [blame] | 89 | config MAX_CPUS |
| 90 | int |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 91 | default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU |
Felix Singer | 9a6a18e | 2021-01-04 22:10:26 +0000 | [diff] [blame] | 92 | default 8 |
| 93 | |
Patrick Rudolph | 203061c | 2019-09-02 09:35:21 +0200 | [diff] [blame] | 94 | config FSP_HYPERTHREADING |
| 95 | bool "Enable Hyper-Threading" |
Patrick Rudolph | 203061c | 2019-09-02 09:35:21 +0200 | [diff] [blame] | 96 | default y |
| 97 | |
Angel Pons | 8f3e119 | 2021-04-04 16:20:54 +0200 | [diff] [blame] | 98 | config ENABLE_SATA_TEST_MODE |
| 99 | bool "Enable SATA test mode" |
| 100 | default n |
| 101 | help |
| 102 | Enable SATA test mode in FSP-S. |
| 103 | |
Arthur Heymans | 27d3f71 | 2018-01-05 17:51:46 +0100 | [diff] [blame] | 104 | config CPU_INTEL_NUM_FIT_ENTRIES |
| 105 | int |
| 106 | default 10 |
| 107 | |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 108 | config VBOOT |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 109 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 110 | select VBOOT_MUST_REQUEST_DISPLAY |
Aaron Durbin | a6914d2 | 2016-08-24 08:49:29 -0500 | [diff] [blame] | 111 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 112 | select VBOOT_VBNV_CMOS |
| 113 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 114 | |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 115 | config CBFS_SIZE |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 116 | default 0x200000 |
| 117 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 118 | config DCACHE_RAM_BASE |
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 119 | hex |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 120 | default 0xfef00000 |
| 121 | |
| 122 | config DCACHE_RAM_SIZE |
Arthur Heymans | 432ac61 | 2017-06-13 14:17:05 +0200 | [diff] [blame] | 123 | hex |
Rizwan Qureshi | 3ad6356 | 2016-08-14 15:48:33 +0530 | [diff] [blame] | 124 | default 0x40000 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 125 | help |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 126 | The size of the cache-as-ram region required during bootblock |
| 127 | and/or romstage. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 128 | |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 129 | config DCACHE_BSP_STACK_SIZE |
| 130 | hex |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 131 | default 0x20400 if FSP_USES_CB_STACK |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 132 | default 0x4000 |
| 133 | help |
| 134 | The amount of anticipated stack usage in CAR by bootblock and |
| 135 | other stages. |
| 136 | |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 137 | config FSP_TEMP_RAM_SIZE |
| 138 | hex |
| 139 | depends on FSP_USES_CB_STACK |
| 140 | default 0x10000 |
| 141 | help |
| 142 | The amount of anticipated heap usage in CAR by FSP. |
| 143 | Refer to Platform FSP integration guide document to know |
| 144 | the exact FSP requirement for Heap setup. |
| 145 | |
Subrata Banik | 086730b | 2015-12-02 11:42:04 +0530 | [diff] [blame] | 146 | config EXCLUDE_NATIVE_SD_INTERFACE |
| 147 | bool |
| 148 | default n |
| 149 | help |
| 150 | If you set this option to n, will not use native SD controller. |
| 151 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 152 | config HEAP_SIZE |
| 153 | hex |
| 154 | default 0x80000 |
| 155 | |
| 156 | config IED_REGION_SIZE |
| 157 | hex |
| 158 | default 0x400000 |
| 159 | |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 160 | config PCR_BASE_ADDRESS |
| 161 | hex |
| 162 | default 0xfd000000 |
| 163 | help |
| 164 | This option allows you to select MMIO Base Address of sideband bus. |
| 165 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 166 | config SMM_RESERVED_SIZE |
| 167 | hex |
| 168 | default 0x200000 |
| 169 | |
| 170 | config SMM_TSEG_SIZE |
| 171 | hex |
| 172 | default 0x800000 |
| 173 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 174 | config VGA_BIOS_ID |
| 175 | string |
| 176 | default "8086,0406" |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 177 | |
Teo Boon Tiong | 2fc06c8 | 2016-09-15 11:11:45 +0800 | [diff] [blame] | 178 | config SKYLAKE_SOC_PCH_H |
| 179 | bool |
| 180 | default n |
Teo Boon Tiong | 2fc06c8 | 2016-09-15 11:11:45 +0800 | [diff] [blame] | 181 | |
Benjamin Doron | eecaf36 | 2020-08-04 06:45:46 +0000 | [diff] [blame] | 182 | config NHLT_DMIC_1CH |
| 183 | bool |
| 184 | default n |
| 185 | help |
| 186 | Include DSP firmware settings for 1 channel DMIC array. |
| 187 | |
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 188 | config NHLT_DMIC_2CH |
| 189 | bool |
| 190 | default n |
| 191 | help |
| 192 | Include DSP firmware settings for 2 channel DMIC array. |
| 193 | |
| 194 | config NHLT_DMIC_4CH |
| 195 | bool |
| 196 | default n |
| 197 | help |
| 198 | Include DSP firmware settings for 4 channel DMIC array. |
| 199 | |
| 200 | config NHLT_NAU88L25 |
| 201 | bool |
| 202 | default n |
| 203 | help |
| 204 | Include DSP firmware settings for nau88l25 headset codec. |
| 205 | |
| 206 | config NHLT_MAX98357 |
| 207 | bool |
| 208 | default n |
| 209 | help |
| 210 | Include DSP firmware settings for max98357 amplifier. |
| 211 | |
Duncan Laurie | e6c8a38 | 2018-03-26 02:45:02 -0700 | [diff] [blame] | 212 | config NHLT_MAX98373 |
| 213 | bool |
| 214 | default n |
| 215 | help |
| 216 | Include DSP firmware settings for max98373 amplifier. |
| 217 | |
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 218 | config NHLT_SSM4567 |
| 219 | bool |
| 220 | default n |
| 221 | help |
| 222 | Include DSP firmware settings for ssm4567 smart amplifier. |
| 223 | |
Duncan Laurie | 4a75a66 | 2017-03-02 10:13:51 -0800 | [diff] [blame] | 224 | config NHLT_RT5514 |
| 225 | bool |
| 226 | default n |
| 227 | help |
| 228 | Include DSP firmware settings for rt5514 DSP. |
| 229 | |
Rizwan Qureshi | 17335fa | 2017-01-14 06:08:21 +0530 | [diff] [blame] | 230 | config NHLT_RT5663 |
| 231 | bool |
| 232 | default n |
| 233 | help |
| 234 | Include DSP firmware settings for rt5663 headset codec. |
| 235 | |
| 236 | config NHLT_MAX98927 |
| 237 | bool |
| 238 | default n |
| 239 | help |
| 240 | Include DSP firmware settings for max98927 amplifier. |
| 241 | |
Naveen Manohar | 83670c5 | 2017-11-04 02:55:09 +0530 | [diff] [blame] | 242 | config NHLT_DA7219 |
| 243 | bool |
| 244 | default n |
| 245 | help |
| 246 | Include DSP firmware settings for DA7219 headset codec. |
| 247 | |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 248 | # Use KabylakeFsp for both Skylake and Kabylake as it supports both. |
| 249 | # SkylakeFsp is FSP 1.1 and therefore incompatible. |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 250 | config FSP_HEADER_PATH |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 251 | default "3rdparty/fsp/AmberLakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE_LGA1151_V2 |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 252 | default "3rdparty/fsp/KabylakeFspBinPkg/Include/" |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 253 | |
| 254 | config FSP_FD_PATH |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 255 | default "3rdparty/fsp/AmberLakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE_LGA1151_V2 |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 256 | default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 257 | |
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 258 | config MAX_ROOT_PORTS |
| 259 | int |
Michael Niewöhner | 0f91f79 | 2019-10-05 19:47:47 +0200 | [diff] [blame] | 260 | default 24 |
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 261 | |
Jenny TC | 2864f85 | 2017-02-09 16:01:59 +0530 | [diff] [blame] | 262 | config NO_FADT_8042 |
| 263 | bool |
| 264 | default n |
| 265 | help |
| 266 | Choose this option if you want to disable 8042 Keyboard |
| 267 | |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 268 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Furquan Shaikh | 340908a | 2017-04-04 11:47:19 -0700 | [diff] [blame] | 269 | int |
| 270 | default 120 |
| 271 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 272 | config CPU_XTAL_HZ |
| 273 | default 24000000 |
| 274 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 275 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 276 | int |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 277 | default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 278 | |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 279 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 280 | int |
| 281 | default 2 |
| 282 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 283 | config SOC_INTEL_I2C_DEV_MAX |
| 284 | int |
| 285 | default 6 |
| 286 | |
Aamir Bohra | 1041d39 | 2017-06-02 11:56:14 +0530 | [diff] [blame] | 287 | config CPU_BCLK_MHZ |
| 288 | int |
| 289 | default 100 |
| 290 | |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 291 | config CONSOLE_UART_BASE_ADDRESS |
| 292 | hex |
| 293 | default 0xfe030000 |
| 294 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 295 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 296 | # Clock divider parameters for 115200 baud rate |
| 297 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 298 | hex |
| 299 | default 0x30 |
| 300 | |
| 301 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 302 | hex |
| 303 | default 0xc35 |
| 304 | |
Felix Singer | 424467c | 2020-10-12 19:51:02 +0000 | [diff] [blame] | 305 | config CHIPSET_DEVICETREE |
| 306 | string |
| 307 | default "soc/intel/skylake/chipset.cb" |
| 308 | |
Furquan Shaikh | a3ad990 | 2018-03-21 10:45:08 -0700 | [diff] [blame] | 309 | config IFD_CHIPSET |
| 310 | string |
| 311 | default "sklkbl" |
| 312 | |
Patrick Rudolph | 5fffb5e | 2019-07-25 11:55:30 +0200 | [diff] [blame] | 313 | config INTEL_TXT_BIOSACM_ALIGNMENT |
| 314 | hex |
| 315 | default 0x40000 # 256KB |
| 316 | |
Wim Vervoorn | 2ab4f4b | 2019-10-23 10:22:06 +0200 | [diff] [blame] | 317 | config MAINBOARD_SUPPORTS_SKYLAKE_CPU |
| 318 | bool "Board can contain Skylake CPU" |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 319 | default !SOC_INTEL_SKYLAKE_LGA1151_V2 |
Wim Vervoorn | 2ab4f4b | 2019-10-23 10:22:06 +0200 | [diff] [blame] | 320 | |
| 321 | if SKYLAKE_SOC_PCH_H |
| 322 | |
| 323 | config MAINBOARD_SUPPORTS_KABYLAKE_CPU |
| 324 | bool "Board can contain Kaby Lake CPU" |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 325 | default !SOC_INTEL_SKYLAKE_LGA1151_V2 && SOC_INTEL_KABYLAKE |
Wim Vervoorn | 2ab4f4b | 2019-10-23 10:22:06 +0200 | [diff] [blame] | 326 | |
Timofey Komarov | 7e7d27b | 2021-04-27 11:00:10 +0300 | [diff] [blame] | 327 | config MAINBOARD_SUPPORTS_COFFEELAKE_CPU |
| 328 | bool "Board can contain Coffee Lake CPU" |
Timofey Komarov | 756f51b | 2021-04-27 10:54:34 +0300 | [diff] [blame] | 329 | default y if SOC_INTEL_SKYLAKE_LGA1151_V2 |
Timofey Komarov | 7e7d27b | 2021-04-27 11:00:10 +0300 | [diff] [blame] | 330 | |
Wim Vervoorn | 2ab4f4b | 2019-10-23 10:22:06 +0200 | [diff] [blame] | 331 | endif |
| 332 | |
| 333 | if !SKYLAKE_SOC_PCH_H |
| 334 | |
| 335 | config MAINBOARD_SUPPORTS_KABYLAKE_DUAL |
| 336 | bool "Board can contain Kaby Lake DUAL core" |
| 337 | default y |
| 338 | |
| 339 | config MAINBOARD_SUPPORTS_KABYLAKE_QUAD |
| 340 | bool "Board can contain Kaby Lake QUAD core" |
| 341 | default y |
| 342 | |
| 343 | endif |
| 344 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 345 | endif |