Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 6 | #include <bootstate.h> |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 7 | #include <cpu/x86/smm.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 8 | #include <device/device.h> |
| 9 | #include <device/pci.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
| 11 | #include <cbmem.h> |
Richard Spiegel | 2bbc3dc | 2017-12-06 16:14:58 -0700 | [diff] [blame] | 12 | #include <amdblocks/amd_pci_util.h> |
Richard Spiegel | 7108107 | 2018-07-26 10:51:38 -0700 | [diff] [blame] | 13 | #include <amdblocks/agesawrapper.h> |
Nico Huber | 73c1119 | 2018-10-06 18:20:47 +0200 | [diff] [blame] | 14 | #include <amdblocks/reset.h> |
Marshall Dawson | 69486ca | 2019-05-02 12:03:45 -0600 | [diff] [blame] | 15 | #include <amdblocks/acpimmio.h> |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 16 | #include <amdblocks/lpc.h> |
Marshall Dawson | 4ee83b2 | 2019-05-03 11:44:22 -0600 | [diff] [blame] | 17 | #include <amdblocks/acpi.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 18 | #include <soc/southbridge.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 19 | #include <soc/smi.h> |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 20 | #include <soc/amd_pci_int_defs.h> |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 21 | #include <delay.h> |
| 22 | #include <soc/pci_devs.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 23 | #include <agesa_headers.h> |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 24 | #include <soc/nvs.h> |
Elyes HAOUAS | 27d02d8 | 2019-05-15 21:11:39 +0200 | [diff] [blame] | 25 | #include <types.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 26 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 27 | /* |
| 28 | * Table of devices that need their AOAC registers enabled and waited |
| 29 | * upon (usually about .55 milliseconds). Instead of individual delays |
| 30 | * waiting for each device to become available, a single delay will be |
Richard Spiegel | 6dfbb59 | 2018-03-15 15:45:44 -0700 | [diff] [blame] | 31 | * executed. |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 32 | */ |
Elyes HAOUAS | 68ec3eb | 2019-06-22 09:21:18 +0200 | [diff] [blame] | 33 | static const struct stoneyridge_aoac aoac_devs[] = { |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 34 | { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), |
| 35 | (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, |
| 36 | { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, |
| 37 | { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, |
| 38 | { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, |
| 39 | { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, |
| 40 | { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } |
| 41 | }; |
| 42 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 43 | static int is_sata_config(void) |
| 44 | { |
Richard Spiegel | bdd272a | 2018-10-16 13:53:05 -0700 | [diff] [blame] | 45 | return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) |
| 46 | || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 47 | } |
| 48 | |
Richard Spiegel | 7ea8e02 | 2018-01-16 14:40:10 -0700 | [diff] [blame] | 49 | static inline int sb_sata_enable(void) |
| 50 | { |
| 51 | /* True if IDE or AHCI. */ |
Richard Spiegel | bdd272a | 2018-10-16 13:53:05 -0700 | [diff] [blame] | 52 | return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || |
| 53 | (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); |
Richard Spiegel | 7ea8e02 | 2018-01-16 14:40:10 -0700 | [diff] [blame] | 54 | } |
| 55 | |
| 56 | static inline int sb_ide_enable(void) |
| 57 | { |
| 58 | /* True if IDE or LEGACY IDE. */ |
Richard Spiegel | bdd272a | 2018-10-16 13:53:05 -0700 | [diff] [blame] | 59 | return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || |
| 60 | (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); |
Richard Spiegel | 7ea8e02 | 2018-01-16 14:40:10 -0700 | [diff] [blame] | 61 | } |
| 62 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 63 | void SetFchResetParams(FCH_RESET_INTERFACE *params) |
| 64 | { |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 65 | const struct device *dev = pcidev_path_on_root(SATA_DEVFN); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 66 | params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); |
Richard Spiegel | bb18b43 | 2018-08-03 10:37:28 -0700 | [diff] [blame] | 67 | if (dev && dev->enabled) { |
| 68 | params->SataEnable = sb_sata_enable(); |
| 69 | params->IdeEnable = sb_ide_enable(); |
| 70 | } else { |
| 71 | params->SataEnable = FALSE; |
| 72 | params->IdeEnable = FALSE; |
| 73 | } |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | void SetFchEnvParams(FCH_INTERFACE *params) |
| 77 | { |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 78 | const struct device *dev = pcidev_path_on_root(SATA_DEVFN); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 79 | params->AzaliaController = AzEnable; |
| 80 | params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; |
Richard Spiegel | bb18b43 | 2018-08-03 10:37:28 -0700 | [diff] [blame] | 81 | if (dev && dev->enabled) { |
| 82 | params->SataEnable = is_sata_config(); |
| 83 | params->IdeEnable = !params->SataEnable; |
| 84 | params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == |
| 85 | SataLegacyIde); |
| 86 | } else { |
| 87 | params->SataEnable = FALSE; |
| 88 | params->IdeEnable = FALSE; |
| 89 | params->SataIdeMode = FALSE; |
| 90 | } |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | void SetFchMidParams(FCH_INTERFACE *params) |
| 94 | { |
| 95 | SetFchEnvParams(params); |
| 96 | } |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 97 | |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 98 | /* |
| 99 | * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 100 | * provides a visible association with the index, therefore helping |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 101 | * maintainability of table. If a new index/name is defined in |
| 102 | * amd_pci_int_defs.h, just add the pair at the end of this table. |
| 103 | * Order is not important. |
| 104 | */ |
Elyes HAOUAS | 68ec3eb | 2019-06-22 09:21:18 +0200 | [diff] [blame] | 105 | static const struct irq_idx_name irq_association[] = { |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 106 | { PIRQ_A, "INTA#" }, |
| 107 | { PIRQ_B, "INTB#" }, |
| 108 | { PIRQ_C, "INTC#" }, |
| 109 | { PIRQ_D, "INTD#" }, |
| 110 | { PIRQ_E, "INTE#" }, |
| 111 | { PIRQ_F, "INTF#" }, |
| 112 | { PIRQ_G, "INTG#" }, |
| 113 | { PIRQ_H, "INTH#" }, |
| 114 | { PIRQ_MISC, "Misc" }, |
| 115 | { PIRQ_MISC0, "Misc0" }, |
| 116 | { PIRQ_MISC1, "Misc1" }, |
| 117 | { PIRQ_MISC2, "Misc2" }, |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 118 | { PIRQ_SIRQA, "Ser IRQ INTA" }, |
| 119 | { PIRQ_SIRQB, "Ser IRQ INTB" }, |
| 120 | { PIRQ_SIRQC, "Ser IRQ INTC" }, |
| 121 | { PIRQ_SIRQD, "Ser IRQ INTD" }, |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 122 | { PIRQ_SCI, "SCI" }, |
| 123 | { PIRQ_SMBUS, "SMBUS" }, |
| 124 | { PIRQ_ASF, "ASF" }, |
| 125 | { PIRQ_HDA, "HDA" }, |
| 126 | { PIRQ_FC, "FC" }, |
| 127 | { PIRQ_PMON, "PerMon" }, |
| 128 | { PIRQ_SD, "SD" }, |
| 129 | { PIRQ_SDIO, "SDIOt" }, |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 130 | { PIRQ_EHCI, "EHCI" }, |
| 131 | { PIRQ_XHCI, "XHCI" }, |
| 132 | { PIRQ_SATA, "SATA" }, |
| 133 | { PIRQ_GPIO, "GPIO" }, |
| 134 | { PIRQ_I2C0, "I2C0" }, |
| 135 | { PIRQ_I2C1, "I2C1" }, |
| 136 | { PIRQ_I2C2, "I2C2" }, |
| 137 | { PIRQ_I2C3, "I2C3" }, |
| 138 | { PIRQ_UART0, "UART0" }, |
| 139 | { PIRQ_UART1, "UART1" }, |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 140 | }; |
| 141 | |
| 142 | const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) |
| 143 | { |
| 144 | *size = ARRAY_SIZE(irq_association); |
| 145 | return irq_association; |
| 146 | } |
| 147 | |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 148 | static void power_on_aoac_device(int aoac_device_control_register) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 149 | { |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 150 | uint8_t byte; |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 151 | |
| 152 | /* Power on the UART and AMBA devices */ |
Marshall Dawson | b435d44 | 2019-05-01 21:17:20 -0600 | [diff] [blame] | 153 | byte = aoac_read8(aoac_device_control_register); |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 154 | byte |= FCH_AOAC_PWR_ON_DEV; |
Marshall Dawson | b435d44 | 2019-05-01 21:17:20 -0600 | [diff] [blame] | 155 | aoac_write8(aoac_device_control_register, byte); |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 156 | } |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 157 | |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 158 | static bool is_aoac_device_enabled(int aoac_device_status_register) |
| 159 | { |
| 160 | uint8_t byte; |
Marshall Dawson | b435d44 | 2019-05-01 21:17:20 -0600 | [diff] [blame] | 161 | |
| 162 | byte = aoac_read8(aoac_device_status_register); |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 163 | byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); |
| 164 | if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) |
| 165 | return true; |
| 166 | else |
| 167 | return false; |
| 168 | } |
| 169 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 170 | void enable_aoac_devices(void) |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 171 | { |
| 172 | bool status; |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 173 | int i; |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 174 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 175 | for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) |
| 176 | power_on_aoac_device(aoac_devs[i].enable); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 177 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 178 | /* Wait for AOAC devices to indicate power and clock OK */ |
| 179 | do { |
| 180 | udelay(100); |
| 181 | status = true; |
| 182 | for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) |
| 183 | status &= is_aoac_device_enabled(aoac_devs[i].status); |
| 184 | } while (!status); |
| 185 | } |
| 186 | |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 187 | static void sb_enable_lpc(void) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 188 | { |
| 189 | u8 byte; |
| 190 | |
| 191 | /* Enable LPC controller */ |
Marshall Dawson | 939bfcc | 2019-05-05 15:39:40 -0600 | [diff] [blame] | 192 | byte = pm_io_read8(PM_LPC_GATING); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 193 | byte |= PM_LPC_ENABLE; |
Marshall Dawson | 939bfcc | 2019-05-05 15:39:40 -0600 | [diff] [blame] | 194 | pm_io_write8(PM_LPC_GATING, byte); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 195 | } |
| 196 | |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 197 | static void sb_lpc_decode(void) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 198 | { |
| 199 | u32 tmp = 0; |
| 200 | |
| 201 | /* Enable I/O decode to LPC bus */ |
| 202 | tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 |
| 203 | | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 |
| 204 | | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 |
| 205 | | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 |
| 206 | | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 |
| 207 | | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 |
| 208 | | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 |
| 209 | | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 |
| 210 | | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 |
| 211 | | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT |
| 212 | | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT |
| 213 | | DECODE_ENABLE_ADLIB_PORT; |
| 214 | |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 215 | /* Decode SIOs at 2E/2F and 4E/4F */ |
| 216 | if (CONFIG(STONEYRIDGE_LEGACY_FREE)) |
| 217 | tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; |
| 218 | |
| 219 | lpc_enable_decode(tmp); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 220 | } |
| 221 | |
Raul E Rangel | 5b05823 | 2018-06-28 16:31:45 -0600 | [diff] [blame] | 222 | static void sb_enable_cf9_io(void) |
| 223 | { |
| 224 | uint32_t reg = pm_read32(PM_DECODE_EN); |
| 225 | |
| 226 | pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); |
| 227 | } |
| 228 | |
Raul E Rangel | 9abc3fe | 2018-06-28 16:31:45 -0600 | [diff] [blame] | 229 | static void sb_enable_legacy_io(void) |
| 230 | { |
| 231 | uint32_t reg = pm_read32(PM_DECODE_EN); |
| 232 | |
| 233 | pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); |
| 234 | } |
| 235 | |
Richard Spiegel | c93d4ab | 2019-02-12 19:17:02 -0700 | [diff] [blame] | 236 | void sb_clk_output_48Mhz(u32 osc) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 237 | { |
| 238 | u32 ctrl; |
| 239 | |
| 240 | /* |
Richard Spiegel | c93d4ab | 2019-02-12 19:17:02 -0700 | [diff] [blame] | 241 | * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) |
| 242 | * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 243 | */ |
Marshall Dawson | b4b9efc | 2019-05-01 17:33:42 -0600 | [diff] [blame] | 244 | ctrl = misc_read32(MISC_CLK_CNTL1); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 245 | |
Richard Spiegel | c93d4ab | 2019-02-12 19:17:02 -0700 | [diff] [blame] | 246 | switch (osc) { |
| 247 | case 1: |
| 248 | ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; |
| 249 | break; |
| 250 | case 2: |
| 251 | ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; |
| 252 | break; |
| 253 | default: |
| 254 | return; /* do nothing if invalid */ |
| 255 | } |
Marshall Dawson | b4b9efc | 2019-05-01 17:33:42 -0600 | [diff] [blame] | 256 | misc_write32(MISC_CLK_CNTL1, ctrl); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 257 | } |
| 258 | |
Marshall Dawson | eceaa97 | 2019-05-05 18:35:12 -0600 | [diff] [blame] | 259 | static uintptr_t sb_init_spi_base(void) |
| 260 | { |
| 261 | uintptr_t base; |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 262 | |
| 263 | /* Make sure the base address is predictable */ |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 264 | base = lpc_get_spibase(); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 265 | |
Marshall Dawson | eceaa97 | 2019-05-05 18:35:12 -0600 | [diff] [blame] | 266 | if (base) |
| 267 | return base; |
| 268 | |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 269 | lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); |
Marshall Dawson | eceaa97 | 2019-05-05 18:35:12 -0600 | [diff] [blame] | 270 | return SPI_BASE_ADDRESS; |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) |
| 274 | { |
Marshall Dawson | eceaa97 | 2019-05-05 18:35:12 -0600 | [diff] [blame] | 275 | uintptr_t base = sb_init_spi_base(); |
Richard Spiegel | 9f25e9d | 2018-10-29 08:01:53 -0700 | [diff] [blame] | 276 | write16((void *)(base + SPI100_SPEED_CONFIG), |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 277 | (norm << SPI_NORM_SPEED_NEW_SH) | |
| 278 | (fast << SPI_FAST_SPEED_NEW_SH) | |
| 279 | (alt << SPI_ALT_SPEED_NEW_SH) | |
| 280 | (tpm << SPI_TPM_SPEED_NEW_SH)); |
Richard Spiegel | 9f25e9d | 2018-10-29 08:01:53 -0700 | [diff] [blame] | 281 | write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 282 | } |
| 283 | |
| 284 | void sb_disable_4dw_burst(void) |
| 285 | { |
Marshall Dawson | eceaa97 | 2019-05-05 18:35:12 -0600 | [diff] [blame] | 286 | uintptr_t base = sb_init_spi_base(); |
Richard Spiegel | 9f25e9d | 2018-10-29 08:01:53 -0700 | [diff] [blame] | 287 | write16((void *)(base + SPI100_HOST_PREF_CONFIG), |
| 288 | read16((void *)(base + SPI100_HOST_PREF_CONFIG)) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 289 | & ~SPI_RD4DW_EN_HOST); |
| 290 | } |
| 291 | |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 292 | void sb_read_mode(u32 mode) |
| 293 | { |
Marshall Dawson | eceaa97 | 2019-05-05 18:35:12 -0600 | [diff] [blame] | 294 | uintptr_t base = sb_init_spi_base(); |
Richard Spiegel | 9f25e9d | 2018-10-29 08:01:53 -0700 | [diff] [blame] | 295 | write32((void *)(base + SPI_CNTRL0), |
| 296 | (read32((void *)(base + SPI_CNTRL0)) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 297 | & ~SPI_READ_MODE_MASK) | mode); |
| 298 | } |
| 299 | |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 300 | static void setup_spread_spectrum(int *reboot) |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 301 | { |
| 302 | uint16_t rstcfg = pm_read16(PWR_RESET_CFG); |
| 303 | |
| 304 | rstcfg &= ~TOGGLE_ALL_PWR_GOOD; |
| 305 | pm_write16(PWR_RESET_CFG, rstcfg); |
| 306 | |
| 307 | uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); |
| 308 | |
| 309 | if (cntl1 & CG1PLL_FBDIV_TEST) { |
| 310 | printk(BIOS_DEBUG, "Spread spectrum is ready\n"); |
| 311 | misc_write32(MISC_CGPLL_CONFIG1, |
| 312 | misc_read32(MISC_CGPLL_CONFIG1) | |
| 313 | CG1PLL_SPREAD_SPECTRUM_ENABLE); |
| 314 | |
| 315 | return; |
| 316 | } |
| 317 | |
| 318 | printk(BIOS_DEBUG, "Setting up spread spectrum\n"); |
| 319 | |
| 320 | uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); |
| 321 | cfg6 &= ~CG1PLL_LF_MODE_MASK; |
Marshall Dawson | ecce847 | 2018-10-05 15:41:03 -0600 | [diff] [blame] | 322 | cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 323 | misc_write32(MISC_CGPLL_CONFIG6, cfg6); |
| 324 | |
| 325 | uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); |
| 326 | cfg3 &= ~CG1PLL_REFDIV_MASK; |
| 327 | cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; |
| 328 | cfg3 &= ~CG1PLL_FBDIV_MASK; |
Marshall Dawson | ecce847 | 2018-10-05 15:41:03 -0600 | [diff] [blame] | 329 | cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 330 | misc_write32(MISC_CGPLL_CONFIG3, cfg3); |
| 331 | |
| 332 | uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); |
Marshall Dawson | edba21e | 2018-10-05 19:01:52 -0600 | [diff] [blame] | 333 | cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; |
| 334 | cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 335 | misc_write32(MISC_CGPLL_CONFIG5, cfg5); |
| 336 | |
| 337 | uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); |
Marshall Dawson | edba21e | 2018-10-05 19:01:52 -0600 | [diff] [blame] | 338 | cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; |
| 339 | cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; |
| 340 | cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; |
| 341 | cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) |
| 342 | & SS_STEP_SIZE_DSFRAC_MASK; |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 343 | misc_write32(MISC_CGPLL_CONFIG4, cfg4); |
| 344 | |
| 345 | rstcfg |= TOGGLE_ALL_PWR_GOOD; |
| 346 | pm_write16(PWR_RESET_CFG, rstcfg); |
| 347 | |
| 348 | cntl1 |= CG1PLL_FBDIV_TEST; |
| 349 | misc_write32(MISC_CLK_CNTL1, cntl1); |
| 350 | |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 351 | *reboot = 1; |
| 352 | } |
| 353 | |
| 354 | static void setup_misc(int *reboot) |
| 355 | { |
| 356 | /* Undocumented register */ |
| 357 | uint32_t reg = misc_read32(0x50); |
| 358 | if (!(reg & BIT(16))) { |
| 359 | reg |= BIT(16); |
| 360 | |
| 361 | misc_write32(0x50, reg); |
| 362 | *reboot = 1; |
| 363 | } |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 364 | } |
| 365 | |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 366 | static void fch_smbus_init(void) |
| 367 | { |
Aaron Durbin | 5c0ef70 | 2020-01-28 10:56:46 -0700 | [diff] [blame] | 368 | /* 400 kHz smbus speed. */ |
| 369 | const uint8_t smbus_speed = (66000000 / (400000 * 4)); |
| 370 | |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 371 | pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); |
Aaron Durbin | 5c0ef70 | 2020-01-28 10:56:46 -0700 | [diff] [blame] | 372 | smbus_write8(SMBTIMING, smbus_speed); |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 373 | /* Clear all SMBUS status bits */ |
Marshall Dawson | 753c225 | 2019-05-05 14:08:59 -0600 | [diff] [blame] | 374 | smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); |
| 375 | smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); |
| 376 | asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); |
| 377 | asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 378 | } |
| 379 | |
Raul E Rangel | d820f4b8 | 2018-08-13 10:39:03 -0600 | [diff] [blame] | 380 | /* Before console init */ |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 381 | void bootblock_fch_early_init(void) |
| 382 | { |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 383 | int reboot = 0; |
| 384 | |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 385 | lpc_enable_rom(); |
| 386 | sb_enable_lpc(); |
| 387 | lpc_enable_port80(); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 388 | sb_lpc_decode(); |
Marshall Dawson | 6ab5ed3 | 2019-05-29 09:24:18 -0600 | [diff] [blame] | 389 | lpc_enable_spi_prefetch(); |
Marshall Dawson | eceaa97 | 2019-05-05 18:35:12 -0600 | [diff] [blame] | 390 | sb_init_spi_base(); |
Marc Jones | cfb1680 | 2018-04-20 16:27:41 -0600 | [diff] [blame] | 391 | sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ |
Michał Żygowski | 73a544d | 2019-11-24 14:16:34 +0100 | [diff] [blame] | 392 | enable_acpimmio_decode_pm04(); |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 393 | fch_smbus_init(); |
Raul E Rangel | 5b05823 | 2018-06-28 16:31:45 -0600 | [diff] [blame] | 394 | sb_enable_cf9_io(); |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 395 | setup_spread_spectrum(&reboot); |
| 396 | setup_misc(&reboot); |
| 397 | |
| 398 | if (reboot) |
Nico Huber | 73c1119 | 2018-10-06 18:20:47 +0200 | [diff] [blame] | 399 | warm_reset(); |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 400 | |
Raul E Rangel | 9abc3fe | 2018-06-28 16:31:45 -0600 | [diff] [blame] | 401 | sb_enable_legacy_io(); |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 402 | enable_aoac_devices(); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 403 | } |
| 404 | |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 405 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 406 | const char *const bit_names[]) |
| 407 | { |
| 408 | int i; |
| 409 | |
| 410 | if (!status) |
| 411 | return; |
| 412 | |
| 413 | for (i = num_bits - 1; i >= 0; i--) { |
| 414 | if (status & (1 << i)) { |
| 415 | if (bit_names[i]) |
| 416 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 417 | else |
| 418 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 419 | } |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | static void sb_print_pmxc0_status(void) |
| 424 | { |
| 425 | /* PMxC0 S5/Reset Status shows the source of previous reset. */ |
| 426 | uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); |
| 427 | |
Edward Hill | 917b400 | 2018-10-02 14:17:19 -0600 | [diff] [blame] | 428 | static const char *const pmxc0_status_bits[32] = { |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 429 | [0] = "ThermalTrip", |
| 430 | [1] = "FourSecondPwrBtn", |
| 431 | [2] = "Shutdown", |
| 432 | [3] = "ThermalTripFromTemp", |
| 433 | [4] = "RemotePowerDownFromASF", |
| 434 | [5] = "ShutDownFan0", |
| 435 | [16] = "UserRst", |
| 436 | [17] = "SoftPciRst", |
| 437 | [18] = "DoInit", |
| 438 | [19] = "DoReset", |
| 439 | [20] = "DoFullReset", |
| 440 | [21] = "SleepReset", |
| 441 | [22] = "KbReset", |
| 442 | [23] = "LtReset", |
| 443 | [24] = "FailBootRst", |
| 444 | [25] = "WatchdogIssueReset", |
| 445 | [26] = "RemoteResetFromASF", |
| 446 | [27] = "SyncFlood", |
| 447 | [28] = "HangReset", |
| 448 | [29] = "EcWatchdogRst", |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 449 | }; |
| 450 | |
Edward Hill | 917b400 | 2018-10-02 14:17:19 -0600 | [diff] [blame] | 451 | printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 452 | print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, |
| 453 | pmxc0_status_bits); |
Edward Hill | 917b400 | 2018-10-02 14:17:19 -0600 | [diff] [blame] | 454 | printk(BIOS_DEBUG, "\n"); |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 455 | } |
| 456 | |
Raul E Rangel | d820f4b8 | 2018-08-13 10:39:03 -0600 | [diff] [blame] | 457 | /* After console init */ |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 458 | void bootblock_fch_init(void) |
| 459 | { |
| 460 | sb_print_pmxc0_status(); |
| 461 | } |
Raul E Rangel | d820f4b8 | 2018-08-13 10:39:03 -0600 | [diff] [blame] | 462 | |
Elyes HAOUAS | c5ad267 | 2018-12-05 10:58:34 +0100 | [diff] [blame] | 463 | void sb_enable(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 464 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 465 | printk(BIOS_DEBUG, "%s\n", __func__); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 466 | } |
| 467 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 468 | static void sb_init_acpi_ports(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 469 | { |
Marshall Dawson | 91b8041 | 2017-09-27 16:44:40 -0600 | [diff] [blame] | 470 | u32 reg; |
| 471 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 472 | /* We use some of these ports in SMM regardless of whether or not |
| 473 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 474 | */ |
| 475 | |
| 476 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 477 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 478 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 479 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 480 | /* CpuControl is in \_SB.CP00, 6 bytes */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 481 | pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); |
| 482 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 483 | if (CONFIG(HAVE_SMI_HANDLER)) { |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame] | 484 | /* APMC - SMI Command Port */ |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 485 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame] | 486 | configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); |
Marshall Dawson | 91b8041 | 2017-09-27 16:44:40 -0600 | [diff] [blame] | 487 | |
| 488 | /* SMI on SlpTyp requires sending SMI before completion |
| 489 | * response of the I/O write. The BKDG also specifies |
| 490 | * clearing ForceStpClkRetry for SMI trapping. |
| 491 | */ |
| 492 | reg = pm_read32(PM_PCI_CTRL); |
| 493 | reg |= FORCE_SLPSTATE_RETRY; |
| 494 | reg &= ~FORCE_STPCLK_RETRY; |
| 495 | pm_write32(PM_PCI_CTRL, reg); |
| 496 | |
| 497 | /* Disable SlpTyp feature */ |
| 498 | reg = pm_read8(PM_RST_CTRL1); |
| 499 | reg &= ~SLPTYPE_CONTROL_EN; |
| 500 | pm_write8(PM_RST_CTRL1, reg); |
| 501 | |
| 502 | configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 503 | } else { |
| 504 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 505 | } |
| 506 | |
Marshall Dawson | 5e2e74f | 2017-11-10 09:59:56 -0700 | [diff] [blame] | 507 | /* Decode ACPI registers and enable standard features */ |
| 508 | pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | |
| 509 | PM_ACPI_GLOBAL_EN | |
| 510 | PM_ACPI_RTC_EN_EN | |
| 511 | PM_ACPI_TIMER_EN_EN); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 512 | } |
| 513 | |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 514 | static int get_index_bit(uint32_t value, uint16_t limit) |
| 515 | { |
| 516 | uint16_t i; |
| 517 | uint32_t t; |
| 518 | |
Richard Spiegel | ef73cb8 | 2018-06-19 07:40:18 -0700 | [diff] [blame] | 519 | if (limit >= TOTAL_BITS(uint32_t)) |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 520 | return -1; |
| 521 | |
| 522 | /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ |
| 523 | t = (1 << limit) - 1; |
| 524 | if ((value & t) == 0) |
| 525 | return -1; |
| 526 | t = 1; |
| 527 | for (i = 0; i < limit; i++) { |
| 528 | if (value & t) |
| 529 | break; |
| 530 | t <<= 1; |
| 531 | } |
| 532 | return i; |
| 533 | } |
| 534 | |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 535 | static void set_nvs_sws(void *unused) |
| 536 | { |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 537 | struct soc_power_reg *sws; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 538 | struct global_nvs_t *gnvs; |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 539 | int index; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 540 | |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 541 | sws = cbmem_find(CBMEM_ID_POWER_STATE); |
| 542 | if (sws == NULL) |
| 543 | return; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 544 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 545 | if (gnvs == NULL) |
| 546 | return; |
| 547 | |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 548 | index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT); |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 549 | if (index < 0) |
| 550 | gnvs->pm1i = ~0ULL; |
| 551 | else |
| 552 | gnvs->pm1i = index; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 553 | |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 554 | index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT); |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 555 | if (index < 0) |
| 556 | gnvs->gpei = ~0ULL; |
| 557 | else |
| 558 | gnvs->gpei = index; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); |
| 562 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 563 | void southbridge_init(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 564 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 565 | sb_init_acpi_ports(); |
Marshall Dawson | 4ee83b2 | 2019-05-03 11:44:22 -0600 | [diff] [blame] | 566 | acpi_clear_pm1_status(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 567 | } |
| 568 | |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 569 | static void set_sb_final_nvs(void) |
| 570 | { |
| 571 | uintptr_t amdfw_rom; |
| 572 | uintptr_t xhci_fw; |
| 573 | uintptr_t fwaddr; |
| 574 | size_t fwsize; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 575 | const struct device *sd, *sata; |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 576 | |
| 577 | struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 578 | if (gnvs == NULL) |
| 579 | return; |
| 580 | |
| 581 | gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); |
| 582 | gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); |
| 583 | gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); |
| 584 | gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); |
| 585 | gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); |
| 586 | gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); |
| 587 | gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); |
| 588 | gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); |
| 589 | /* Rely on these being in sync with devicetree */ |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 590 | sd = pcidev_path_on_root(SD_DEVFN); |
Marshall Dawson | 6d3b7e6 | 2019-04-18 17:01:01 -0600 | [diff] [blame] | 591 | gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 592 | sata = pcidev_path_on_root(SATA_DEVFN); |
Marshall Dawson | 6d3b7e6 | 2019-04-18 17:01:01 -0600 | [diff] [blame] | 593 | gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 594 | gnvs->aoac.espi = 1; |
| 595 | |
| 596 | amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); |
| 597 | xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); |
| 598 | |
| 599 | fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET |
| 600 | + XHCI_FW_BOOTRAM_SIZE)); |
| 601 | fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET |
| 602 | + XHCI_FW_BOOTRAM_SIZE)); |
| 603 | gnvs->fw00 = 0; |
| 604 | gnvs->fw01 = ((32 * KiB) << 16) + 0; |
| 605 | gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; |
| 606 | gnvs->fw03 = fwsize << 16; |
| 607 | |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 608 | gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) |
| 609 | & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 610 | } |
| 611 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 612 | void southbridge_final(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 613 | { |
Richard Spiegel | 6a38914 | 2018-03-05 14:28:10 -0700 | [diff] [blame] | 614 | uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; |
| 615 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 616 | if (CONFIG(MAINBOARD_POWER_RESTORE)) |
Richard Spiegel | 6a38914 | 2018-03-05 14:28:10 -0700 | [diff] [blame] | 617 | restored_power = PM_RESTORE_S0_IF_PREV_S0; |
| 618 | pm_write8(PM_RTC_SHADOW, restored_power); |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 619 | |
| 620 | set_sb_final_nvs(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 621 | } |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 622 | |
| 623 | /* |
| 624 | * Update the PCI devices with a valid IRQ number |
| 625 | * that is set in the mainboard PCI_IRQ structures. |
| 626 | */ |
| 627 | static void set_pci_irqs(void *unused) |
| 628 | { |
| 629 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 630 | write_pci_int_table(); |
| 631 | |
| 632 | /* Write IRQs for all devicetree enabled devices */ |
| 633 | write_pci_cfg_irqs(); |
| 634 | } |
| 635 | |
| 636 | /* |
| 637 | * Hook this function into the PCI state machine |
| 638 | * on entry into BS_DEV_ENABLE. |
| 639 | */ |
| 640 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |