Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 4 | * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 17 | #include <device/mmio.h> |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 18 | #include <bootstate.h> |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 19 | #include <cpu/x86/smm.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <device/pci_ops.h> |
| 24 | #include <cbmem.h> |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 25 | #include <elog.h> |
Richard Spiegel | 2bbc3dc | 2017-12-06 16:14:58 -0700 | [diff] [blame] | 26 | #include <amdblocks/amd_pci_util.h> |
Richard Spiegel | 7108107 | 2018-07-26 10:51:38 -0700 | [diff] [blame] | 27 | #include <amdblocks/agesawrapper.h> |
Nico Huber | 73c1119 | 2018-10-06 18:20:47 +0200 | [diff] [blame] | 28 | #include <amdblocks/reset.h> |
Marshall Dawson | 69486ca | 2019-05-02 12:03:45 -0600 | [diff] [blame] | 29 | #include <amdblocks/acpimmio.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 30 | #include <soc/southbridge.h> |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 31 | #include <soc/smbus.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 32 | #include <soc/smi.h> |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 33 | #include <soc/amd_pci_int_defs.h> |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 34 | #include <delay.h> |
| 35 | #include <soc/pci_devs.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 36 | #include <agesa_headers.h> |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 37 | #include <soc/nvs.h> |
Elyes HAOUAS | 27d02d8 | 2019-05-15 21:11:39 +0200 | [diff] [blame^] | 38 | #include <types.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 39 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 40 | /* |
| 41 | * Table of devices that need their AOAC registers enabled and waited |
| 42 | * upon (usually about .55 milliseconds). Instead of individual delays |
| 43 | * waiting for each device to become available, a single delay will be |
Richard Spiegel | 6dfbb59 | 2018-03-15 15:45:44 -0700 | [diff] [blame] | 44 | * executed. |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 45 | */ |
| 46 | const static struct stoneyridge_aoac aoac_devs[] = { |
| 47 | { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), |
| 48 | (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, |
| 49 | { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, |
| 50 | { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, |
| 51 | { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, |
| 52 | { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, |
| 53 | { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } |
| 54 | }; |
| 55 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 56 | static int is_sata_config(void) |
| 57 | { |
Richard Spiegel | bdd272a | 2018-10-16 13:53:05 -0700 | [diff] [blame] | 58 | return !((SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) |
| 59 | || (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE)); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 60 | } |
| 61 | |
Richard Spiegel | 7ea8e02 | 2018-01-16 14:40:10 -0700 | [diff] [blame] | 62 | static inline int sb_sata_enable(void) |
| 63 | { |
| 64 | /* True if IDE or AHCI. */ |
Richard Spiegel | bdd272a | 2018-10-16 13:53:05 -0700 | [diff] [blame] | 65 | return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || |
| 66 | (SataAhci == CONFIG_STONEYRIDGE_SATA_MODE); |
Richard Spiegel | 7ea8e02 | 2018-01-16 14:40:10 -0700 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | static inline int sb_ide_enable(void) |
| 70 | { |
| 71 | /* True if IDE or LEGACY IDE. */ |
Richard Spiegel | bdd272a | 2018-10-16 13:53:05 -0700 | [diff] [blame] | 72 | return (SataNativeIde == CONFIG_STONEYRIDGE_SATA_MODE) || |
| 73 | (SataLegacyIde == CONFIG_STONEYRIDGE_SATA_MODE); |
Richard Spiegel | 7ea8e02 | 2018-01-16 14:40:10 -0700 | [diff] [blame] | 74 | } |
| 75 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 76 | void SetFchResetParams(FCH_RESET_INTERFACE *params) |
| 77 | { |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 78 | const struct device *dev = pcidev_path_on_root(SATA_DEVFN); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 79 | params->Xhci0Enable = CONFIG(STONEYRIDGE_XHCI_ENABLE); |
Richard Spiegel | bb18b43 | 2018-08-03 10:37:28 -0700 | [diff] [blame] | 80 | if (dev && dev->enabled) { |
| 81 | params->SataEnable = sb_sata_enable(); |
| 82 | params->IdeEnable = sb_ide_enable(); |
| 83 | } else { |
| 84 | params->SataEnable = FALSE; |
| 85 | params->IdeEnable = FALSE; |
| 86 | } |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | void SetFchEnvParams(FCH_INTERFACE *params) |
| 90 | { |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 91 | const struct device *dev = pcidev_path_on_root(SATA_DEVFN); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 92 | params->AzaliaController = AzEnable; |
| 93 | params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; |
Richard Spiegel | bb18b43 | 2018-08-03 10:37:28 -0700 | [diff] [blame] | 94 | if (dev && dev->enabled) { |
| 95 | params->SataEnable = is_sata_config(); |
| 96 | params->IdeEnable = !params->SataEnable; |
| 97 | params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == |
| 98 | SataLegacyIde); |
| 99 | } else { |
| 100 | params->SataEnable = FALSE; |
| 101 | params->IdeEnable = FALSE; |
| 102 | params->SataIdeMode = FALSE; |
| 103 | } |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | void SetFchMidParams(FCH_INTERFACE *params) |
| 107 | { |
| 108 | SetFchEnvParams(params); |
| 109 | } |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 110 | |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 111 | /* |
| 112 | * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 113 | * provides a visible association with the index, therefore helping |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 114 | * maintainability of table. If a new index/name is defined in |
| 115 | * amd_pci_int_defs.h, just add the pair at the end of this table. |
| 116 | * Order is not important. |
| 117 | */ |
| 118 | const static struct irq_idx_name irq_association[] = { |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 119 | { PIRQ_A, "INTA#" }, |
| 120 | { PIRQ_B, "INTB#" }, |
| 121 | { PIRQ_C, "INTC#" }, |
| 122 | { PIRQ_D, "INTD#" }, |
| 123 | { PIRQ_E, "INTE#" }, |
| 124 | { PIRQ_F, "INTF#" }, |
| 125 | { PIRQ_G, "INTG#" }, |
| 126 | { PIRQ_H, "INTH#" }, |
| 127 | { PIRQ_MISC, "Misc" }, |
| 128 | { PIRQ_MISC0, "Misc0" }, |
| 129 | { PIRQ_MISC1, "Misc1" }, |
| 130 | { PIRQ_MISC2, "Misc2" }, |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 131 | { PIRQ_SIRQA, "Ser IRQ INTA" }, |
| 132 | { PIRQ_SIRQB, "Ser IRQ INTB" }, |
| 133 | { PIRQ_SIRQC, "Ser IRQ INTC" }, |
| 134 | { PIRQ_SIRQD, "Ser IRQ INTD" }, |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 135 | { PIRQ_SCI, "SCI" }, |
| 136 | { PIRQ_SMBUS, "SMBUS" }, |
| 137 | { PIRQ_ASF, "ASF" }, |
| 138 | { PIRQ_HDA, "HDA" }, |
| 139 | { PIRQ_FC, "FC" }, |
| 140 | { PIRQ_PMON, "PerMon" }, |
| 141 | { PIRQ_SD, "SD" }, |
| 142 | { PIRQ_SDIO, "SDIOt" }, |
Richard Spiegel | e89d444 | 2017-12-08 07:52:42 -0700 | [diff] [blame] | 143 | { PIRQ_EHCI, "EHCI" }, |
| 144 | { PIRQ_XHCI, "XHCI" }, |
| 145 | { PIRQ_SATA, "SATA" }, |
| 146 | { PIRQ_GPIO, "GPIO" }, |
| 147 | { PIRQ_I2C0, "I2C0" }, |
| 148 | { PIRQ_I2C1, "I2C1" }, |
| 149 | { PIRQ_I2C2, "I2C2" }, |
| 150 | { PIRQ_I2C3, "I2C3" }, |
| 151 | { PIRQ_UART0, "UART0" }, |
| 152 | { PIRQ_UART1, "UART1" }, |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 153 | }; |
| 154 | |
Richard Spiegel | ebf3aa8 | 2017-11-24 07:47:42 -0700 | [diff] [blame] | 155 | /* |
| 156 | * Structure to simplify code obtaining the total of used wide IO |
| 157 | * registers and the size assigned to each. |
| 158 | */ |
| 159 | static struct wide_io_ioport_and_bits { |
| 160 | uint32_t enable; |
| 161 | uint16_t port; |
| 162 | uint8_t alt; |
| 163 | } wio_io_en[TOTAL_WIDEIO_PORTS] = { |
| 164 | { |
| 165 | LPC_WIDEIO0_ENABLE, |
| 166 | LPC_WIDEIO_GENERIC_PORT, |
| 167 | LPC_ALT_WIDEIO0_ENABLE |
| 168 | }, |
| 169 | { |
| 170 | LPC_WIDEIO1_ENABLE, |
| 171 | LPC_WIDEIO1_GENERIC_PORT, |
| 172 | LPC_ALT_WIDEIO1_ENABLE |
| 173 | }, |
| 174 | { |
| 175 | LPC_WIDEIO2_ENABLE, |
| 176 | LPC_WIDEIO2_GENERIC_PORT, |
| 177 | LPC_ALT_WIDEIO2_ENABLE |
| 178 | } |
| 179 | }; |
| 180 | |
Richard Spiegel | 376dc82 | 2017-12-01 08:24:26 -0700 | [diff] [blame] | 181 | const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) |
| 182 | { |
| 183 | *size = ARRAY_SIZE(irq_association); |
| 184 | return irq_association; |
| 185 | } |
| 186 | |
Richard Spiegel | ebf3aa8 | 2017-11-24 07:47:42 -0700 | [diff] [blame] | 187 | /** |
| 188 | * @brief Find the size of a particular wide IO |
| 189 | * |
| 190 | * @param index = index of desired wide IO |
| 191 | * |
| 192 | * @return size of desired wide IO |
| 193 | */ |
| 194 | uint16_t sb_wideio_size(int index) |
| 195 | { |
| 196 | uint32_t enable_register; |
| 197 | uint16_t size = 0; |
| 198 | uint8_t alternate_register; |
| 199 | |
| 200 | if (index >= TOTAL_WIDEIO_PORTS) |
| 201 | return size; |
| 202 | enable_register = pci_read_config32(SOC_LPC_DEV, |
| 203 | LPC_IO_OR_MEM_DECODE_ENABLE); |
| 204 | alternate_register = pci_read_config8(SOC_LPC_DEV, |
| 205 | LPC_ALT_WIDEIO_RANGE_ENABLE); |
| 206 | if (enable_register & wio_io_en[index].enable) |
| 207 | size = (alternate_register & wio_io_en[index].alt) ? |
| 208 | 16 : 512; |
| 209 | return size; |
| 210 | } |
| 211 | |
| 212 | /** |
| 213 | * @brief Identify if any LPC wide IO is covering the IO range |
| 214 | * |
| 215 | * @param start = start of IO range |
| 216 | * @param size = size of IO range |
| 217 | * |
| 218 | * @return Index of wide IO covering the range or error |
| 219 | */ |
| 220 | int sb_find_wideio_range(uint16_t start, uint16_t size) |
| 221 | { |
Richard Spiegel | ebf3aa8 | 2017-11-24 07:47:42 -0700 | [diff] [blame] | 222 | int i, index = WIDEIO_RANGE_ERROR; |
| 223 | uint16_t end, current_size, start_wideio, end_wideio; |
| 224 | |
| 225 | end = start + size; |
Richard Spiegel | ebf3aa8 | 2017-11-24 07:47:42 -0700 | [diff] [blame] | 226 | for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { |
| 227 | current_size = sb_wideio_size(i); |
| 228 | if (current_size == 0) |
| 229 | continue; |
| 230 | start_wideio = pci_read_config16(SOC_LPC_DEV, |
| 231 | wio_io_en[i].port); |
| 232 | end_wideio = start_wideio + current_size; |
| 233 | if ((start >= start_wideio) && (end <= end_wideio)) { |
| 234 | index = i; |
| 235 | break; |
| 236 | } |
| 237 | } |
| 238 | return index; |
| 239 | } |
| 240 | |
| 241 | /** |
| 242 | * @brief Program a LPC wide IO to support an IO range |
| 243 | * |
| 244 | * @param start = start of range to be routed through wide IO |
| 245 | * @param size = size of range to be routed through wide IO |
| 246 | * |
| 247 | * @return Index of wide IO register used or error |
| 248 | */ |
| 249 | int sb_set_wideio_range(uint16_t start, uint16_t size) |
| 250 | { |
| 251 | int i, index = WIDEIO_RANGE_ERROR; |
| 252 | uint32_t enable_register; |
| 253 | uint8_t alternate_register; |
| 254 | |
| 255 | enable_register = pci_read_config32(SOC_LPC_DEV, |
| 256 | LPC_IO_OR_MEM_DECODE_ENABLE); |
| 257 | alternate_register = pci_read_config8(SOC_LPC_DEV, |
| 258 | LPC_ALT_WIDEIO_RANGE_ENABLE); |
| 259 | for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { |
| 260 | if (enable_register & wio_io_en[i].enable) |
| 261 | continue; |
| 262 | index = i; |
| 263 | pci_write_config16(SOC_LPC_DEV, wio_io_en[i].port, start); |
| 264 | enable_register |= wio_io_en[i].enable; |
| 265 | pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, |
| 266 | enable_register); |
| 267 | if (size <= 16) |
| 268 | alternate_register |= wio_io_en[i].alt; |
| 269 | else |
| 270 | alternate_register &= ~wio_io_en[i].alt; |
| 271 | pci_write_config8(SOC_LPC_DEV, |
| 272 | LPC_ALT_WIDEIO_RANGE_ENABLE, |
| 273 | alternate_register); |
| 274 | break; |
| 275 | } |
| 276 | return index; |
| 277 | } |
| 278 | |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 279 | static void power_on_aoac_device(int aoac_device_control_register) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 280 | { |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 281 | uint8_t byte; |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 282 | |
| 283 | /* Power on the UART and AMBA devices */ |
Marshall Dawson | b435d44 | 2019-05-01 21:17:20 -0600 | [diff] [blame] | 284 | byte = aoac_read8(aoac_device_control_register); |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 285 | byte |= FCH_AOAC_PWR_ON_DEV; |
Marshall Dawson | b435d44 | 2019-05-01 21:17:20 -0600 | [diff] [blame] | 286 | aoac_write8(aoac_device_control_register, byte); |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 287 | } |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 288 | |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 289 | static bool is_aoac_device_enabled(int aoac_device_status_register) |
| 290 | { |
| 291 | uint8_t byte; |
Marshall Dawson | b435d44 | 2019-05-01 21:17:20 -0600 | [diff] [blame] | 292 | |
| 293 | byte = aoac_read8(aoac_device_status_register); |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 294 | byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); |
| 295 | if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) |
| 296 | return true; |
| 297 | else |
| 298 | return false; |
| 299 | } |
| 300 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 301 | void enable_aoac_devices(void) |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 302 | { |
| 303 | bool status; |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 304 | int i; |
Garrett Kirkendall | a0ff6fc | 2018-03-06 09:23:47 -0600 | [diff] [blame] | 305 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 306 | for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) |
| 307 | power_on_aoac_device(aoac_devs[i].enable); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 308 | |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 309 | /* Wait for AOAC devices to indicate power and clock OK */ |
| 310 | do { |
| 311 | udelay(100); |
| 312 | status = true; |
| 313 | for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) |
| 314 | status &= is_aoac_device_enabled(aoac_devs[i].status); |
| 315 | } while (!status); |
| 316 | } |
| 317 | |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 318 | void sb_pci_port80(void) |
| 319 | { |
| 320 | u8 byte; |
| 321 | |
| 322 | byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); |
| 323 | byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ |
| 324 | pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); |
| 325 | } |
| 326 | |
| 327 | void sb_lpc_port80(void) |
| 328 | { |
| 329 | u8 byte; |
| 330 | |
| 331 | /* Enable LPC controller */ |
Marshall Dawson | 939bfcc | 2019-05-05 15:39:40 -0600 | [diff] [blame] | 332 | byte = pm_io_read8(PM_LPC_GATING); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 333 | byte |= PM_LPC_ENABLE; |
Marshall Dawson | 939bfcc | 2019-05-05 15:39:40 -0600 | [diff] [blame] | 334 | pm_io_write8(PM_LPC_GATING, byte); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 335 | |
| 336 | /* Enable port 80 LPC decode in pci function 3 configuration space. */ |
| 337 | byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); |
| 338 | byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */ |
| 339 | pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); |
| 340 | } |
| 341 | |
| 342 | void sb_lpc_decode(void) |
| 343 | { |
| 344 | u32 tmp = 0; |
| 345 | |
| 346 | /* Enable I/O decode to LPC bus */ |
| 347 | tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 |
| 348 | | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 |
| 349 | | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 |
| 350 | | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 |
| 351 | | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 |
| 352 | | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 |
| 353 | | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 |
| 354 | | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 |
| 355 | | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 |
| 356 | | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT |
| 357 | | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT |
| 358 | | DECODE_ENABLE_ADLIB_PORT; |
| 359 | |
| 360 | pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); |
| 361 | } |
| 362 | |
Raul E Rangel | 5b05823 | 2018-06-28 16:31:45 -0600 | [diff] [blame] | 363 | static void sb_enable_cf9_io(void) |
| 364 | { |
| 365 | uint32_t reg = pm_read32(PM_DECODE_EN); |
| 366 | |
| 367 | pm_write32(PM_DECODE_EN, reg | CF9_IO_EN); |
| 368 | } |
| 369 | |
Raul E Rangel | 9abc3fe | 2018-06-28 16:31:45 -0600 | [diff] [blame] | 370 | static void sb_enable_legacy_io(void) |
| 371 | { |
| 372 | uint32_t reg = pm_read32(PM_DECODE_EN); |
| 373 | |
| 374 | pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN); |
| 375 | } |
| 376 | |
Richard Spiegel | c93d4ab | 2019-02-12 19:17:02 -0700 | [diff] [blame] | 377 | void sb_clk_output_48Mhz(u32 osc) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 378 | { |
| 379 | u32 ctrl; |
| 380 | |
| 381 | /* |
Richard Spiegel | c93d4ab | 2019-02-12 19:17:02 -0700 | [diff] [blame] | 382 | * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) |
| 383 | * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 384 | */ |
Marshall Dawson | b4b9efc | 2019-05-01 17:33:42 -0600 | [diff] [blame] | 385 | ctrl = misc_read32(MISC_CLK_CNTL1); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 386 | |
Richard Spiegel | c93d4ab | 2019-02-12 19:17:02 -0700 | [diff] [blame] | 387 | switch (osc) { |
| 388 | case 1: |
| 389 | ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB; |
| 390 | break; |
| 391 | case 2: |
| 392 | ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB; |
| 393 | break; |
| 394 | default: |
| 395 | return; /* do nothing if invalid */ |
| 396 | } |
Marshall Dawson | b4b9efc | 2019-05-01 17:33:42 -0600 | [diff] [blame] | 397 | misc_write32(MISC_CLK_CNTL1, ctrl); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 398 | } |
| 399 | |
| 400 | static uintptr_t sb_spibase(void) |
| 401 | { |
| 402 | u32 base, enables; |
| 403 | |
| 404 | /* Make sure the base address is predictable */ |
| 405 | base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); |
Patrick Georgi | 4fbefc5 | 2018-10-23 14:35:37 +0200 | [diff] [blame] | 406 | enables = base & SPI_PRESERVE_BITS; |
| 407 | base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 408 | |
| 409 | if (!base) { |
| 410 | base = SPI_BASE_ADDRESS; |
| 411 | pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, |
| 412 | base | enables | SPI_ROM_ENABLE); |
| 413 | /* PCI_COMMAND_MEMORY is read-only and enabled. */ |
| 414 | } |
| 415 | return (uintptr_t)base; |
| 416 | } |
| 417 | |
| 418 | void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) |
| 419 | { |
| 420 | uintptr_t base = sb_spibase(); |
Richard Spiegel | 9f25e9d | 2018-10-29 08:01:53 -0700 | [diff] [blame] | 421 | write16((void *)(base + SPI100_SPEED_CONFIG), |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 422 | (norm << SPI_NORM_SPEED_NEW_SH) | |
| 423 | (fast << SPI_FAST_SPEED_NEW_SH) | |
| 424 | (alt << SPI_ALT_SPEED_NEW_SH) | |
| 425 | (tpm << SPI_TPM_SPEED_NEW_SH)); |
Richard Spiegel | 9f25e9d | 2018-10-29 08:01:53 -0700 | [diff] [blame] | 426 | write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 427 | } |
| 428 | |
| 429 | void sb_disable_4dw_burst(void) |
| 430 | { |
| 431 | uintptr_t base = sb_spibase(); |
Richard Spiegel | 9f25e9d | 2018-10-29 08:01:53 -0700 | [diff] [blame] | 432 | write16((void *)(base + SPI100_HOST_PREF_CONFIG), |
| 433 | read16((void *)(base + SPI100_HOST_PREF_CONFIG)) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 434 | & ~SPI_RD4DW_EN_HOST); |
| 435 | } |
| 436 | |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 437 | void sb_read_mode(u32 mode) |
| 438 | { |
| 439 | uintptr_t base = sb_spibase(); |
Richard Spiegel | 9f25e9d | 2018-10-29 08:01:53 -0700 | [diff] [blame] | 440 | write32((void *)(base + SPI_CNTRL0), |
| 441 | (read32((void *)(base + SPI_CNTRL0)) |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 442 | & ~SPI_READ_MODE_MASK) | mode); |
| 443 | } |
| 444 | |
Garrett Kirkendall | 6575306 | 2018-03-07 16:12:11 -0600 | [diff] [blame] | 445 | /* |
| 446 | * Enable FCH to decode TPM associated Memory and IO regions |
| 447 | * |
| 448 | * Enable decoding of TPM cycles defined in TPM 1.2 spec |
| 449 | * Enable decoding of legacy TPM addresses: IO addresses 0x7f- |
| 450 | * 0x7e and 0xef-0xee. |
| 451 | * This function should be called if TPM is connected in any way to the FCH and |
| 452 | * conforms to the regions decoded. |
| 453 | * Absent any other routing configuration the TPM cycles will be claimed by the |
| 454 | * LPC bus |
| 455 | */ |
| 456 | void sb_tpm_decode(void) |
| 457 | { |
| 458 | u32 value; |
| 459 | |
| 460 | value = pci_read_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE); |
| 461 | value |= TPM_12_EN | TPM_LEGACY_EN; |
| 462 | pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value); |
| 463 | } |
| 464 | |
| 465 | /* |
| 466 | * Enable FCH to decode TPM associated Memory and IO regions to SPI |
| 467 | * |
| 468 | * This should be used if TPM is connected to SPI bus. |
| 469 | * Assumes SPI address space is already configured via a call to sb_spibase(). |
| 470 | */ |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 471 | void sb_tpm_decode_spi(void) |
| 472 | { |
Garrett Kirkendall | 6575306 | 2018-03-07 16:12:11 -0600 | [diff] [blame] | 473 | /* Enable TPM decoding to FCH */ |
| 474 | sb_tpm_decode(); |
| 475 | |
| 476 | /* Route TPM accesses to SPI */ |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 477 | u32 spibase = pci_read_config32(SOC_LPC_DEV, |
| 478 | SPIROM_BASE_ADDRESS_REGISTER); |
| 479 | pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase |
| 480 | | ROUTE_TPM_2_SPI); |
| 481 | } |
| 482 | |
| 483 | /* |
| 484 | * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. |
| 485 | * |
| 486 | * Hardware should enable LPC ROM by pin straps. This function does not |
| 487 | * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. |
| 488 | * |
| 489 | * The southbridge power-on default is to map 512K ROM space. |
| 490 | * |
| 491 | */ |
| 492 | void sb_enable_rom(void) |
| 493 | { |
| 494 | u8 reg8; |
| 495 | |
| 496 | /* |
| 497 | * Decode variable LPC ROM address ranges 1 and 2. |
| 498 | * Bits 3-4 are not defined in any publicly available datasheet |
| 499 | */ |
| 500 | reg8 = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); |
| 501 | reg8 |= (1 << 3) | (1 << 4); |
| 502 | pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8); |
| 503 | |
| 504 | /* |
| 505 | * LPC ROM address range 1: |
| 506 | * Enable LPC ROM range mirroring start at 0x000e(0000). |
| 507 | */ |
| 508 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e); |
| 509 | |
| 510 | /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ |
| 511 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f); |
| 512 | |
| 513 | /* |
| 514 | * LPC ROM address range 2: |
| 515 | * |
| 516 | * Enable LPC ROM range start at: |
| 517 | * 0xfff8(0000): 512KB |
| 518 | * 0xfff0(0000): 1MB |
| 519 | * 0xffe0(0000): 2MB |
| 520 | * 0xffc0(0000): 4MB |
| 521 | */ |
| 522 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 |
| 523 | - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); |
| 524 | |
| 525 | /* Enable LPC ROM range end at 0xffff(ffff). */ |
| 526 | pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff); |
| 527 | } |
| 528 | |
Marc Jones | cfb1680 | 2018-04-20 16:27:41 -0600 | [diff] [blame] | 529 | static void sb_lpc_early_setup(void) |
| 530 | { |
| 531 | uint32_t dword; |
| 532 | |
| 533 | /* Enable SPI prefetch */ |
| 534 | dword = pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); |
| 535 | dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN; |
| 536 | pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); |
| 537 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 538 | if (CONFIG(STONEYRIDGE_LEGACY_FREE)) { |
Marc Jones | cfb1680 | 2018-04-20 16:27:41 -0600 | [diff] [blame] | 539 | /* Decode SIOs at 2E/2F and 4E/4F */ |
| 540 | dword = pci_read_config32(SOC_LPC_DEV, |
| 541 | LPC_IO_OR_MEM_DECODE_ENABLE); |
| 542 | dword |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; |
| 543 | pci_write_config32(SOC_LPC_DEV, |
| 544 | LPC_IO_OR_MEM_DECODE_ENABLE, dword); |
| 545 | } |
| 546 | } |
| 547 | |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 548 | static void setup_spread_spectrum(int *reboot) |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 549 | { |
| 550 | uint16_t rstcfg = pm_read16(PWR_RESET_CFG); |
| 551 | |
| 552 | rstcfg &= ~TOGGLE_ALL_PWR_GOOD; |
| 553 | pm_write16(PWR_RESET_CFG, rstcfg); |
| 554 | |
| 555 | uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); |
| 556 | |
| 557 | if (cntl1 & CG1PLL_FBDIV_TEST) { |
| 558 | printk(BIOS_DEBUG, "Spread spectrum is ready\n"); |
| 559 | misc_write32(MISC_CGPLL_CONFIG1, |
| 560 | misc_read32(MISC_CGPLL_CONFIG1) | |
| 561 | CG1PLL_SPREAD_SPECTRUM_ENABLE); |
| 562 | |
| 563 | return; |
| 564 | } |
| 565 | |
| 566 | printk(BIOS_DEBUG, "Setting up spread spectrum\n"); |
| 567 | |
| 568 | uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); |
| 569 | cfg6 &= ~CG1PLL_LF_MODE_MASK; |
Marshall Dawson | ecce847 | 2018-10-05 15:41:03 -0600 | [diff] [blame] | 570 | cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 571 | misc_write32(MISC_CGPLL_CONFIG6, cfg6); |
| 572 | |
| 573 | uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); |
| 574 | cfg3 &= ~CG1PLL_REFDIV_MASK; |
| 575 | cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; |
| 576 | cfg3 &= ~CG1PLL_FBDIV_MASK; |
Marshall Dawson | ecce847 | 2018-10-05 15:41:03 -0600 | [diff] [blame] | 577 | cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 578 | misc_write32(MISC_CGPLL_CONFIG3, cfg3); |
| 579 | |
| 580 | uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); |
Marshall Dawson | edba21e | 2018-10-05 19:01:52 -0600 | [diff] [blame] | 581 | cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; |
| 582 | cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 583 | misc_write32(MISC_CGPLL_CONFIG5, cfg5); |
| 584 | |
| 585 | uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); |
Marshall Dawson | edba21e | 2018-10-05 19:01:52 -0600 | [diff] [blame] | 586 | cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; |
| 587 | cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; |
| 588 | cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; |
| 589 | cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) |
| 590 | & SS_STEP_SIZE_DSFRAC_MASK; |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 591 | misc_write32(MISC_CGPLL_CONFIG4, cfg4); |
| 592 | |
| 593 | rstcfg |= TOGGLE_ALL_PWR_GOOD; |
| 594 | pm_write16(PWR_RESET_CFG, rstcfg); |
| 595 | |
| 596 | cntl1 |= CG1PLL_FBDIV_TEST; |
| 597 | misc_write32(MISC_CLK_CNTL1, cntl1); |
| 598 | |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 599 | *reboot = 1; |
| 600 | } |
| 601 | |
| 602 | static void setup_misc(int *reboot) |
| 603 | { |
| 604 | /* Undocumented register */ |
| 605 | uint32_t reg = misc_read32(0x50); |
| 606 | if (!(reg & BIT(16))) { |
| 607 | reg |= BIT(16); |
| 608 | |
| 609 | misc_write32(0x50, reg); |
| 610 | *reboot = 1; |
| 611 | } |
Raul E Rangel | 6b0fc80 | 2018-08-02 15:56:34 -0600 | [diff] [blame] | 612 | } |
| 613 | |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 614 | static void fch_smbus_init(void) |
| 615 | { |
| 616 | pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); |
Marshall Dawson | 753c225 | 2019-05-05 14:08:59 -0600 | [diff] [blame] | 617 | smbus_write8(SMBTIMING, SMB_SPEED_400KHZ); |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 618 | /* Clear all SMBUS status bits */ |
Marshall Dawson | 753c225 | 2019-05-05 14:08:59 -0600 | [diff] [blame] | 619 | smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); |
| 620 | smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); |
| 621 | asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); |
| 622 | asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 623 | } |
| 624 | |
Raul E Rangel | d820f4b8 | 2018-08-13 10:39:03 -0600 | [diff] [blame] | 625 | /* Before console init */ |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 626 | void bootblock_fch_early_init(void) |
| 627 | { |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 628 | int reboot = 0; |
| 629 | |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 630 | sb_enable_rom(); |
| 631 | sb_lpc_port80(); |
| 632 | sb_lpc_decode(); |
Marc Jones | cfb1680 | 2018-04-20 16:27:41 -0600 | [diff] [blame] | 633 | sb_lpc_early_setup(); |
Garrett Kirkendall | 64294eb | 2018-03-16 13:00:46 -0500 | [diff] [blame] | 634 | sb_spibase(); |
Marc Jones | cfb1680 | 2018-04-20 16:27:41 -0600 | [diff] [blame] | 635 | sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ |
Marshall Dawson | 69486ca | 2019-05-02 12:03:45 -0600 | [diff] [blame] | 636 | enable_acpimmio_decode(); |
Richard Spiegel | b40e193 | 2018-10-24 12:51:21 -0700 | [diff] [blame] | 637 | fch_smbus_init(); |
Raul E Rangel | 5b05823 | 2018-06-28 16:31:45 -0600 | [diff] [blame] | 638 | sb_enable_cf9_io(); |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 639 | setup_spread_spectrum(&reboot); |
| 640 | setup_misc(&reboot); |
| 641 | |
| 642 | if (reboot) |
Nico Huber | 73c1119 | 2018-10-06 18:20:47 +0200 | [diff] [blame] | 643 | warm_reset(); |
Raul E Rangel | 7905341 | 2018-08-06 10:40:02 -0600 | [diff] [blame] | 644 | |
Raul E Rangel | 9abc3fe | 2018-06-28 16:31:45 -0600 | [diff] [blame] | 645 | sb_enable_legacy_io(); |
Richard Spiegel | 0e0e93c | 2018-03-13 10:19:51 -0700 | [diff] [blame] | 646 | enable_aoac_devices(); |
Richard Spiegel | bec44f2 | 2017-11-24 07:41:29 -0700 | [diff] [blame] | 647 | } |
| 648 | |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 649 | static void print_num_status_bits(int num_bits, uint32_t status, |
| 650 | const char *const bit_names[]) |
| 651 | { |
| 652 | int i; |
| 653 | |
| 654 | if (!status) |
| 655 | return; |
| 656 | |
| 657 | for (i = num_bits - 1; i >= 0; i--) { |
| 658 | if (status & (1 << i)) { |
| 659 | if (bit_names[i]) |
| 660 | printk(BIOS_DEBUG, "%s ", bit_names[i]); |
| 661 | else |
| 662 | printk(BIOS_DEBUG, "BIT%d ", i); |
| 663 | } |
| 664 | } |
| 665 | } |
| 666 | |
| 667 | static void sb_print_pmxc0_status(void) |
| 668 | { |
| 669 | /* PMxC0 S5/Reset Status shows the source of previous reset. */ |
| 670 | uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); |
| 671 | |
Edward Hill | 917b400 | 2018-10-02 14:17:19 -0600 | [diff] [blame] | 672 | static const char *const pmxc0_status_bits[32] = { |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 673 | [0] = "ThermalTrip", |
| 674 | [1] = "FourSecondPwrBtn", |
| 675 | [2] = "Shutdown", |
| 676 | [3] = "ThermalTripFromTemp", |
| 677 | [4] = "RemotePowerDownFromASF", |
| 678 | [5] = "ShutDownFan0", |
| 679 | [16] = "UserRst", |
| 680 | [17] = "SoftPciRst", |
| 681 | [18] = "DoInit", |
| 682 | [19] = "DoReset", |
| 683 | [20] = "DoFullReset", |
| 684 | [21] = "SleepReset", |
| 685 | [22] = "KbReset", |
| 686 | [23] = "LtReset", |
| 687 | [24] = "FailBootRst", |
| 688 | [25] = "WatchdogIssueReset", |
| 689 | [26] = "RemoteResetFromASF", |
| 690 | [27] = "SyncFlood", |
| 691 | [28] = "HangReset", |
| 692 | [29] = "EcWatchdogRst", |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 693 | }; |
| 694 | |
Edward Hill | 917b400 | 2018-10-02 14:17:19 -0600 | [diff] [blame] | 695 | printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 696 | print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, |
| 697 | pmxc0_status_bits); |
Edward Hill | 917b400 | 2018-10-02 14:17:19 -0600 | [diff] [blame] | 698 | printk(BIOS_DEBUG, "\n"); |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 699 | } |
| 700 | |
Raul E Rangel | d820f4b8 | 2018-08-13 10:39:03 -0600 | [diff] [blame] | 701 | /* After console init */ |
Edward Hill | cc68034 | 2018-08-10 16:20:02 -0600 | [diff] [blame] | 702 | void bootblock_fch_init(void) |
| 703 | { |
| 704 | sb_print_pmxc0_status(); |
| 705 | } |
Raul E Rangel | d820f4b8 | 2018-08-13 10:39:03 -0600 | [diff] [blame] | 706 | |
Elyes HAOUAS | c5ad267 | 2018-12-05 10:58:34 +0100 | [diff] [blame] | 707 | void sb_enable(struct device *dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 708 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 709 | printk(BIOS_DEBUG, "%s\n", __func__); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 710 | } |
| 711 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 712 | static void sb_init_acpi_ports(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 713 | { |
Marshall Dawson | 91b8041 | 2017-09-27 16:44:40 -0600 | [diff] [blame] | 714 | u32 reg; |
| 715 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 716 | /* We use some of these ports in SMM regardless of whether or not |
| 717 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 718 | */ |
| 719 | |
| 720 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 721 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 722 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 723 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
| 724 | /* CpuControl is in \_PR.CP00, 6 bytes */ |
| 725 | pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); |
| 726 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 727 | if (CONFIG(HAVE_SMI_HANDLER)) { |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame] | 728 | /* APMC - SMI Command Port */ |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 729 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame] | 730 | configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); |
Marshall Dawson | 91b8041 | 2017-09-27 16:44:40 -0600 | [diff] [blame] | 731 | |
| 732 | /* SMI on SlpTyp requires sending SMI before completion |
| 733 | * response of the I/O write. The BKDG also specifies |
| 734 | * clearing ForceStpClkRetry for SMI trapping. |
| 735 | */ |
| 736 | reg = pm_read32(PM_PCI_CTRL); |
| 737 | reg |= FORCE_SLPSTATE_RETRY; |
| 738 | reg &= ~FORCE_STPCLK_RETRY; |
| 739 | pm_write32(PM_PCI_CTRL, reg); |
| 740 | |
| 741 | /* Disable SlpTyp feature */ |
| 742 | reg = pm_read8(PM_RST_CTRL1); |
| 743 | reg &= ~SLPTYPE_CONTROL_EN; |
| 744 | pm_write8(PM_RST_CTRL1, reg); |
| 745 | |
| 746 | configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 747 | } else { |
| 748 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 749 | } |
| 750 | |
Marshall Dawson | 5e2e74f | 2017-11-10 09:59:56 -0700 | [diff] [blame] | 751 | /* Decode ACPI registers and enable standard features */ |
| 752 | pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | |
| 753 | PM_ACPI_GLOBAL_EN | |
| 754 | PM_ACPI_RTC_EN_EN | |
| 755 | PM_ACPI_TIMER_EN_EN); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 756 | } |
| 757 | |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 758 | static uint16_t reset_pm1_status(void) |
| 759 | { |
Richard Spiegel | e24d795 | 2018-10-26 13:25:01 -0700 | [diff] [blame] | 760 | uint16_t pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); |
| 761 | acpi_write16(MMIO_ACPI_PM1_STS, pm1_sts); |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 762 | return pm1_sts; |
| 763 | } |
| 764 | |
| 765 | static uint16_t print_pm1_status(uint16_t pm1_sts) |
| 766 | { |
Edward Hill | 917b400 | 2018-10-02 14:17:19 -0600 | [diff] [blame] | 767 | static const char *const pm1_sts_bits[16] = { |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 768 | [0] = "TMROF", |
| 769 | [4] = "BMSTATUS", |
| 770 | [5] = "GBL", |
| 771 | [8] = "PWRBTN", |
| 772 | [10] = "RTC", |
| 773 | [14] = "PCIEXPWAK", |
| 774 | [15] = "WAK", |
| 775 | }; |
| 776 | |
| 777 | if (!pm1_sts) |
| 778 | return 0; |
| 779 | |
Edward Hill | 917b400 | 2018-10-02 14:17:19 -0600 | [diff] [blame] | 780 | printk(BIOS_DEBUG, "PM1_STS: "); |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 781 | print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); |
Edward Hill | 917b400 | 2018-10-02 14:17:19 -0600 | [diff] [blame] | 782 | printk(BIOS_DEBUG, "\n"); |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 783 | |
| 784 | return pm1_sts; |
| 785 | } |
| 786 | |
| 787 | static void sb_log_pm1_status(uint16_t pm1_sts) |
| 788 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 789 | if (!CONFIG(ELOG)) |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 790 | return; |
| 791 | |
Daniel Kurtz | b6fdd22 | 2018-05-24 15:52:45 -0600 | [diff] [blame] | 792 | if (pm1_sts & WAK_STS) |
| 793 | elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, |
| 794 | acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5); |
| 795 | |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 796 | if (pm1_sts & PWRBTN_STS) |
| 797 | elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); |
| 798 | |
| 799 | if (pm1_sts & RTC_STS) |
| 800 | elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); |
| 801 | |
| 802 | if (pm1_sts & PCIEXPWAK_STS) |
| 803 | elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); |
| 804 | } |
| 805 | |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 806 | static void sb_save_sws(uint16_t pm1_status) |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 807 | { |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 808 | struct soc_power_reg *sws; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 809 | uint32_t reg32; |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 810 | uint16_t reg16; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 811 | |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 812 | sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg)); |
| 813 | if (sws == NULL) |
| 814 | return; |
| 815 | sws->pm1_sts = pm1_status; |
Richard Spiegel | e24d795 | 2018-10-26 13:25:01 -0700 | [diff] [blame] | 816 | sws->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN); |
| 817 | reg32 = acpi_read32(MMIO_ACPI_GPE0_STS); |
| 818 | acpi_write32(MMIO_ACPI_GPE0_STS, reg32); |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 819 | sws->gpe0_sts = reg32; |
Richard Spiegel | e24d795 | 2018-10-26 13:25:01 -0700 | [diff] [blame] | 820 | sws->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN); |
| 821 | reg16 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 822 | reg16 &= SLP_TYP; |
| 823 | sws->wake_from = reg16 >> SLP_TYP_SHIFT; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 824 | } |
| 825 | |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 826 | static void sb_clear_pm1_status(void) |
| 827 | { |
| 828 | uint16_t pm1_sts = reset_pm1_status(); |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 829 | |
| 830 | sb_save_sws(pm1_sts); |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 831 | sb_log_pm1_status(pm1_sts); |
| 832 | print_pm1_status(pm1_sts); |
| 833 | } |
| 834 | |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 835 | static int get_index_bit(uint32_t value, uint16_t limit) |
| 836 | { |
| 837 | uint16_t i; |
| 838 | uint32_t t; |
| 839 | |
Richard Spiegel | ef73cb8 | 2018-06-19 07:40:18 -0700 | [diff] [blame] | 840 | if (limit >= TOTAL_BITS(uint32_t)) |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 841 | return -1; |
| 842 | |
| 843 | /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ |
| 844 | t = (1 << limit) - 1; |
| 845 | if ((value & t) == 0) |
| 846 | return -1; |
| 847 | t = 1; |
| 848 | for (i = 0; i < limit; i++) { |
| 849 | if (value & t) |
| 850 | break; |
| 851 | t <<= 1; |
| 852 | } |
| 853 | return i; |
| 854 | } |
| 855 | |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 856 | static void set_nvs_sws(void *unused) |
| 857 | { |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 858 | struct soc_power_reg *sws; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 859 | struct global_nvs_t *gnvs; |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 860 | int index; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 861 | |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 862 | sws = cbmem_find(CBMEM_ID_POWER_STATE); |
| 863 | if (sws == NULL) |
| 864 | return; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 865 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 866 | if (gnvs == NULL) |
| 867 | return; |
| 868 | |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 869 | index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT); |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 870 | if (index < 0) |
| 871 | gnvs->pm1i = ~0ULL; |
| 872 | else |
| 873 | gnvs->pm1i = index; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 874 | |
Richard Spiegel | 35282a0 | 2018-06-14 14:57:54 -0700 | [diff] [blame] | 875 | index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT); |
Richard Spiegel | 572f498 | 2018-05-25 15:49:33 -0700 | [diff] [blame] | 876 | if (index < 0) |
| 877 | gnvs->gpei = ~0ULL; |
| 878 | else |
| 879 | gnvs->gpei = index; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); |
| 883 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 884 | void southbridge_init(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 885 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 886 | sb_init_acpi_ports(); |
Marshall Dawson | 70f051f | 2018-03-20 10:27:41 -0600 | [diff] [blame] | 887 | sb_clear_pm1_status(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 888 | } |
| 889 | |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 890 | static void set_sb_final_nvs(void) |
| 891 | { |
| 892 | uintptr_t amdfw_rom; |
| 893 | uintptr_t xhci_fw; |
| 894 | uintptr_t fwaddr; |
| 895 | size_t fwsize; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 896 | const struct device *sd, *sata; |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 897 | |
| 898 | struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 899 | if (gnvs == NULL) |
| 900 | return; |
| 901 | |
| 902 | gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); |
| 903 | gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); |
| 904 | gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); |
| 905 | gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); |
| 906 | gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); |
| 907 | gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); |
| 908 | gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2); |
| 909 | gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); |
| 910 | /* Rely on these being in sync with devicetree */ |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 911 | sd = pcidev_path_on_root(SD_DEVFN); |
Marshall Dawson | 6d3b7e6 | 2019-04-18 17:01:01 -0600 | [diff] [blame] | 912 | gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 913 | sata = pcidev_path_on_root(SATA_DEVFN); |
Marshall Dawson | 6d3b7e6 | 2019-04-18 17:01:01 -0600 | [diff] [blame] | 914 | gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 915 | gnvs->aoac.espi = 1; |
| 916 | |
| 917 | amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); |
| 918 | xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); |
| 919 | |
| 920 | fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET |
| 921 | + XHCI_FW_BOOTRAM_SIZE)); |
| 922 | fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET |
| 923 | + XHCI_FW_BOOTRAM_SIZE)); |
| 924 | gnvs->fw00 = 0; |
| 925 | gnvs->fw01 = ((32 * KiB) << 16) + 0; |
| 926 | gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; |
| 927 | gnvs->fw03 = fwsize << 16; |
| 928 | |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 929 | gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) |
| 930 | & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 931 | } |
| 932 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 933 | void southbridge_final(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 934 | { |
Richard Spiegel | 6a38914 | 2018-03-05 14:28:10 -0700 | [diff] [blame] | 935 | uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; |
| 936 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 937 | if (CONFIG(MAINBOARD_POWER_RESTORE)) |
Richard Spiegel | 6a38914 | 2018-03-05 14:28:10 -0700 | [diff] [blame] | 938 | restored_power = PM_RESTORE_S0_IF_PREV_S0; |
| 939 | pm_write8(PM_RTC_SHADOW, restored_power); |
Marshall Dawson | 1d9a46b | 2018-09-26 16:23:41 -0600 | [diff] [blame] | 940 | |
| 941 | set_sb_final_nvs(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 942 | } |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 943 | |
| 944 | /* |
| 945 | * Update the PCI devices with a valid IRQ number |
| 946 | * that is set in the mainboard PCI_IRQ structures. |
| 947 | */ |
| 948 | static void set_pci_irqs(void *unused) |
| 949 | { |
| 950 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 951 | write_pci_int_table(); |
| 952 | |
| 953 | /* Write IRQs for all devicetree enabled devices */ |
| 954 | write_pci_cfg_irqs(); |
| 955 | } |
| 956 | |
| 957 | /* |
| 958 | * Hook this function into the PCI state machine |
| 959 | * on entry into BS_DEV_ENABLE. |
| 960 | */ |
| 961 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |