Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 73a544d4533fa8305f1c0a809137b5e2151ea17e
commit73a544d4533fa8305f1c0a809137b5e2151ea17e[log] [tgz]
authorMichał Żygowski <michal.zygowski@3mdeb.com>Sun Nov 24 14:16:34 2019 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>Wed Dec 04 12:23:50 2019 +0000
treee7d0b63098c2d021b579599a9ce419d3ced9db52
parentc08fdf3decc6a61a9020a7df484d92473f7223e9 [diff]
soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable function

According to BKDGs for families 15h 60-6fh or newer and families 16h the
ACPI MMIO decode enable bit is the second LSB, not the first LSB.

Additionally create another enable function for older families where
the register and bit is different.

It does not seem to impact any current board, but may be crucial for
incoming C bootblock implementations when this bit will need to be set
very early. Most likely this bit is set by AGESA right now.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5 files changed
tree: e7d0b63098c2d021b579599a9ce419d3ced9db52
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. src/
  7. util/
  8. .checkpatch.conf
  9. .clang-format
  10. .editorconfig
  11. .gitignore
  12. .gitmodules
  13. .gitreview
  14. AUTHORS
  15. COPYING
  16. gnat.adc
  17. MAINTAINERS
  18. Makefile
  19. Makefile.inc
  20. README.md
  21. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.