Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <arch/acpi.h> |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 20 | #include <bootstate.h> |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame^] | 21 | #include <cpu/x86/smm.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <device/pci_ops.h> |
| 26 | #include <cbmem.h> |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 27 | #include <amd_pci_util.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 28 | #include <soc/southbridge.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 29 | #include <soc/smbus.h> |
| 30 | #include <soc/smi.h> |
| 31 | #if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) |
| 32 | #include <fchec.h> |
| 33 | #endif |
| 34 | |
| 35 | |
| 36 | int acpi_get_sleep_type(void) |
| 37 | { |
| 38 | u16 tmp = inw(ACPI_PM1_CNT_BLK); |
| 39 | tmp = ((tmp & (7 << 10)) >> 10); |
| 40 | return (int)tmp; |
| 41 | } |
| 42 | |
| 43 | void pm_write8(u8 reg, u8 value) |
| 44 | { |
| 45 | write8((void *)(PM_MMIO_BASE + reg), value); |
| 46 | } |
| 47 | |
| 48 | u8 pm_read8(u8 reg) |
| 49 | { |
| 50 | return read8((void *)(PM_MMIO_BASE + reg)); |
| 51 | } |
| 52 | |
| 53 | void pm_write16(u8 reg, u16 value) |
| 54 | { |
| 55 | write16((void *)(PM_MMIO_BASE + reg), value); |
| 56 | } |
| 57 | |
| 58 | u16 pm_read16(u16 reg) |
| 59 | { |
| 60 | return read16((void *)(PM_MMIO_BASE + reg)); |
| 61 | } |
| 62 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 63 | void sb_enable(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 64 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 65 | printk(BIOS_DEBUG, "%s\n", __func__); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 66 | } |
| 67 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 68 | static void sb_init_acpi_ports(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 69 | { |
| 70 | /* We use some of these ports in SMM regardless of whether or not |
| 71 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 72 | */ |
| 73 | |
| 74 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 75 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 76 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 77 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
| 78 | /* CpuControl is in \_PR.CP00, 6 bytes */ |
| 79 | pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); |
| 80 | |
| 81 | if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame^] | 82 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 83 | enable_acpi_cmd_smi(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 84 | } else { |
| 85 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 86 | } |
| 87 | |
| 88 | /* AcpiDecodeEnable, When set, SB uses the contents of the PM registers |
| 89 | * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn |
| 90 | */ |
| 91 | pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2)); |
| 92 | } |
| 93 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 94 | void southbridge_init(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 95 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 96 | sb_init_acpi_ports(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 97 | } |
| 98 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 99 | void southbridge_final(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 100 | { |
| 101 | #if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) |
| 102 | agesawrapper_fchecfancontrolservice(); |
| 103 | #if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) |
| 104 | enable_imc_thermal_zone(); |
| 105 | #endif |
| 106 | #endif |
| 107 | } |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 108 | |
| 109 | /* |
| 110 | * Update the PCI devices with a valid IRQ number |
| 111 | * that is set in the mainboard PCI_IRQ structures. |
| 112 | */ |
| 113 | static void set_pci_irqs(void *unused) |
| 114 | { |
| 115 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 116 | write_pci_int_table(); |
| 117 | |
| 118 | /* Write IRQs for all devicetree enabled devices */ |
| 119 | write_pci_cfg_irqs(); |
| 120 | } |
| 121 | |
| 122 | /* |
| 123 | * Hook this function into the PCI state machine |
| 124 | * on entry into BS_DEV_ENABLE. |
| 125 | */ |
| 126 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |