Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <arch/acpi.h> |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 20 | #include <bootstate.h> |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 21 | #include <cpu/x86/smm.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <device/pci_ops.h> |
| 26 | #include <cbmem.h> |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 27 | #include <amd_pci_util.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 28 | #include <soc/southbridge.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 29 | #include <soc/smbus.h> |
| 30 | #include <soc/smi.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 31 | #include <fchec.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 32 | |
| 33 | |
| 34 | int acpi_get_sleep_type(void) |
| 35 | { |
| 36 | u16 tmp = inw(ACPI_PM1_CNT_BLK); |
| 37 | tmp = ((tmp & (7 << 10)) >> 10); |
| 38 | return (int)tmp; |
| 39 | } |
| 40 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 41 | void sb_enable(device_t dev) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 42 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 43 | printk(BIOS_DEBUG, "%s\n", __func__); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 44 | } |
| 45 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 46 | static void sb_init_acpi_ports(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 47 | { |
| 48 | /* We use some of these ports in SMM regardless of whether or not |
| 49 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 50 | */ |
| 51 | |
| 52 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 53 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 54 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 55 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
| 56 | /* CpuControl is in \_PR.CP00, 6 bytes */ |
| 57 | pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); |
| 58 | |
| 59 | if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame^] | 60 | /* APMC - SMI Command Port */ |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 61 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
Marshall Dawson | a05fdcb | 2017-09-27 15:01:37 -0600 | [diff] [blame^] | 62 | configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 63 | } else { |
| 64 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 65 | } |
| 66 | |
| 67 | /* AcpiDecodeEnable, When set, SB uses the contents of the PM registers |
| 68 | * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn |
| 69 | */ |
| 70 | pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2)); |
| 71 | } |
| 72 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 73 | void southbridge_init(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 74 | { |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 75 | sb_init_acpi_ports(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 76 | } |
| 77 | |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 78 | void southbridge_final(void *chip_info) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 79 | { |
Richard Spiegel | 38f1940 | 2017-09-29 11:39:46 -0700 | [diff] [blame] | 80 | if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) { |
| 81 | agesawrapper_fchecfancontrolservice(); |
| 82 | if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) |
| 83 | enable_imc_thermal_zone(); |
| 84 | } |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 85 | } |
Marshall Dawson | 8a906df | 2017-06-13 14:19:02 -0600 | [diff] [blame] | 86 | |
| 87 | /* |
| 88 | * Update the PCI devices with a valid IRQ number |
| 89 | * that is set in the mainboard PCI_IRQ structures. |
| 90 | */ |
| 91 | static void set_pci_irqs(void *unused) |
| 92 | { |
| 93 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 94 | write_pci_int_table(); |
| 95 | |
| 96 | /* Write IRQs for all devicetree enabled devices */ |
| 97 | write_pci_cfg_irqs(); |
| 98 | } |
| 99 | |
| 100 | /* |
| 101 | * Hook this function into the PCI state machine |
| 102 | * on entry into BS_DEV_ENABLE. |
| 103 | */ |
| 104 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |