commit a0ff6fc860b8738920366e4f4e328134ffd982d0
author Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Tue Mar 06 09:23:47 2018 -0600
committer Martin Roth <martinroth@google.com> Wed Mar 07 17:55:12 2018 +0000
tree 6b9a51f41bddaa1a63767c1dfd76e6ca04510b0e
parent d2558304183e3f79e2dfbfdab4c1b78f8f222217

soc/amd/stoneyridge: clean up southbridge.c

* Limit dependency on vendorcode header files and use defines from
  iomap.h and southbridge.h
* Factor out to functions, device power-on code for AMBA and UART.

BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt

Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

src/soc/amd/stoneyridge/southbridge.c

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 47f15cd..d2495a6 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -272,23 +272,38 @@
 	return index;
 }
 
-void configure_stoneyridge_uart(void)
+static void power_on_aoac_device(int aoac_device_control_register)
 {
-	u8 byte, byte2;
-
-	if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1)
-		return;
+	uint8_t byte;
+	uint8_t *register_pointer = (uint8_t *)(uintptr_t)AOAC_MMIO_BASE
+			+ aoac_device_control_register;
 
 	/* Power on the UART and AMBA devices */
-	byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56
-					+ CONFIG_UART_FOR_CONSOLE * 2);
-	byte |= AOAC_PWR_ON_DEV;
-	write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56
-					+ CONFIG_UART_FOR_CONSOLE * 2, byte);
+	byte = read8(register_pointer);
+	byte |= FCH_AOAC_PWR_ON_DEV;
+	write8(register_pointer, byte);
+}
 
-	byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62);
-	byte |= AOAC_PWR_ON_DEV;
-	write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte);
+static bool is_aoac_device_enabled(int aoac_device_status_register)
+{
+	uint8_t byte;
+	byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE
+			+ aoac_device_status_register);
+	byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE);
+	if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE))
+		return true;
+	else
+		return false;
+}
+
+void configure_stoneyridge_uart(void)
+{
+	bool status;
+
+	/* Power on the UART and AMBA devices */
+	power_on_aoac_device(FCH_AOAC_D3_CONTROL_UART0
+			+ CONFIG_UART_FOR_CONSOLE * 2);
+	power_on_aoac_device(FCH_AOAC_D3_CONTROL_AMBA);
 
 	/* Set the GPIO mux to UART */
 	write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
@@ -299,15 +314,10 @@
 	/* Wait for the UART and AMBA devices to indicate power and clock OK */
 	do {
 		udelay(100);
-		byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57
+		status = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0
 					+ CONFIG_UART_FOR_CONSOLE * 2);
-		byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);
-		byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE
-					+ FCH_AOAC_REG63);
-		byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);
-	} while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) &&
-		   (byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE))));
-
+		status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_AMBA);
+	} while (!status);
 }
 
 void sb_pci_port80(void)