src/soc/amd/stoneyridge: Remove IMC support
Per AMD, the Integrated Micro Controller is not a supported feature of
the Stoney Ridge APU. Systems are expected to implement an external EC
for desired features. Remove all stoney IMC files and functions from
src/soc/amd/stoneyridge.
There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG
describe these bits, so a new patch will be released later to fix the
names and comment.
BUG=b:111780177
TEST=Build grunt and gardenia
Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27651
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 18e6c6c..63d8806 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -25,10 +25,10 @@
#include <cbmem.h>
#include <elog.h>
#include <amdblocks/amd_pci_util.h>
+#include <amdblocks/agesawrapper.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
#include <soc/amd_pci_int_defs.h>
-#include <fchec.h>
#include <delay.h>
#include <soc/pci_devs.h>
#include <agesa_headers.h>
@@ -123,12 +123,6 @@
{ PIRQ_PMON, "PerMon" },
{ PIRQ_SD, "SD" },
{ PIRQ_SDIO, "SDIOt" },
- { PIRQ_IMC0, "IMC INT0" },
- { PIRQ_IMC1, "IMC INT1" },
- { PIRQ_IMC2, "IMC INT2" },
- { PIRQ_IMC3, "IMC INT3" },
- { PIRQ_IMC4, "IMC INT4" },
- { PIRQ_IMC5, "IMC INT5" },
{ PIRQ_EHCI, "EHCI" },
{ PIRQ_XHCI, "XHCI" },
{ PIRQ_SATA, "SATA" },
@@ -766,11 +760,6 @@
{
uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;
- if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) {
- agesawrapper_fchecfancontrolservice();
- if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE))
- enable_imc_thermal_zone();
- }
if (IS_ENABLED(CONFIG_MAINBOARD_POWER_RESTORE))
restored_power = PM_RESTORE_S0_IF_PREV_S0;
pm_write8(PM_RTC_SHADOW, restored_power);