commit 939bfccb3dbf04a0a2f7e15b82db1fdb469b7a73
author Marshall Dawson <marshalldawson3rd@gmail.com> Sun May 05 15:39:40 2019 -0600
committer Martin Roth <martinroth@google.com> Fri May 10 17:35:18 2019 +0000
tree c19c99337abf8416866d32f3430bb43df8439592
parent f36fcdf2ab6a9956ac60012404e0edf1d6653fac

soc/amd/stoneyridge: Add IO access functions for PMx

Replace locations in the source that explicitely use the CD6/CD7
index/data pair with utility function calls.

Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/amd/stoneyridge/southbridge.c

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index b590178..8dfef8b 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -329,11 +329,9 @@
 	u8 byte;
 
 	/* Enable LPC controller */
-	outb(PM_LPC_GATING, PM_INDEX);
-	byte = inb(PM_DATA);
+	byte = pm_io_read8(PM_LPC_GATING);
 	byte |= PM_LPC_ENABLE;
-	outb(PM_LPC_GATING, PM_INDEX);
-	outb(byte, PM_DATA);
+	pm_io_write8(PM_LPC_GATING, byte);
 
 	/* Enable port 80 LPC decode in pci function 3 configuration space. */
 	byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
@@ -367,11 +365,9 @@
 	uint8_t byte;
 
 	/* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */
-	outb(PM_ISA_CONTROL, PM_INDEX);
-	byte = inb(PM_DATA);
+	byte = pm_io_read8(PM_ISA_CONTROL);
 	byte |= MMIO_EN;
-	outb(PM_ISA_CONTROL, PM_INDEX);
-	outb(byte, PM_DATA);
+	pm_io_write8(PM_ISA_CONTROL, byte);
 }
 
 static void sb_enable_cf9_io(void)